EP0551323A1 - Liaison assistee par champ - Google Patents

Liaison assistee par champ

Info

Publication number
EP0551323A1
EP0551323A1 EP91917115A EP91917115A EP0551323A1 EP 0551323 A1 EP0551323 A1 EP 0551323A1 EP 91917115 A EP91917115 A EP 91917115A EP 91917115 A EP91917115 A EP 91917115A EP 0551323 A1 EP0551323 A1 EP 0551323A1
Authority
EP
European Patent Office
Prior art keywords
voltage
interface
workpieces
substrate
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91917115A
Other languages
German (de)
English (en)
Inventor
Tony William James 142 Bath Road Rogers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BTG International Ltd
Original Assignee
BTG International Ltd
British Technology Group Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BTG International Ltd, British Technology Group Ltd filed Critical BTG International Ltd
Publication of EP0551323A1 publication Critical patent/EP0551323A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Definitions

  • FIELD-ASSISTED BONDING This invention relates to a method of bonding workpieces together by the field-assisted bonding process known as electrostatic bonding, anodic bonding or Mallory bonding.
  • two workpieces which are to be bonded together are positioned 1n contact with one another at a common Interface, the workpieces are maintained at least at their interface at an elevated temperature, and a voltage is applied between them so as to establish at the interface an electrostatic attraction which forces the workplece surfaces into intimate contact with one another and causes them to bond to one another, whereafter the voltage is removed and the workpieces are allowed to cool.
  • the process is commonly employed in bonding a silicon or other semiconductive wafer to a glass substrate, the voltage being so applied as to make the semiconductive wafer electrically positive relative to the glass; and it may also be used for bonding one glass to another if the positive voltage is applied to the glass having the greater alkali content.
  • a semiconductive wafer has an operative or diaphragm region, which is parallel to but spaced from a glass substrate surface, and a surrounding region which is bonded to the substrate surface to provide a hermetically sealed cavity between the diaphragm region of the wafer and the corresponding part of the substrate surface.
  • the spacing of the diaphragm region of the wafer from the substrate surface may be achieved either by machining or etching a well or recess in the wafer surface or by depositing an intimately adherent upstanding surrounding ring of Insulating material, such as silicon nitride, on either the wafer or the 75
  • the substrate surface within the cavity may have deposited upon it a metal electrode layer forming with the wafer diaphragm, as described, for example, in our international patent application No. WO91/10120, a capacitor whose changes in capacitance indicate changes in the cavity depth and thus accelerations or pressure changes which are to be measured.
  • WO91/10120 a capacitor whose changes in capacitance indicate changes in the cavity depth and thus accelerations or pressure changes which are to be measured.
  • Another cavity device of the kind here in question is described in our international patent application No. W091/10119.
  • the ionic movement produces a change in the composition of the substrate at and adjacent the interface, where a depletion of mobile ionic species such as lithium occurs, and also at the opposite face and in the body of the substrate, where an increased concentration of the mobile ionic species results.
  • the composition of the substrate is normally chosen to give a thermal expansion characteristic which matches that of the semiconductor wafer almost exactly; but the redistribution of ionic concentration results in this matching being lost and also in a variation of the physical properties of the substrate across its thickness.
  • the depleted substrate region at and near the interface has a reduced thermal coefficient of expansion, whereas the coefficient at and near the opposite face Increases.
  • this bowing may be of the order of hundreds of micrometres, and even in a smaller assembly the amount of bowing, between the periphery and the centre of the cavity formed between the substrate and the wafer, may be equal to a significant fraction of the nominal depth of the cavity.
  • Such bowing of the bonded assembly is undesirable for several reasons. Firstly, it produces a distortion of the nominal shape and dimensions of the cavity between the wafer and the substrate, which may affect, to an unpredictable and variable degree, the characteristics and performance of the device in use. Secondly, the bonding operation may be followed by other operations (such as lapping the semiconductor wafer to reduce Its thickness, thereby to convert its operative region bounding the cavity into a diaphragm of accurately controlled thickness) which require the use of the opposite, exposed surface of the substrate as a reference plane from which to gauge the wafer thickness, and any bowing of the nominally flat reference surface must reduce the accuracy of such operations.
  • other operations such as lapping the semiconductor wafer to reduce Its thickness, thereby to convert its operative region bounding the cavity into a diaphragm of accurately controlled thickness
  • a method of bonding together two workpieces comprising the steps of positioning the workpieces in contact with one another at a common interface, maintaining at least their interface at an elevated temperature, applying a substantial first voltage between them so as to establish at the interface an electrostatic attraction which forces the workpiece surfaces Into Intimate contact with one another and causes them to bond to one another, and thereafter removing the applied voltage and allowing the workpieces to cool, characterised by the additional step, after application of the first voltage and while still maintaining the said interface at elevated temperature, of applying between the workpieces a second voltage of opposite polarity to the first voltage.
  • the magnitude of the second applied voltage Is at least approximately equal to that of the first voltage, though of opposite polarity, and the reversed-polarity second voltage is applied for a period at least approximately equal to that during which the bond-assisting first voltage is applied.
  • the effect of applying the second voltage, with reversed polarity appears to be to reverse the direction of the migration of mobile ions which has occurred, as described above, during application of the bond-assisting first voltage.
  • the workpieces being bonded are respectively a semiconductor wafer and a glass substrate
  • the mobile ion depletion in the substrate at and near the interface, and the build-up of a mobile ion excess in other parts of the substrate are reversed and the compositional homogeneity of the substrate is in large measure restored during the period of application of the reversed-polarity second voltage.
  • the uniformity of the substrate in terms of thermal coefficient of expansion is also in large measure restored, with the result that, when the second voltage is removed and the bonded assembly is allowed to cool, the substrate contracts uniformly and virtually without any bowing or other distortion.
  • bonded assemblies which, without application of the reversed polarity voltage in accordance with the invention might have shown bowing of hundreds of micrometres as mentioned above, have been obtained with a bowing of as little as 2 micrometres when made in accordance with the invention.
  • the composition of the substrate has been chosen to match Its thermal coefficient of expansion to that of the semiconductor wafer being bonded to it, this matching is not lost when the bonding is effected by the method of invention, and, as intended, the bond is therefore not subjected to substantial stresses due to differential contraction rates as the bonded assembly cools.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Sensors (AREA)

Abstract

L'invention se rapporte à un procédé de liaison de deux pièces, dont au moins une est (ou bien a une surface) constituée d'un matériau pratiquement non conducteur électriquement, au moyen d'un procédé de liaison assisté par champ, connu sous le nom de liaison électrostatique, qui comprend les étapes suivantes: mise en contact des pièces l'une avec l'autre par une interface commune, maintien d'au moins leur interface à une température élevée, application d'une première tension importante entre elles pour établir, à l'interface, une attraction électrostatique provoquant un contact étroit des surfaces des pièces entre elles et leur liaison, et, ensuite, suppression de la tension appliquée et refroidissement des pièces. Selon l'invention, on améliore ce procédé en incluant l'étape supplémentaire, après application de la première tension et tout en maintenant ladite interface à une température élevée, étape qui consiste à appliquer entre les pièces une deuxième tension à polarité opposée à celle de la première tension.
EP91917115A 1990-09-26 1991-09-26 Liaison assistee par champ Withdrawn EP0551323A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9020908 1990-09-26
GB909020908A GB9020908D0 (en) 1990-09-26 1990-09-26 Field-assisted bonding

Publications (1)

Publication Number Publication Date
EP0551323A1 true EP0551323A1 (fr) 1993-07-21

Family

ID=10682759

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91917115A Withdrawn EP0551323A1 (fr) 1990-09-26 1991-09-26 Liaison assistee par champ

Country Status (4)

Country Link
EP (1) EP0551323A1 (fr)
JP (1) JPH06504877A (fr)
GB (1) GB9020908D0 (fr)
WO (1) WO1992005575A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0539741B1 (fr) * 1991-09-30 2003-01-15 Canon Kabushiki Kaisha Procédé de liaison anodique à radiation de lumière
FR2715502B1 (fr) * 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure présentant des cavités et procédé de réalisation d'une telle structure.
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4285714A (en) * 1978-12-07 1981-08-25 Spire Corporation Electrostatic bonding using externally applied pressure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9205575A1 *

Also Published As

Publication number Publication date
GB9020908D0 (en) 1990-11-07
JPH06504877A (ja) 1994-06-02
WO1992005575A1 (fr) 1992-04-02

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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17P Request for examination filed

Effective date: 19930414

AK Designated contracting states

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Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 19940923

STAA Information on the status of an ep patent application or granted ep patent

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18D Application deemed to be withdrawn

Effective date: 19950204