EP0543197A2 - Mémoire à accès séquentiel multiple utilisée dans des systèmes rébouclés, telle qu'une image de télévision, compensée en mouvement - Google Patents

Mémoire à accès séquentiel multiple utilisée dans des systèmes rébouclés, telle qu'une image de télévision, compensée en mouvement Download PDF

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Publication number
EP0543197A2
EP0543197A2 EP92118660A EP92118660A EP0543197A2 EP 0543197 A2 EP0543197 A2 EP 0543197A2 EP 92118660 A EP92118660 A EP 92118660A EP 92118660 A EP92118660 A EP 92118660A EP 0543197 A2 EP0543197 A2 EP 0543197A2
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EP
European Patent Office
Prior art keywords
data
array
memory
frame
serial output
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Granted
Application number
EP92118660A
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German (de)
English (en)
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EP0543197A3 (fr
EP0543197B1 (fr
Inventor
Paul Shen
Woo H. Paik
Edward A. Krause
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Arris Technology Inc
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Arris Technology Inc
General Instrument Corp
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Priority to EP98105936A priority Critical patent/EP0862333B1/fr
Publication of EP0543197A2 publication Critical patent/EP0543197A2/fr
Publication of EP0543197A3 publication Critical patent/EP0543197A3/xx
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Definitions

  • HDTV high definition television
  • a subscriber receives the digital data stream via a receiver/descrambler that provides video, audio, and data to the subscriber.
  • a receiver/descrambler that provides video, audio, and data to the subscriber.
  • Video compression techniques enable the efficient transmission of digital video signals over conventional communication channels. Such techniques use compression algorithms that take advantage of the correlation among adjacent pixels in order to derive a more efficient representation of the important information in a video signal.
  • the most powerful compression systems not only take advantage of spatial correlation, but can also utilize similarities among adjacent frames to further compact the data.
  • the encoder reproduces the same prediction frame as the decoder, and then sends the differences between the prediction frame and the actual frame.
  • the amount of information needed to represent the image sequence can be significantly reduced, particularly when the motion estimation model closely resembles the frame to frame changes that actually occur.
  • This technique can result in a significant reduction in the amount of data that needs to be transmitted once simple coding algorithms are applied to the prediction error signal.
  • An example of such a motion compensated video compression system is described by Ericsson in "Fixed and Adaptive Predictors for Hybrid Predictive/Transform Coding," IEEE Transactions on Communications , Vol. COM-33, No. 12, December 1985.
  • An improvement to the system described by Ericsson is disclosed in commonly assigned U.S. patent no. 5,057,916 entitled “Method and Apparatus for Refreshing Motion Compensated Sequential Video Images.”
  • Motion compensated television systems require the storage of both current frame and previous frame video data to implement the differential encoding technique described above. Specifically, prior frame data must be summed with a transmitted difference signal to recreate a full current frame for display. The full current frame must be stored for subsequent use in recreating the next frame from a received difference signal.
  • a dual memory bank system has been used to implement such systems. The same data is stored in both memory banks, allowing it to be accessed independently from each bank. Such an implementation, however, is costly, particularly in HDTV systems where large amounts of memory are required.
  • a multiple serial access memory includes a dynamic random access memory array. Means are provided for addressing the array to input data thereto and output data therefrom. Rows of data are output from the array in response to address signals provided by the addressing means. A plurality of serial output ports, coupled to the outputting means, selectively latch different rows of data output by the outputting means. Means are provided for clocking the serial output ports to output latched data therefrom.
  • each of the serial output ports comprises a shift register having a length at least equal to a width of the array.
  • the shift register is responsive to a first signal from a timing means for latching a row of data from the array.
  • the shift register is responsive to a second signal from the timing means for shifting the row of latched data.
  • a serial access selector coupled to the shift register outputs a selected portion of the shifted data from the serial output port.
  • a digital television apparatus is also provided in accordance with the present invention.
  • the apparatus is a type which requires memory for storing a set of working data, such as pixel data from a previous video frame.
  • the apparatus also requires memory for storing a set of display data (e.g., representing a current video frame) derived from the working data.
  • the invention provides a dynamic random access memory array for the television apparatus. Means are provided for addressing the array to input data thereto and output data therefrom. Rows of data are output from the array in response to address signals provided by the addressing means.
  • a plurality of serial output ports coupled to the outputting means selectively latch rows of data output by the outputting means. Means are provided for clocking the serial output ports to output latched data therefrom. At least one of the serial output ports is used to output working data from the array. At least one other of the serial output ports is used to output display data from the array.
  • Timing means can be operatively associated with the array of the television apparatus for limiting access to the array to one of the serial output ports at a time. Alternatively, several serial output ports can concurrently latch the same data.
  • each of the serial output ports comprises a shift register having a length at least equal to a width of the array.
  • the shift register is responsive to a first signal from a timing means for latching a row of data from the array.
  • the shift register is responsive to a second signal from the timing means for shifting the row of latched data.
  • a serial access selector coupled to the shift register outputs a selected portion of the shifted data from the serial output port.
  • the working data is accessed from the array by its respective serial output port in a block format.
  • the display data is accessed from the array by its respective serial output port in a television line format.
  • the array has a storage capacity sufficient to store the current video frame together with enough working data to accommodate a predetermined motion estimation search area.
  • the array is filled with data for successive video frames on an ongoing basis, with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.
  • a method in accordance with the present invention stores video data for use by a motion compensator that estimates motion over a maximum horizontal displacement DX and a maximum vertical displacement DY.
  • a frame store memory is provided for storing N+K lines of video data, where N is the number of lines in a video frame and K is at least equal to the number of lines corresponding to the vertical displacement DY.
  • the frame store memory is filled with video data from successive video frames on a revolving basis. N consecutive lines of a second video frame are written into the memory following the last line of a first video frame. In this manner, the first video frame is overwritten by the second video frame on a first-in first-out basis, with the last K lines of the first video frame remaining in the memory once the full second video frame has been written into the memory.
  • the addresses are input to a memory 16, which serves as a frame store.
  • a motion compensation difference signal is input to a summer 20 via terminal 12.
  • Summer 20 adds the difference signal to the previous frame data w that was used to generate the difference signal in the first place, to recover the current frame video data u .
  • u _ address identifies where the current pixel is located in a video frame stored in memory 16. Thus, it is the memory address for that pixel.
  • w _ address is the estimated location of that pixel in the previous frame, also stored in memory 16.
  • u _ address u _ address + mv, where mv is the motion vector.
  • the address of the displayed data v is not the same as the address of the current data u .
  • an interlaced television system may use field scanning for display and frame scanning for processing.
  • field scanning the odd numbered horizontal television lines are processed as a first field, and the even numbered lines are processed as a second field.
  • the two fields are interleaved so that the horizontal lines are in the proper order.
  • frame scanning all of the television lines are processed together, in order, as a single video frame.
  • the displayed data v is obtained by selecting every second line only.
  • the current data u must be written into memory in a nonsequential order.
  • u _ address may also differ from v _ address in a noninterlaced television system. For example, this may result from the block-by-block processing that is common in video compression systems.
  • the displayed data v would still be accessed one line at a time while the current data u and the previous frame data w are accessed one block at a time.
  • Common block sizes for such processing are 8 x 8 pixels and 16 x 16 pixels.
  • the DRAM contains a conventional random access port 32 for inputting data (DIN), a dynamic RAM array 30, and row and column decoders 36, 38 for accessing the array via an address input 34.
  • the address input is also coupled to a plurality of serial output ports 44, 46, 48 that receive data via output bus 50 from the DRAM array 30.
  • serial output ports are illustrated in Figure 3, it should be appreciated that fewer or more such ports can be provided.
  • serial output ports The operation of the serial output ports is controlled by a timing generator 42 that is responsive to control signals 40.
  • Serial clocks input to each of the serial output ports control the output of data from each port to a respective output buffer 54, 56, 58.
  • DRAM array 30 is P rows high by Q columns wide by B bits deep.
  • the output from each output buffer is therefore a B-bit byte, although other implementations will be apparent to those skilled in the art.
  • the individual control signals 40 input to timing generator 42 include a row access signal RAS ⁇ , a column access signal CAS ⁇ , a write enable signal WE ⁇ , and a separate data transfer signal for each serial output port, DT -1 ⁇ to DT - N ⁇ .
  • Timing diagrams for each of the signals in the data transfer mode of operation are illustrated in Figure 6.
  • Timing diagrams for a data write cycle are illustrated in Figure 7.
  • Serial port access consists of two steps. These are referred to as “setup” and “readout.”
  • a load signal carried on line 52 from timing generator 42 ( Figure 3) is set high. This latches the selected row of data from DRAM 30 into the shift register comprising cells 62, 64, 66 ... 68.
  • the serial access selector 70 is responsive to a column address input coupled via terminal 72 to output the latched data, commencing from one of the shift register cells identified by the column address input. In other words, although an entire row of data is latched into the shift register when the load signal goes high, it is not necessary to output the entire row of data from the serial access selector.
  • serial access selector in accordance with the present invention is illustrated in greater detail in Figure 5.
  • the column address input is latched in a serial address register 74 when the load signal goes low.
  • multiplexer 76 will initially output the first byte of data from the cell pointed to by the column address, and continue to output successive bytes of data that are shifted into the designated cell from successive cells of the shift register.
  • serial access to a serial port is independent of other serial and random access ports in the multiple access memory of Figure 3.
  • a random access port cannot be used at the same time a serial output port is latching data from the array.
  • serial clocks 90, 96, and 102 for each of the three serial output ports illustrated are used, as described above, to clock data out from the serial output ports to the output buffers 54, 56, 58.
  • Column access signal CAS ⁇ 82 controls the output of the column address as indicated at 84. The row address is output when RAS ⁇ goes low.
  • a write enable signal WE ⁇ shown at 86 controls the writing of data into DRAM array 30.
  • a feedback system as illustrated in Figure 1 can be easily implemented by using the multiple serial access DRAM of the present invention.
  • Memory 16 is the multiple serial access DRAM illustrated in Figure 3.
  • the current data u is input to the random access port 32.
  • the output data v is obtained from one of the serial output ports 44, 46, 48.
  • the feedback data w is obtained from another serial output port.
  • the multiple access memory of the present invention in a television system, where motion compensation is not used, it is possible to equate the addresses of the current frame data u and the previous frame data w .
  • the previous frame data is simply summed with the new input data and then written back into the same memory address.
  • the previous frame address is derived by adding a motion vector displacement to the current frame address, it becomes necessary to isolate the two video frames. Otherwise, since the motion vector can be unpredictable and may vary from one region to the next, it is very likely that the current frame data will overwrite the previous frame data that is required to predict the value of the pixels which follow.
  • the additional memory that is required can be expressed as: DX + DY * M * b, where DX and DY are the maximum horizontal and vertical displacements, respectively, of the motion estimator. M is the number of pixels in each line of video, and b is the number of bits used to represent each pixel sample.
  • the amount of additional memory required is rounded up to simplify the design, and expressed as a number of lines such that the required extra memory equals DY + 1 .
  • an NTSC video compression system consisting of 480 lines of active video, and having a motion estimator vertical displacement limited to 31 lines, can be implemented using a 512 line frame memory.
  • a 1050 line high definition video compression system that contains 960 lines of active video and uses a maximum vertical displacement of 63 lines, can be implemented using a 1024 line frame memory.
  • w _ address u_address + mv - K * M.
  • mv is the motion vector
  • K is the number of extra lines provided for in the frame memory 130
  • M is the number of pixels per line. Since a frame of video may be split across the frame memory boundaries, it is necessary to use the modulo remainder of (N + K) * M (i.e., the frame memory size) when deriving the previous frame address.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Input (AREA)
  • Dram (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
  • Information Transfer Systems (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Hydrogenated Pyridines (AREA)
  • Other In-Based Heterocyclic Compounds (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Television Signal Processing For Recording (AREA)
EP92118660A 1991-11-19 1992-10-31 Système de télévision comportant une mémoire à accès séquentiel multiple Expired - Lifetime EP0543197B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98105936A EP0862333B1 (fr) 1991-11-19 1992-10-31 Procédé pour stocker des données vidéo et système de télévision correspondant

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US791369 1991-11-19
US07/791,369 US5315388A (en) 1991-11-19 1991-11-19 Multiple serial access memory for use in feedback systems such as motion compensated television

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EP98105936A Division EP0862333B1 (fr) 1991-11-19 1992-10-31 Procédé pour stocker des données vidéo et système de télévision correspondant

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EP0543197A2 true EP0543197A2 (fr) 1993-05-26
EP0543197A3 EP0543197A3 (fr) 1994-04-20
EP0543197B1 EP0543197B1 (fr) 1998-12-09

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EP92118660A Expired - Lifetime EP0543197B1 (fr) 1991-11-19 1992-10-31 Système de télévision comportant une mémoire à accès séquentiel multiple
EP98105936A Expired - Lifetime EP0862333B1 (fr) 1991-11-19 1992-10-31 Procédé pour stocker des données vidéo et système de télévision correspondant

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EP (2) EP0543197B1 (fr)
JP (1) JP3194500B2 (fr)
KR (1) KR970000604B1 (fr)
AT (2) ATE218263T1 (fr)
AU (1) AU661637B2 (fr)
CA (1) CA2082133C (fr)
DE (2) DE69227821T2 (fr)
MX (1) MX9206693A (fr)
NO (1) NO302679B1 (fr)
TW (1) TW225081B (fr)

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JPH0612485A (ja) 1994-01-21
DE69232623T2 (de) 2003-02-06
NO924452D0 (no) 1992-11-18
DE69227821D1 (de) 1999-01-21
KR930011726A (ko) 1993-06-24
MX9206693A (es) 1993-05-01
EP0862333A3 (fr) 2000-09-27
NO924452L (no) 1993-05-20
NO302679B1 (no) 1998-04-06
JP3194500B2 (ja) 2001-07-30
TW225081B (fr) 1994-06-11
ATE174449T1 (de) 1998-12-15
AU661637B2 (en) 1995-07-27
ATE218263T1 (de) 2002-06-15
EP0543197A3 (fr) 1994-04-20
US5315388A (en) 1994-05-24
EP0862333A2 (fr) 1998-09-02
AU2845692A (en) 1993-05-20
DE69227821T2 (de) 1999-06-17
KR970000604B1 (ko) 1997-01-14
EP0862333B1 (fr) 2002-05-29
EP0543197B1 (fr) 1998-12-09
DE69232623D1 (de) 2002-07-04
CA2082133C (fr) 2000-05-02
CA2082133A1 (fr) 1993-05-20

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