Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K21/00—Details of pulse counters or frequency dividers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/32—Timing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/5644—Multilevel memory comprising counting devices
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store

Definitions

• the invention relates to a two-dimensional circuit array, in particular for use in a data processing system.
• Two-dimensional circuit arrays are known. For example, a multiplicity of memory cells are arranged in semiconductor memories in a two-dimensional matrix with, for example, X row lines and Y column lines. By selecting a specific x row line and a specific y column line, ie by specifying a specific address, data can be stored in the memory cell addressed with this address and read out again. At each crossing point of a row and a column line, the two inputs of an AND gate are connected, the output of which is connected to a memory cell. In order to write information into a specific memory cell, the corresponding address is created and information, for example binary 0 or binary 1, is optionally written into the memory cell.
• Such a semiconductor memory is described, for example, in the specialist book "semiconductor circuit technology", Tietze, Schenk, reprint of the third edition, Springer Verlag, 1976, pages 525-527 (chapter 17.5.1), If, instead of one bit, n-bits are to be stored under an address, n memory cells are accommodated under each address and n parallel write and read lines are used.
• the object of the present invention is to provide a two-dimensional circuit array and to specify a method for using this circuit array with which data words applied to the circuit array can be checked.
• the use of counters in the device according to the invention has the advantage that, in contrast to an individual memory cell, more than 1 bit can be stored under each address.
• a data word with a binary value from 0 to 255 can be stored under each address.
• the present invention also has the advantage that, depending on the desired use, a special link is used.
• a special link is used.
• the use of an AND gate or a NAND gate is preferred.
• OR, NOR, EQUIVALENCE or ANTIVALENCE elements can also be used.
• a common clock signal is applied to all synchronous counters.
• the counter is either incremented with each clock pulse, for example, increments or maintains its previous counter reading.
• the step size with which the counter can be counted up or down can be set as desired, i.e. the step size can also be greater than 1.
• the counter has, for example, a combination of an arithmetic unit (ALU) and at least one register.
• ALU arithmetic unit
• the output of the counter is connected to a first input of a comparator.
• the comparator delivers a corresponding output signal.
• the output signal indicates whether the counter reading is greater than, equal to or less than the comparison value.
• each counter and / or each comparator of the two-dimensional circuit array is transferred to a common evaluation logic.
• This evaluation logic is preferably a priority encoder.
• the evaluation logic is particularly preferably connected to a memory in which, depending on the counter reading at a specific point in time and a comparison result provided by the comparator, information is stored, e.g. the address of the cross point at which the comparator provides an output signal that indicates that the count is greater than the comparison value.
• the outputs of the counter are connected to the inputs of a maximum value detector.
• a maximum value detector By checking, for example, the line (lines) which corresponds to the highest bit (the highest bits), can in a simple manner. Counters with the largest counter reading (s) can be determined.
• An array is particularly preferably constructed as a 4 ⁇ 4 matrix.
• the method according to the invention using the device according to the invention has the advantage that individual data words of a large data word can be examined very quickly for their degree of agreement by linking them with certain comparison criteria.
• the method is repeated with further comparison criteria until the amount of data words is reduced to the desired number.
• Fig. 1 is a schematic arrangement of the two-dimensional circuit array according to the invention.
• Fig. 2 shows a detail of Fig. L.
• the circuit array according to the invention shown by way of example in FIG. 1 consists of a 4 ⁇ 4 matrix. It therefore has four row lines 1 to 4 and four column lines 1 to 4. At each crossing point of a row with a column there is a logic element with two inputs, the first input of which is connected to a corresponding row and the second input of which is connected to a corresponding column.
• the link is in the execution example of an AND gate.
• the output of each logic link is connected to an input E of an associated counter module 20.
• Each counter module 20 also has one
• address decoders are arranged at the input of the row lines and the column lines.
• clock generator (not shown), or a system clock signal is supplied to the counter modules 20.
• each counter module 20 is incremented when both the associated row line and the associated column line are driven with a specific electrical signal. Otherwise the counter module maintains its previous counter status.
• all counter modules 20 are reset to 0, for example, with a RESET signal. Then, for a certain period of time or depending on a certain number of comparison criteria, the row lines and the column lines are subjected to signals one after the other and at the end the counter reading in the respective counter module 20, ie BS ⁇ , BS 12 ... B s 43 and BS 44 the number of matches of the signals on the row line and column line pairs. This counter reading can be output via output A of counter modules 20 for further processing.
• each counter module 20, as shown in FIG. 2 has a counter 22 and a comparator 24.
• the comparator 24 can be programmed either with a fixed comparison value or with a comparison value that can be input from the outside via an input V.
• the Comparator 24 an output signal which indicates whether the counter reading in counter 22 is less than, equal to or greater than the programmed comparison value.
• the output of the counter and / or each comparator is transferred to a common evaluation logic (not shown).
• This evaluation logic e.g. in the form of a priority encoder determines which of the counter modules 20 in the two-dimensional circuit array has a certain criterion, e.g. meets the comparison value.
• the result of this evaluation can be stored in a further memory (not shown).

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Logic Circuits (AREA)

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• 1990
  • 1990-05-15 DE DE19904015604 patent/DE4015604A1/de active Granted
• 1991
  • 1991-05-14 WO PCT/EP1991/000900 patent/WO1991018395A1/de not_active Application Discontinuation
  • 1991-05-14 EP EP19910909174 patent/EP0528889A1/de not_active Withdrawn

Non-Patent Citations (1)

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