EP0507210A2 - Datenverarbeitungssystem zum Quadratieren mit erhöhter Geschwindigkeit und Verfahren dazu - Google Patents

Datenverarbeitungssystem zum Quadratieren mit erhöhter Geschwindigkeit und Verfahren dazu Download PDF

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Publication number
EP0507210A2
EP0507210A2 EP92105179A EP92105179A EP0507210A2 EP 0507210 A2 EP0507210 A2 EP 0507210A2 EP 92105179 A EP92105179 A EP 92105179A EP 92105179 A EP92105179 A EP 92105179A EP 0507210 A2 EP0507210 A2 EP 0507210A2
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EP
European Patent Office
Prior art keywords
data
memory
address
addresses
response
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92105179A
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English (en)
French (fr)
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EP0507210B1 (de
EP0507210A3 (en
Inventor
James W. Girardeau
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Motorola Solutions Inc
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Motorola Inc
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Publication of EP0507210A3 publication Critical patent/EP0507210A3/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/552—Indexing scheme relating to groups G06F7/552 - G06F7/5525
    • G06F2207/5523—Calculates a power, e.g. the square, of a number or a function, e.g. polynomials

Definitions

  • This invention relates generally to data processing systems, and more particularly, to data processing systems having data processors with two or more data paths.
  • DSPs digital signal processors
  • FFT fast fourier transform
  • One way to accomplish fast arithmetic manipulation of data is for the DSP to access two separate operands independently via two separate data paths. See, for example, "A Digital Signal Processor with IEEE Floating-Point Arithmetic" by Sohie, G. and Kloker, K., IEEE Micro , vol. 8, no. 6, December 1988, pp. 49-67.
  • the data accessed through the two data paths may be in physically distinct memory systems, but more typically is located within the same memory system.
  • a DSP may perform a multiply operation by fetching one operand through the first data path, and the other operand from the second data path.
  • An assembly code mnemonic for such an operation may read "mpy (r0)*(r1)", where r0 and r1 are pointers to data to be accessed from the first and second data paths, respectively, as the two operands of the multiply operation.
  • Computational algorithms for digital signal processing often involve squaring of operands, that is, multiplying an operand by itself. To maximize the speed of the square operation, it is desirable to fetch one operand from each data path.
  • the mnemonic for such an operation may read “mpy (r0)*(r0)", where r0 is the pointer to the operand to be squared.
  • r0 is the pointer to the operand to be squared.
  • the square operation "mpy (r0) * (r0)” takes multiple cycles because the same data must be fetched twice out of the same memory location and provided to two different data paths.
  • a memory system comprising first and second memory portions, a controller, multiplex means, and logic means.
  • the controller receives first and second input addresses and provides first and second memory addresses to the first and second memory portions, respectively, in response.
  • the multiplex means is coupled to the first and second memory portions, and multiplexes data from the first memory portion onto either the first or the second data path in response to a first portion of the first address, and from the second memory portion onto either the first or the second data path in response to a first portion of the second address.
  • the logic means provides a wait signal if both, the first portion of the first address and the first portion of the second address are equal, and, a second portion of the first address and a second portion of the second address are not equal.
  • FIG. 1 illustrates in block form a data processing system with a data processor having two data paths.
  • FIG. 2 illustrates a timing diagram of signals pertinent to the data processing system of FIG. 1.
  • FIG. 3 illustrates in block form a data processing system in accordance with the present invention.
  • FIG. 4 illustrates a timing diagram of signals pertinent to the data processing system of FIG. 3.
  • FIG. 5 illustrates a data processing system in accordance with a preferred embodiment of the present invention.
  • FIG. 1 illustrates in block form a data processing system 20 with a data processor having two data paths.
  • Data processing system 20 includes generally a digital signal processor 21, and a memory system 22. More particularly, memory system 22 includes a memory controller 23, a first memory portion 24 labelled “MEMORY BANK 0", a second memory portion 25 labelled “MEMORY BANK 1", a multiplexer 26, a multiplexer 27, and a comparator 28.
  • Digital signal processor 21 has two data paths, one data path conducting 16 bidirectional data signals labelled "XDATA", and another data path conducting 16 bidirectional data signals labelled "YDATA”. Digital signal processor 21 provides two addresses labelled "XADDRESS” and "YADDRESS" to access data in memory system 22.
  • XADDRESS has a highest-ordered bit labeled "XBANK”, with the remaining bit positions designated "XINDEX”.
  • YADDRESS has a highest-ordered bit labeled "YBANK”, with the remaining bit positions designated "YINDEX”.
  • both XDATA and YDATA are 16-bit, general purpose, bidirectional data paths. In another embodiments, either or both data paths may be read-only. It should also be apparent that the present invention is applicable also to different address and data bus sizes.
  • Memory controller 23 receives both XADDRESS and YADDRESS, and provides a plurality of address signals labelled "BANK 0 INDEX” to first memory portion 24, and a plurality of address signals labelled “BANK 1 INDEX” to second memory portion 25.
  • Memory portions 24 and 25 each couple sixteen bidirectional data signal lines to both multiplexer 26 and multiplexer 27.
  • Multiplexer 26 is coupled to both memory portion 24 and memory portion 25, receives address signal XBANK from digital signal processor 21, and is coupled to the XDATA path.
  • Multiplexer 27 is coupled to both memory portion 24 and memory portion 25, receives address signal YBANK from digital signal processor 21, and is coupled to the YDATA path.
  • Comparator 28 receives both address signals XBANK and YBANK, and provides a signal labelled "WAIT" to digital signal processor 21. It should be apparent that various timing and control signals are omitted from this illustration of data processing system 20, but the timing and function of such control signals are known in the art and are not essential in understanding the present invention.
  • digital signal processor 21 is a conventional digital signal processor which accesses data through two separate data paths, accessed by two addresses.
  • the first address, XADDRESS includes high-order address bit XBANK to select whether memory portion 24 or 25 is coupled to the XDATA path.
  • the remaining bits of XADDRESS provide an index into memory portion selected by XBANK.
  • the second address, YADDRESS includes high-order address bit YBANK to select whether memory portion 24 or 25 is coupled to the YDATA path.
  • the remaining bits of YADDRESS provide an index into the memory portion selected by YBANK.
  • digital signal processor 21 may simultaneously accesses data from both the XDATA and YDATA paths if an instruction being executed so specifies.
  • digital signal processor 21 may be a general purpose or integer data processor, although dual data paths are especially suited to DSP systems.
  • accesses to the XDATA and YDATA paths may occur simultaneously, without delay.
  • Memory system 22 has two portions, 24 and 25, to more easily avoid delay. If all the operands accessed via the XDATA path are located in one portion, and all operands accessed via the YDATA path are located in the other portion, then each operation may proceed without delay, providing two operands of data to digital signal processor 21 in one memory access cycle. If XBANK and YBANK are the same, indicating that data to be accessed via both data paths is present in the same memory portion, then a collision occurs. Comparator 28 detects the collision and activates WAIT to digital signal processor 21. If a collision occurs and WAIT is activated, then the memory fetches must be done sequentially, taking two cycles to provide data to digital signal processor 21.
  • XBANK and YBANK are within the address space of memory portion 24.
  • Memory controller 23 recognizes the collision by examining XBANK and YBANK. In a first cycle, memory controller 23 provides BANK 0 INDEX to memory portion 24 in response to the lower fifteen bits of XADDRESS, and the contents of the accessed location are passed through multiplexer 26 as XDATA. Comparator 28 also recognizes the collision by comparing XBANK and YBANK, and activates signal WAIT in response.
  • YBANK also causes multiplexer 27 to couple data from memory portion 24 accessed by XADDRESS to the YDATA path
  • digital signal processor 21 receives signal WAIT, and reads only the first operand via the XDATA path.
  • memory controller 23 provides BANK 0 INDEX to memory portion 24 in response to YADDRESS, and the contents of the accessed location are passed through multiplexer 27 as YDATA.
  • Comparator 28 deactivates signal WAIT to indicate to digital signal processor 21 that the second operand may be received on the YDATA path.
  • XBANK also causes multiplexer 26 to couple data from memory portion 24 accessed by YADDRESS to the XDATA path during the second cycle
  • digital signal processor senses the negation of signal WAIT and reads only the second operand via the YDATA path.
  • memory portion 24 provides data labeled "BANK0 DATA” addressed by XADDRESS to the XDATA path
  • memory portion 25 provides data labelled "BANK1 DATA” addressed by YADDRESS to the YDATA path, where r0 is a pointer to a memory location in MEMORY BANK 0, and r1 is a pointer to a memory location in MEMORY BANK 1.
  • BANK0 DATA and BANK1 DATA do not represent a data element from a single memory location, but rather some data element from memory portion 24 and memory portion 25, respectively.
  • Data is provided to both data paths and the instruction mpy(r0)*(r1) is completed in one memory access cycle, which is the time between t0 and a time labelled "t1".
  • a subsequent access occurs between t1 and a time labeled "t2", during which BANK0 DATA is addressed by XADDRESS on the XDATA path and BANK1 DATA is addressed by YADDRESS on the YDATA path.
  • data processing system 20 provides an efficient system to access data via two data paths for real-time DSP operation.
  • FIG. 3 illustrates in block form a data processing system 20' in accordance with the present invention.
  • Data processing system 20' has some elements in common with data processing system 20 of FIG. 1, and the common elements are similarly numbered.
  • Memory system 22' additionally includes a comparator 30, an inverter 31, and an AND gate 32.
  • Comparator 30 has a first set of input terminals for receiving the fifteen XINDEX signals, a second set of input terminals for receiving the fifteen YINDEX signals, and an output terminal.
  • Inverter 31 has an input terminal coupled to the output terminal of comparator 30, and an output terminal for providing a signal labelled SQUARE ⁇ .
  • SQUARE ⁇ is an active low signal indicating that a square operation is in progress.
  • AND gate 32 has a first input terminal for receiving SQUARE ⁇ , a second input terminal connected to the output terminal of comparator 28, and an output terminal providing signal WAIT to digital signal processor 21.
  • comparator 28 If an operation is in progress in which accesses from both data paths are sought in a single memory portion, but to different addresses, it is of course necessary to provide the data in sequential cycles (as previously illustrated between t2 and t3 in FIG. 2).
  • the output terminal of comparator 28 is active at a logic high to indicate that XBANK and YBANK are equal. Since XINDEX and YINDEX are not equal, SQUARE ⁇ is inactive at a logic high, and thus WAIT is active. If a square operation is in progress, indicated by the mnemonic "mpy (r0)*(r0)", digital signal processor 21 attempts to access the same memory location on both the XDATA and YDATA paths.
  • both XBANK and YBANK are equal, and XINDEX and YINDEX are equal.
  • the output of comparator 28 is a logic high, and signal SQUARE ⁇ is active at a logic low. Thus, signal WAIT remains inactive. If r0 is a pointer to MEMORY BANK 0, then the sixteen bits of data provided by MEMORY BANK 0 are coupled to both the XDATA and YDATA paths, and digital signal processor 21 reads operands from both the XDATA and YDATA paths within a single memory access cycle.
  • r0 is a pointer to MEMORY BANK 1
  • the sixteen bits of data provided by MEMORY BANK 1 are coupled to both the XDATA and YDATA paths, and digital signal processor 21 reads operands from both the XDATA and YDATA paths within a single memory access cycle.
  • FIG. 4 illustrates a timing diagram of signals pertinent to data processing system 20' of FIG. 3. Time points are similarly numbered as corresponding time points in FIG. 2. Between times t0 and t1, and t1 and t2, digital signal processor 21 accesses BANK0 DATA addressed by XADDRESS and BANK1 DATA addressed by YADDRESS on the XDATA and YDATA paths, respectively. However, digital signal processor 21 attempts to execute a square operation at time t2. Since signal WAIT is now kept inactive when comparator 30 detects XADDRESS and YADDRESS being equal, the data element of the square operation is now simultaneously read on both the XDATA and YDATA paths. Thus, data processing system 20' has improved performance in relation to data processing system 20 illustrated in FIG. 1. The amount of performance improvement depends on the application, but as the proportion of square operations to the number of total operations increases, the percentage performance improvement increases. The performance improvement is larger for computation-intensive applications such as digital signal processing.
  • the lost bus bandwidth during the square operation is recovered, resulting in improved system performance.
  • the amount of improvement depends, of course, on the types of instructions being performed by digital signal processor 21. However, the improvement is greater for more computation-intensive applications.
  • the overall power consumption expended in performing the multiply instruction is reduced because, for example, power consumed by multiplexer 27 providing the unused data element between times t2 and t3, in which the YDATA path is idle, is saved.
  • data processing system 20' adds only a small amount of extra circuitry, which can be easily added to integrated circuits or computer-board logic.
  • the delay through comparator 30, inverter 31, and AND gate 32 is less than the time it takes for either memory portion 24 or memory portion 25 to provide data to either the XDATA or the YDATA path, and thus the additional circuitry does not slow the memory access cycle.
  • the invention is transparent to a programmer of digital signal processor 21, because a special instruction to perform a square operation is not required.
  • the extra circuitry of data processing system 20' improves the operation of instructions other than the square instruction, such as an add instruction of the same operand to achieve a quick multiply by two.
  • Sixth existing software programs will run unchanged using the improved memory architecture, but will execute faster. Thus, the improvement offered by memory system 22' over memory system 22 of FIG. 2 is transparent to the programmer.
  • FIG. 5 illustrates a data processing system 20'' in accordance with a preferred embodiment of the present invention.
  • Data processing system 20'' has some elements in common with data processing system 20' of FIG. 3, and the common elements are similarly numbered.
  • memory system 22'' includes eight memory portions 40-47, each receiving an index address from memory controller 23''.
  • XBANK and YBANK are three high-order bits to select one-of-eight memory portions.
  • XINDEX and YINDEX are 13-bit indexes into operands for the XDATA and YDATA paths, respectively.
  • comparator 30'' performs a comparison on 13-bit input numbers
  • comparator 28'' performs a comparison on 3-bit input numbers
  • multiplexers 26'' and 27'' receive the 3-bit XBANK and YBANK to select one-of-eight memory portions to couple to the XDATA and YDATA paths, respectively.
  • FIG. 5 to FIG. 1 it is seen that arbitrary numbers of memory portions may be included in the memory system, with a minimum of two. The number of memory portions included may be affected by how a compiler of machine code for digital signal processor 21 segments operands for the program running on digital signal processor 21.
  • the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above.
  • the number of memory portions in the memory system may be increased to decrease the likelihood that digital signal processor 21 will access the same portion on both data paths and WAIT must be activated. In that case, the number of signals in XBANK and YBANK is increased.
  • a data processor which has two data paths but which performs a function other than digital signal processing is also possible. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.

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  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
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EP92105179A 1991-04-01 1992-03-26 Datenverarbeitungssystem zum Quadratieren mit erhöhter Geschwindigkeit und Verfahren dazu Expired - Lifetime EP0507210B1 (de)

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Application Number Priority Date Filing Date Title
US677919 1984-12-04
US67791991A 1991-04-01 1991-04-01

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EP0507210A2 true EP0507210A2 (de) 1992-10-07
EP0507210A3 EP0507210A3 (en) 1993-05-12
EP0507210B1 EP0507210B1 (de) 1998-10-14

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EP (1) EP0507210B1 (de)
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Cited By (2)

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FR2773234A1 (fr) * 1997-12-31 1999-07-02 Sgs Thomson Microelectronics Memoire a double acces pour processeur de signal numerique
US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations

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US7483935B2 (en) * 1995-08-16 2009-01-27 Microunity Systems Engineering, Inc. System and method to implement a matrix multiply unit of a broadband processor
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5953241A (en) 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US5638533A (en) * 1995-10-12 1997-06-10 Lsi Logic Corporation Method and apparatus for providing data to a parallel processing array
US7932911B2 (en) * 1998-08-24 2011-04-26 Microunity Systems Engineering, Inc. Processor for executing switch and translate instructions requiring wide operands
DE69942339D1 (de) * 1998-08-24 2010-06-17 Microunity Systems Eng System mit breiter operandenarchitektur und verfahren
US6442672B1 (en) * 1998-09-30 2002-08-27 Conexant Systems, Inc. Method for dynamic allocation and efficient sharing of functional unit datapaths
EP1139669A1 (de) * 2000-03-28 2001-10-04 STMicroelectronics S.r.l. Koprozessor zur bewegungsschätzung in codierern für digitalisierte videosequenzen
FR2818145B1 (fr) * 2000-12-18 2003-11-28 Oreal Compositions cosmetiques antisolaires a base d'un melange synergetique de filtres et utilisations
JP2002215606A (ja) 2001-01-24 2002-08-02 Mitsubishi Electric Corp データ処理装置
US6968447B1 (en) * 2001-04-13 2005-11-22 The United States Of America As Represented By The Secretary Of The Navy System and method for data forwarding in a programmable multiple network processor environment
WO2003021423A2 (en) * 2001-09-04 2003-03-13 Microunity Systems Engineering, Inc. System and method for performing multiplication
JP5204777B2 (ja) * 2007-12-21 2013-06-05 パナソニック株式会社 メモリ装置及びその制御方法
US9785565B2 (en) 2014-06-30 2017-10-10 Microunity Systems Engineering, Inc. System and methods for expandably wide processor instructions

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US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations
US8769248B2 (en) 1995-08-16 2014-07-01 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations
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DE69227271D1 (de) 1998-11-19
EP0507210B1 (de) 1998-10-14
JPH05100948A (ja) 1993-04-23
US5487024A (en) 1996-01-23
EP0507210A3 (en) 1993-05-12
JP2816624B2 (ja) 1998-10-27

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