EP0496878A1 - Mecanisme d'acces direct a la memoire a base de decalages - Google Patents

Mecanisme d'acces direct a la memoire a base de decalages

Info

Publication number
EP0496878A1
EP0496878A1 EP19910917205 EP91917205A EP0496878A1 EP 0496878 A1 EP0496878 A1 EP 0496878A1 EP 19910917205 EP19910917205 EP 19910917205 EP 91917205 A EP91917205 A EP 91917205A EP 0496878 A1 EP0496878 A1 EP 0496878A1
Authority
EP
European Patent Office
Prior art keywords
tile
storage locations
tiles
address
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910917205
Other languages
German (de)
English (en)
Inventor
James Morgan Gotta, Iii
David William Dellert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of EP0496878A1 publication Critical patent/EP0496878A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Definitions

  • the present invention relates in general to information storage and retrieval systems and is particularly directed to a direct memory access mechanism for rapidly accessing a selected portion of a data base, such as a plurality of tiles within an image bit map memory, by means of a dedicated, offset-based, address control architecture.
  • Accessing discrete portions of a large data base such as a bit map memory which may have a storage capacity that accommodates a 3200 by 3000 pixel matrix, is typically accomplished in one of two ways:
  • this processor overhead burden is removed by means of a dedicated address generation architecture which controllably combines a single starting address supplied by the processor with a set of predefined 'offsets' and steps through each of the tiles of a block of tiles corresponding to that portion of the data base involved in the transfer.
  • the address generation architecture of the present invention contains a line address storage register which is coupled to receive, from the host processor, an address code representative of a first set of addressable storage locations of a first row of a first one of the block of tiles involved in the transfer.
  • a respective row of a tile is subdivided into sets of address words, each of which is associated with, a plurality of pixel locations .e.g..
  • the address generator couples the adder to a second 'line offset' code modifier which, when combined with the contents of said line address store, yields an address code representative of a first set of addressable storage locations of another (e.g. the second or next) row of the tile, which now becomes the base address stored in the .line address register.
  • a fourth strip offset is stored.
  • This code is representative of the sequential address displacement between the first set of addressable storage locations of the last row of a last tile of one strip of tiles and the first set of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of tiles.
  • the fourth offset is used as an offset to the line address register to specify the starting address of the next strip. This sequential offset reference and stepping process is continued through all the strips of the block to complete the DMA transfer.
  • Figure 1 diagrammatically shows an information storage and retrieval system in which the memory access mechanism of the present invention may be employed;
  • Figure 2 diagrammatically shows the configuration of a direct memory access unit 41 of Figure 1;
  • Figure 3 diagrammatically illustrates the hierarchical relationship among a frame store matrix and respective components of a block of addresses to be accessed by the DMA unit of the present invention
  • Figure 5 diagrammatically shows the storage space of destination frame store 21 subdivided into a plurality of tiles 27-1...27-16.
  • the present invention resides primarily in a novel structural combination of conventional digital signal processing circuits and components and not in the particular detailed configurations thereof. Accordingly, the structure, control and arrangement of these conventional circuits and components have been illustrated in the drawings in readily understandable block diagram format to show only those specific details that are pertinent to the present invention, so as not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the block diagram il. .trations do not necessarily represent the mechanical structural arrangement of the exemplary system, but are primarily intended to illustrate the major structural components of the system in a convenient functional grouping, whereby the present invention may be more readily understood.
  • FIG. 1 a non- limiting example of an information storage and retrieval system in which the offset-based direct memory access mechanism of the present invention may be employed is diagrammatically shown as comprising an imagery data processing system having a first, or source, frame store 11, which contains data representative of a bit map image 13 to be displayed by an associated display terminal 15.
  • the bit map itself comprises an M row by N column array or matrix of pixels and, as a simplified illustration, may be considered to comprise a 256X256 array of pixels, subdividable into a plurality (e.g. sixteen) of pixel 'tiles' 17-1 ...17-16, each tile comprising a 64X64 pixel sub-array, or sub-matrix.
  • FIG. 1 Also shown in Figure 1 is a second, or destination, frame store 21 which, like frame store 11, is capable of storing data representative of an MXN bit map array that may be displayed on an associated display terminal, such as display terminal 21, or a separate device (not shown) .
  • Each of frame stores 11 and 21 has its data port coupled to a data bus 25 through which imagery-representative data, accessed from either of frame stores 11 and 21, may be coupled to an digital-analog converter 26, which converts the pixel control codes on bus 25 into analog format for defining the energization of the respective pixels of display 15.
  • the storage and retrieval system of Figure 1 further includes a data orientation device, such as a conventional data rotator unit 31, which is coupled to data bus 25 and rotates (e.g. performs a 90° rotation of) a block of data supplied to its data port 33.
  • DMA unit 41 In accordance with the present invention, addressing of the respective storage locations of each of frame stores 11 and 21, for reading and writing data to and from memory, is effected by means of a Direct Memory Access (DMA) unit 41, shown in detail in Figure 2 to be described below.
  • DMA unit 41 employs a set of offsets that are used to sequentially update the base address with a line address register, in the course of generation address signals only for storage locations associated with those tiles that make up the portion of the frame store to be accessed.
  • the operation to be performed involves a transfer, a translation and a rotation of a portion of the bit map imagery data within frame store 11 to frair '.ore 21.
  • translation is meant that the dest ..tion location, within the bit map of frame store 21, of the transferred portion of the image is different from its original location within the bit map in frame store 11.
  • bit map 17 within frame store 11
  • a destination location within the bit map 27 stored by frame store 21 denoted by a block 52 of tiles 27-11, 27-12, 27-15 and 27-16.
  • the location of 'destination' block 52 in the bit map 27 of frame store 21 is in the lower right-hand corner of the bit map 27, whereas the location of 'source' block 51 is in the upper left-hand corner of bit map 17 of frame store 11, so that the transfer between frame stores effectively performs a translation of the location of the selected portion of the image.
  • the ir gery data within source block 51 is also to undergo a 90° clockwise rotation relative to its orientation within frame store 11.
  • the imagery data within each of the tiles of frame store 11 be represented by an enlarged reference numeral associated with the numerical position of the tile within the sixteen tile matrix, then an associated set of vertically oriented number images 1, 2, 5, and 6 shown within respective tiles 17-1, 17-2, 17-5 and 17-6 of source block 51, after being when rotated clockwise 90°, will be transferred to tiles 27-12, 27-16, 27-11 and 27-15, respectively, of destination block 52 in horizontal orientation, as shown.
  • DMA unit 41 is diagrammatically shown as having an input port 61 which is coupled to the control bus 63 of an attendant control processor (not shown) .
  • the control processor supplies a starting address code representative of the starting address of the block of tiles involved in the data transfer.
  • port 61 receives a starting address code representative of a starting address in the first row of tile 17-1.
  • data is accessed as multi-bit words or sets, so that the starting address will be the address where the first word in the first line of the tile is stored.
  • pixel data may be accessed in words of sixteen pixel addresses per word address, so that there are four words per tile row.
  • Input port 61 is coupled to a first input 71 of a multiplexer 70, the output port 74 of which is coupled to- an output register 73 and to a line register 75.
  • Output register 73 is coupled to output port 81, while line register 75 is coupled to a first port 83 of an address code combiner (here an adder) 80, a second port 85 of which is coupled to output port 95 of a 4:1 multiplexer 90.
  • Adder 80 combines or sums the address code stored in line register 75 with an address code modifier supplied from multiplexer 90 and couples the resulting sum or 'modified' address code to a second input port 72 of multiplexer 70.
  • multiplexer 70 couples input port 72 to its output port 74, so that the modified address code generated by adder 80 is coupled to output register 73 for application to output port 81.
  • output port 74 of multiplexer 70 is also coupled to line address register 75, line address register 75 is not updated in the same manner as output register 73. Instead, the contents of line address register 75 are sequentially incremented only when one of a set of input ports 92-94 of multiplexer 90, to which line, file and offset codes are respectively supplied, is selected. The selected offset code is summed in adder 90 with the contents of the line address register 75 and then rewritten back into register 75 (by way of multiplexer 70) , in order to effectively step through successive address of the block of files involved in the transfer.
  • the input ports to multiplexer 90 include an input port 91 coupled to the output of a tile width up-counter 111, the input of which is coupled to a tile width register 101.
  • Each of tile width counter 111 and tile width register 101 is also coupled to a comparator 113, which generates an output in response to the contents of tile width counter 111 matching the tile width code stored in tile width register 101.
  • 'tile width' is meant the number of words that are contained in a row of a tile. As pointed out above, data is normally accessed as multi-bit words. In the present example of sixty-four pixels per row, with sixteen bits per word, the total word width of an individual tile is four words.
  • up-counter 111 is successively incremented from an initial (reset) value of zero until its count value matches the value (e.g. three for the present example of four words per row) stored in tile width register 101.
  • comparator 113 produces an output which causes tile width counter 111 to be reset and causes multiplexer 90 to select one of its other input ports (92, 93 and 94) depending upon where in the block of tile the address scan is currently located.
  • counter 111 As counter 111 is being incremented, it generates a sequence of address code modifiers which are summed in adder 83 with the contents of line address register 75 to yield a sequence of modified address codes associated with respectively different words of address space within that one of the rows of a respective tile currently pointed to by line address register 75.
  • a second input 92 is coupled to line offset register 102 which stores a line offset code representative of the displacement (in words) between the same word address location for successive rows of a tile. For a matrix line vidth of 256 bits, 1 » displacement between the first word address or. row i and row itl of a respective tile is 16 words.
  • a third input port 93 of multiplexer 90 is coupled to a tile offset register 103, which stores a 'tile offset' address code modifier.
  • the value of the tile offset modifier is such that when combined in adder 80 with the contents of line address register 75, the resulting sum yields an address code representative of the first row or line another (the next successive) tile of the block of tiles involved in the transfer.
  • the value of the strip offset modifier represents the sequential address displacement between the address of the last or Jth row of the last tile in one strip of tiles and that of the next strip of tiles within the block of interest.
  • a tile strip is a subdivision of the tile block in a selected address scan direction (e.g. horizontally, or parallel to the rows or lines of the matrix) .
  • block 51 is comprised of two adjacent tile strips SI and S2, each strip containing two tiles.
  • Strip SI contains tiles 17-1 and 17-2, while strip S2 contains tiles 17-5 and 17-6.
  • Figure 3 diagrammatically illustrates the hierarchical relationship among the frame store matrix and the respective components of a block of addresses to be accessed by the DMA unit of the present invention.
  • block 51 is comprised of two strips SI and S2, strip SI containing two tiles
  • a respective tile has a 'height' of sixty-four rows, as exemplified by tile 17-1.
  • a respective row of sixty- four pixel locations or columns contains four words, each of which comprises sixteen pixel locations.
  • a 'strip' down-counter 120 is employed. At the start of the DMA process, counter 120 is loaded with the number of tile strips in the block (two in the present example) . Counter 120 is then successively decremented as each strip of tiles is processed. When counter 120 expires, or is decremented to zero, it is determined that there are no further strips to be processed for that block. Similarly, to determine when address codes have been generated for all of the tiles in a respective strip of tiles, a 'tile' down-counter 122 and an associated 'tile' register 124 are employed.
  • tile register 124 is initially loaded with the number of tiles per strip (two in the present example) , and the tile code is entered into tile counter 122. Like strip counter 120, tile down-counter 122 is successively decremented as each strip of tiles is processed. When counter 122 expires or is decremented to zero it is determined that there are no further tiles to be processed for that strip. The contents of tile register 124 are then transferred to c inter 122 for processing the next strip.
  • a 'tile height' down-counter 126 and an associated 'tile count' register 128 are employed.
  • 'Tile height' register 126 is initialized with the number of rows per tile (sixty-four in the present example) , and this tile height code is loaded into tile height counter 126.
  • Tile height down-counter 126 is successively decremented as each row of a tile is processed. When counter 126 expires or is decremented to zero it is determined that there are no further rows in the tile to be processed. The contents of tile height register 128 are then transferred to counter 126 for processing the next tile.
  • multiplexer 90 controllably couples the contents of selected ones of tile width counter 111 and offset registers 102, 103 and 104 to its output port 95, so that, when summed with the contents of line address register 75, there is produced a modification of the original address code coupled to input port 61 that effects a rapid scan through only those storage locations in the frame store associated with the tiles in the block of interest. Other entries in the memory are ignored.
  • the addressable storage locations of a respective row are addressable in successive sets or words of sixteen locations (columns) , so that each row of a tile contains four consecutive words (W0-W3) .
  • the control processor supplies to input port 61 an address code representative of the first word WO of the first row of the block of tiles to be involved in the DMA transfer.
  • the processor supplies the address of word WO of the first row of tile 17-1, which is coupled through multiplexer 70 and loaded into line address register 75.
  • Address code offset multiplexer 90 is controlled to select tile width counter 111, which is currently reset.
  • the output of adder 80 is simply the initial address code that has been loaded into line address register 75.
  • This combined address code is coupled through multiplexer 70 and loaded into output register 73, so that the output address code at port 81 points to the upper left- hand corner address of tile 17-1, at row 0, address word W0.
  • Tile width up-counter 111 is then sequentially incremented, so that adder 80, in turn, will sequentially produce increasingly larger sums, thereby modifying the address code supplied to output register 73 and stepping through the successive address words W0-W3 of row R0 of tile 17-1.
  • comparator 113 produces an output, which resets tile width counter 111 to be reset, causes tile height counter 126 to be decremented to a value of 63 from its pre-loaded value of 64 and causes address code offset multiplexer 90 to select input port 92, to which the contents of line offset register 102 are coupled.
  • line offset address register 102 stores a line offset value of sixteen which, when combined with the contents of line address register 75, will point produce an address that points to the first address of the second row Rl of tile 17-1. This new line address is then stored in line address register 75.
  • the multiplexer 90 is controlled to select input port 91 and the above sequence operation is repeated, thereby producing successive addresses that step through the four words W0-W3 of the second row Rl of tile 17-1.
  • tile offset register 103 is a value representative of the sequential address displacement between the first word WO of row R63 of tile 17-1 (the current value of line address register 75) and the first word WO of the first row R0 of tile 17-2, namely the next tile in the strip.
  • tile offset register 103 contains the value (-1004) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 17-2, namely the fifth word address in the first line of the matrix. This value is loaded into line address register 75. Multiplexer 90 is then controlled to select input port 91. Addresses are now generated for tile 17-2 in the same sequential manner as described above for tile 17.
  • tile height down- counter 126 has again been decremented to zero, its output changes state, causing the contents of tile down-counter 122 to be decremented.
  • Tile counter 122 now has been decremented to zero, so that its output also changes state, which, in turn, decrements strip down-counter 120 and causes offset multiplexer 90 to select input port 94, to which the contents of strip offset register 104 are coupled.
  • strip offset register 104 contains a value representative of the sequential address displacement between the first word W0 of row R63 of tile 17-2 (the current value of line address register 75) and the first word WO of the first row R0 of tile 17-5, namely the first tile in the next strip S2 of the block.
  • strip offset register 104 contains a value (12) which, when summed with the current contents of line address register 75, points to word WO in row R0 of tile 17-5. This new offset sum is loaded into line address register 75.
  • Multiplexer 90 is controlled to select input port 91 and addresses are now generated for tiles 17-5 and 17-6 of strip S2 in the same sequential manner as described above for tiles 17-1 and 17-2 of strip SI. When address codes have been generated for each of tiles of strip S2, each of counters 120, 122 and 126 will have been decremented to zero, indicating to the processor that the entire block has been processed.
  • the data read out of block 51 of frame store 11 is rotated (via data rotation device 31, Figure 1) and translated into a block of tiles 27-11, 27-12, 27-15 and 27- 16 of frame store 21.
  • the DMA transfer operation involved only a translation
  • the generation of write addresses for writing data into the memory space of frame store 21 would involve essentially the same tile processing sequence described above, except for the starting address.
  • the contents of the first tile (17-1) read out from block 51 are written into a tile location in destination block 52 (upper right-hand corner tile 27-12) that is displaced relative to the location of tile 71 in source block 51 (upper left-hand corner) .
  • the offset parameters that are stored in line and tile offset registers 102 and 103 are different from those involved in the read operation.
  • the storage space of frame store 21 is subdivided into a plurality of sixteen tiles 27-1...
  • the addressable storage locations of a respective row are addressable in successive sets or words of sixteen locations (columns) , so that each row of a tile contains four consecutive words (W0-W3) .
  • the control processor supplies to input port 61 an address code representative of the first word W0 of the first row of the block of tiles to be involved in the DMA write operation.
  • the processor supplies the address of word WO of the first row of tile 27-12, which is coupled through multiplexer 70 and loaded into line address register 75.
  • address code offset multiplexer 90 selects input port 91, i.e., tile width counter ill, which is currently reset. As a consequence, the output of adder 80 is simply the address code that has been loaded into line address register 75.
  • This address code is coupled through multiplexer 70 and loaded into output register 73, so that the output address code at port 81 points to the upper left-hand corner address of tile 27- 12, at row 0, address word WO.
  • Tile width up-counter 111 is then sequentially incremented, so that adder 80 will modify the address code supplied to output register 73, stepping through the successive address words W0-W3 of row R0 of tile 27-12.
  • comparator 113 produces an output, which resets tile width counter 111, causes tile height counter 126 to be decremented and causes address code offset multiplexer 90 to be coupled to line offset register 102.
  • line offset address register 102 stores a line offset value of (16) which, when combined with the contents of line address register 75, will point produce an address that points to the first address of the second row Rl of tile 27-12.
  • This new line address is then stored in line address register 75, multiplexer 90 again selects input port 91 and the above sequence repeated, thereby producing successive addresses that step through the four words W0-W3 of the second row Rl of tile 27-12. These steps are repeated for each of the sixty-four rows of tile 27-12 until address codes have been generated for all of its 64 rows.
  • tile height down-counter 126 has been decremented to zero, its output changes state.
  • the signal causes the contents of tile down-counter 122 to be decremented and offset multiplexer 90 to be coupled to tile offset register 103.
  • the contents of tile offset register 103 contain an offset value representative of the sequential address displacement between the first word W0 of row R63 of tile 27-12 (the current value of line address register 75) and the first word W0 of the first row R0 of tile 27-16, namely the next tile in the (vertical due to the 90° rotation) strip SI containing tile 27-12.
  • tile offset register 103 contains a value here (+16 words) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 27-16, namely the first word address in line 193 of the matrix.
  • This new base address is loaded into line address register 75 and multiplexer 90 controlled to select input port 91. Addresses are now generated for tile 27-16 in the same sequential manner as described above for tile 27- 12.
  • address codes have been generated for all 64 rows of tile 27-16, the contents of line address counter 75 will again point to the first word W0 of row R63. Since tile height down- counter 126 has again been decremented to zero, its output changes state, causing the contents of tile down-counter 122 to be decremented.
  • Tile counter 122 - too now has been decremented to zero, so that its output changes state.
  • This signal decre-rtents strip down-counter 120 and causes offset multiplexer 90 to select input port 94 to which strip offset r gister 104 is coupled.
  • the contents of strij. offset register 104 contain a value representative of the sequential address displacement between the first word WO of row R63 of tile 27-16 (the current value of line address register 75) and the first word WO of the first row R0 of tile 27-11, namely the first tile in the next strip of the block (here vertical strip 52) .
  • strip offset register 104 contains the value (-2036 words) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 27-11. The offset sum is loaded into line address register, so that its address contents now point toward W0 in row R0 of tile 27-11.
  • Multiplexer 90 is again controlled to select input port 91. Addresses are now generated for tiles 27-11 and 27-15 of strip S2 in the same sequential manner as described above for tiles 27-12 and 27-16 of strip SI. When address codes have been generated for each of the tiles of strip S2, each of counters 120, 122 and 126 will have been decremented to zero, indicating to the processor that the entire block has been processed.
  • the DMA transfer operation of the present example involves a transfer, translation and rotation of a portion of the bit map imagery data from one frame store to another
  • the example has been presented for purposes of a non- limitative illustration.
  • the transfer could just as easily take place between other source and destination entities (e.g. between source and destination locations of the same storage space, such as frame store 11) .
  • the intervening orientation change (via rotation device 31) is not an essential part of the DMA mechanism of the present invention. Data may be transferred, as is.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Image Input (AREA)

Abstract

L'invention se rapporte à un mécanisme d'accès direct à la mémoire (mécanisme ADM), qui permet d'accéder à une partie sélectionnée d'une matrice de stockage d'informations et qui subdivise à cet effet la matrice en plusieurs carreaux, lesquels contiennent chacun une sous-matrice d'emplacements de stockage adressables. On génère des codes d'adresses pour accéder à un bloc de carreaux qui correspondent à la partie sélectionnée de la matrice en stockant l'adresse de départ d'une première rangée d'un premier carreau spécifié du bloc et en procédant ensuite à l'adressage de groupes d'emplacements de stockage à l'intérieur de chacune des rangées successives de ce carreau, par combinaison de modificateurs d'adresse de mot et de ligne avec l'adresse de ligne de départ. En utilisant des codes additionnels qui délimitent la grandeur du bloc, on peut répéter ce processus, si nécessaire, carreau par carreau, pour chacun des carreaux du bloc.
EP19910917205 1990-08-20 1991-08-20 Mecanisme d'acces direct a la memoire a base de decalages Withdrawn EP0496878A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US570176 1984-01-12
US57017690A 1990-08-20 1990-08-20

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EP0496878A1 true EP0496878A1 (fr) 1992-08-05

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JP (1) JPH05502318A (fr)
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JPH0620034A (ja) * 1992-07-02 1994-01-28 Nec Corp 画像処理用アドレス生成回路

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DE3047506C2 (de) * 1980-12-17 1982-12-09 Bruker Analytische Meßtechnik GmbH, 7512 Rheinstetten Verfahren zum Übertragen von Daten und Vorrichtung zur Durchführung dieses Verfahrens
US4658430A (en) * 1984-12-27 1987-04-14 International Business Machines Corp. System for rotating binary images
US4845640A (en) * 1987-03-11 1989-07-04 Megascan Technology, Inc. High-speed dual mode graphics memory
GB2214038B (en) * 1987-10-05 1991-07-03 Int Computers Ltd Image display system

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Title
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WO1992003798A1 (fr) 1992-03-05

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