EP0487715B1 - Drucker mit leuchtdiodenanordnung - Google Patents

Drucker mit leuchtdiodenanordnung Download PDF

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Publication number
EP0487715B1
EP0487715B1 EP91912735A EP91912735A EP0487715B1 EP 0487715 B1 EP0487715 B1 EP 0487715B1 EP 91912735 A EP91912735 A EP 91912735A EP 91912735 A EP91912735 A EP 91912735A EP 0487715 B1 EP0487715 B1 EP 0487715B1
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EP
European Patent Office
Prior art keywords
current
image data
led
recording
printer apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP91912735A
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English (en)
French (fr)
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EP0487715A1 (de
Inventor
Martin Potucek
Mary Hadley
Jeffrey A. Small
Michael William Mattern
Keith W. Agar
Hieu T. Pham
Yee Seung Ng
Jeremy K. Chung
Kenneth D. Kieffer
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Eastman Kodak Co
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Eastman Kodak Co
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Priority claimed from US07/543,929 external-priority patent/US5253934A/en
Priority claimed from US07/543,930 external-priority patent/US5126759A/en
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of EP0487715A1 publication Critical patent/EP0487715A1/de
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
    • B41J2202/01—Embodiments of or processes related to ink-jet heads
    • B41J2202/17—Readable information on the head

Definitions

  • the present invention relates to non-impact printer apparatus for recording, and more specifically, to circuitry thereon for controlling current uniformity to the recording elements.
  • an L.E.D. (light emitting diode) printhead wherein control of current to the LED's during recording is provided by a current mirror circuit.
  • This circuit features an adjustable resistor and voltage supply to allow the respective currents to the LED's to be controlled so that adjustments may be provided to have the outputs of the LED's be more uniform.
  • each driver chip is separately adjustable so that LED's driven from this driver chip receive sufficient current so that their respective intensities are similar to that of LED's driven by other driver chips on this printhead.
  • Another aspect of adjustability requires the LED's to put out sufficient light to expose the recording medium such as a photoconductor.
  • the PATENT ABSTRACTS OF JAPAN vol. 13 no. 299 discloses an optical array printer which comprises a plurality of recording light-emitting elements.
  • an additional light-emitting diode is provided in order to monitor the temperature of a optical print head.
  • the light from this light-emitting diode is detected by a light receiving element.
  • a differential amplifier generates a correction voltage which is fed back to adjust the current through the light-emitting elements which are responsible for the recording of data.
  • the apparatus for the herein disclosed invention is typified by the diagram of FIG. 1; a linear array 10 of say 3584 triggerable recording elements; e.g. LED's, is disposed to expose selectively a photosensitive image-receiver medium 12 that is movable relative to the array by suitable conventional means (not shown). While the embodiments of the invention will be described in terms of LED printheads, other recording elements may also make use of this invention. Optical means for focusing the LED's onto the medium may also be provided. In this regard, gradient index optical fiber devices such as Selfoc (trademark of Nippon Sheet Glass Co., Ltd.) arrays are highly suited. The LED's of the array are triggered into operation by means of image processing electronics 14 that are responsive to image signal information.
  • image processing electronics 14 that are responsive to image signal information.
  • the exposure effected by such LED is more or less made.
  • the medium 12 is, say, photographic film
  • the latent image formed line by line by selective exposure of said LED's may be subsequently developed by conventional means to form a visible image.
  • the medium 12 is an electrophotographic receptor
  • the LED's may be used to form an electrostatic image on a uniformly electrostatically charged photoconductor and this image developed using opaque toner particles and perhaps transferred to a copy sheet, see U.S. Patent 3,850,517 and 4,831,395.
  • a data source 15 such as a computer, word processor, image scanner or other source of digitized image data, provides image data signals to a data processor 16 which may comprise a raster image processor.
  • the data processor under control of clock pulses from a logic and control device (LCU) 13 provides a plurality of outputs including rasterized data outputs and control signals which are fed to the printhead.
  • Data for each pixel may be represented by a multibit signal of say 4 bits representing a grey level for exposure for recording that pixel.
  • a programmable ROM (PROM) 16a may be provided either on or off the printhead to modify the data to provide for uniformity correction from LED to LED.
  • the PROM transforms the 4-bit signal into a 6-bit grey level signal that is adjusted or corrected for the light-emitting characteristics of the respective LED. This balance in light output from LED to LED can be corrected by modifying the data bit signals in accordance with empirical determinations.
  • the PROM has stored therein correction factors associated with each LED for modifying that LED's respective data. As will be described below, this PROM may be modified in accordance with age and/or temperature changes to the printhead.
  • the LCU provides exposure clock pulses to a down/up counter 18 (FIG.
  • the comparators 19 all compare the output of the counter 18 with the value of the respective data.
  • the image data signals provided to each comparator relates to a desired ON time or period of enablement for a respective LED 30 for the recording of a particular pixel.
  • the LED's are alternately divided into odd and even-numbered LED's so that respective integrated circuit driver chips 40 therefor are located on opposite sides of the line of LED's.
  • the discussion herein will be made as to one of these driver chips.
  • the image data signals provided to each comparator 19 during the printing of a single line of dots by the row of LED's is related to the desired pixel or dot size to be exposed onto the image receiver medium by that LED for that particular line of dots.
  • six independent lines of data DI0 through DI5 provide a six bit digital image data signal that allows for grey-scale variation of the output of each LED during each cycle of operation.
  • the data to each comparator may comprise six binary bits representing an amount from decimal 0 to decimal 63.
  • the data lines DI0 through DI5 are shown passing through the data registers 24 in FIG. 4, it will be appreciated that this is for the convenience of this illustration and that actually such lines comprise a plurality of data lines that are simultaneously available to all latches as will be described below.
  • an LED, LED 1 is to be enabled for a time period equal to 20 clock periods plus T MIN .
  • T MIN represents a pre-established minimum LED on time.
  • the counter 18 is enabled and commences to count exposure clock pulses from line 17 from decimal 63 to 0. Note that the clock pulses may be generated to have a variable programmable period.
  • the six bit output of counter 18 is coupled to one set of inputs at terminal X of each of the comparators. This count is now compared with the data input at another set of inputs at terminal Y of this comparator which represents in binary form decimal ten.
  • a programmable read only memory device or PROM or other programmable device may store the characteristics of each LED and data for that LED can be modified to provide an input count at terminal Y that represents data modified by the exposure characteristics of the LED. For example, for an LED that is a relatively strong light emitter the PROM would modify data bits for that LED to reduce the count that otherwise would be provided at terminal Y based solely on the data.
  • the driving circuitry for the LED's are provided on opposite sides of the line of LED's 20. This is a known desirable arrangement for permitting LED's to be packed closer together to provide greater image resolution capabilities for the printer.
  • the circuit arrangement is an alternating one such that what may be called the even-numbered LED's have their respective driving circuitry located to one side of the line of LED's and what may be called the odd-numbered LED's have their respective driving circuitry located to the other side of the line of LED's.
  • groups of, say, 64 of the odd numbered LED's (in a chip array 31 having 128 LED's arranged in a row) will have their respective driver circuitry formed in a single integrated circuit chip 40 and thus, for a printhead having 3584 LED's on the printhead, there may be 28 driver chips located on each side of the line of LED's.
  • driver chips it is desirable that they be identical.
  • the driver chips it is desirable for design simplicity that signals traversing the length of the printhead be programmably movable in either direction; see in this regard U.S. Patent 4,746,941.
  • LED chip arrays having more than 128 LED's are also known but the invention will be described with reference to those having 128 LED's.
  • the image data signals are output by the data processor 16 in accordance with image data signals for the odd-numbered LED's and image data signals for the even-numbered LED's. Discussion will now be made with regard to the image data signals for the odd-numbered LED's, since operation and circuitry for driving the even-numbered LED's is identical.
  • data lines DI0 - DI5 are independent lines each carrying a signal representing a digital bit (0 or 1) so that together their respective signals define a digital six bit number from decimal 0 to decimal 63.
  • This image data signal is passed along lines DI0 - DI5 on the printhead which comprise an image data signal bus.
  • a data register means 24 for latching data from this bus during each cycle of operation for printing a single line of dots or pixels.
  • a token bit is used to enable a data register means associated with a particular LED to accept the data while other data register means associated with other LED's await their respective data.
  • the use of a token bit in a printer apparatus for controlling latching of multibit data is described in U.S. Patent 4,746,941.
  • the pair of latches are connected in a master-slave relationship wherein in response to a token bit signal at the enable input terminal of the master latch 25, an image data signal at the data input terminal of the master latch 25 will cause the output of the master latch to either change or remain the same depending upon the image data signal.
  • the six master latches 25 in the data register means of each LED are commonly connected to a line 27 to simultaneously receive the token bit signal from the token bit shift register 28.
  • the token bit shift register 28 comprises a series of flip-flops 29 which have clock pulses (SHFTCLK) applied to the clock terminals thereof and the signal representing the token bit input to the data input terminal of each. Note that the same token bit signal will be provided to both the even and odd token bit shift registers for the even and odd numbered LED's.
  • the output of each of these flip-flops 29 is connected to the data input terminal of the next flip-flop 29 in the series.
  • Buffers 31 with enable inputs and direction controls are coupled to the token bit shift register 28 so that programmable control may be made of the direction for shifting the token bit along the token bit shift register 28. In the example where the token bit is to be shifted from left to right in FIG.
  • the signal line TDIR (token direction) is made at an appropriate logic level to allow the token bit on line LTOKEN to pass from left to right.
  • the token bit is passed from stage to stage (left to right in FIG. 4) of the token bit shift register 28 and accordingly outputted sequentially over respective lines 21 through OR gates 11 to lines 27 for enablement of all the master latches 25 of a respective data register 24.
  • the data bits occurring on lines DI0-DI5 are accepted by the data registers 24 in turn from left to right until all the 1792 data registers on this side of the printhead have acquired their respective six bits of data.
  • a latch enable signal is then pulsed low on line LLATCHN to cause the respective slave latches 26 to latch the data at their respective outputs and to reset the toggle flip-flops 22.
  • the respective outputs of the slave latches 26 are now communicated to the data input terminals Y of the respective comparators 19 for determining the duration of exposure for each LED in accordance with the techniques described above.
  • the master latches 25 are now free to receive the image data signals for the next line of dots to be recorded.
  • the comparators 19 each have at an output an AND gate 19' and a D type flip-flop 19'' in order to prevent the propagation of extraneous logic glitches from the comparator outputs to the toggle flip-flop inputs.
  • each driver chip 40 is shown.
  • the respective outputs of the toggle flip-flops 22 are fed over respective lines 45 1 , 45 3 , and the following lines not shown 45 5 , --- 45 125 and 45 127 .
  • each of these lines is actually a double line one of which carries an enable signal to turn the respective LED on and the other carries a complement of this signal.
  • the lines 45 1 are input to respective control electrodes of transistors Q 426 , Q 427 . These transistors act as switches and form a part of a current mirror driving circuit that includes a master circuit formed by transistors Q 424 , Q 425 and a series of digitally controlled transistors.
  • these digitally controlled transistors may be selectively turned on to establish a signal I (CHIP BIAS) to thereby regulate a desired current level for the LED's driven by this driver chip.
  • I CHIP BIAS
  • FIGS. 6A and 6B More details concerning the digitally controlled transistors will be found below with reference to the discussion of FIGS. 6A and 6B. Briefly, these digitally controlled transistors may be selectively turned on to establish a signal I (CHIP BIAS) to thereby regulate a desired current level for the LED's driven by this driver chip.
  • I CHIP BIAS
  • the current through the master circuit establishes a potential V G1 on line 117.
  • two transistors Q 428 , Q 429 Directly in series with LED 1 are two transistors Q 428 , Q 429 .
  • Transistor Q 428 is biased to be always conductive while transistor Q 429 is switched on and off and thus is the transistor controlling whether or not current is driven to LED 1 .
  • the gate or control electrode of transistor Q 429 is coupled to the drain-source connection of transistors Q 426 , Q 427 .
  • transistor Q 427 When LED 1 is to be turned on, transistor Q 427 is made conductive and when LED 1 is to be turned off, transistor Q 426 is made conductive.
  • the gate of transistor Q 426 receives a logic signal that is the inverse of that to gate Q 427 from a data driven enabling means 22 that is the circuitry of FIG. 4 which controls whether or not an LED is to be turned on and for how long.
  • the LED is to be turned on for a duration determined by the grey level data signals input
  • an additional current mirror that includes two slave circuits.
  • One slave circuit comprises transistors Q 420 , Q 421 and Q 430 .
  • the other slave circuit comprises transistors Q 422 , Q 423 and Q 431 .
  • Transistors Q 430 , Q 431 are N-channel MOSFETS while the other transistors noted above are P-channel MOSFETS.
  • the currents through these slave circuits establishes a voltage level V G2 on line 114, which is the potential of the drain electrode of transistor Q 427 .
  • transistor Q 426 In operation with transistor Q 429 turned off, transistor Q 426 is on and impresses approximately the voltage V cc at the gate of transistor Q 429 .
  • LED 1 When LED 1 is to be turned on to record a pixel (picture element), a signal is provided by the data enabling means 22 to the gate of transistor Q 427 to turn same on, while an inverse signal turns transistor Q 426 off.
  • the capacitive load or change existing between its gate and substrate must be removed.
  • transistor Q 427 turns on, the charge on the gate terminal of transistor Q 429 discharges through transistors Q 427 and Q 430 .
  • This path for discharge of the gate capacitive load at transistor Q 429 thereby provides a turn-on time not affected by the number of LED's that are sought to be simultaneously energized.
  • the reason for this is that each control transistor corresponding to transistor Q 429 has its own respective path for discharge of its respective capacitive load. While the illustrated embodiment shows use of the additional current mirror circuit containing transistor Q 430 for use in discharging the control electrode of the driving transistor, it will be understood that in some circuit arrangements, charging, rather than discharging, of the control electrode may be facilitated.
  • the potential difference between the gate and source terminals of transistor Q 420 remains fixed as does that of transistor Q 421 thereby establishing a voltage level V G2 on line 114 which varies with V cc although the potential difference V cc -V G2 remains constant.
  • the voltage level V G2 is established at the gate of transistor Q 429 via now conducting transistor Q 427 .
  • the voltage level at the source terminal of transistor Q 429 is now at a fixed threshold value above that of V G2 .
  • Transistor Q 429 acting as a cascode transistor and having its source terminal connected to the drain terminal of transistor Q 428 , thereby establishes the drain potential of the transistor Q 428 as varying with changes in V cc .
  • the potential difference V GS1 is constant even though V cc itself varies.
  • the voltage relationships between the various terminals of transistor Q 428 are not affected by variations in V cc and the current to LED 1 during a period for recording a pixel stays constant.
  • transistor Q 429 conducts current to LED 1 for a time period controlled by the data bits for recording an appropriate pixel.
  • the level of current for recording this pixel is controlled by the current mirror which is responsive to the current level I(CHIP BIAS).
  • transistor Q 429 When transistor Q 429 is turned on, the current passing there through mirrors, i.e., is either the same or proportional to, the current passing through transistor Q 425 .
  • the current passing through transistor Q 425 is equal to I(CHIP BIAS).
  • this current, I(CHIP BIAS) in turn is controlled by three factors comprising a temperature compensated current source 172, a first group of eight digitally controlled NMOSFET transistors Q 25 , Q 26 ..., Q 31 , Q 32 and a second group of eight digitally controlled NMOSFET transistors Q 5 , Q 6 ..., Q 11 , Q 12 .
  • Transistors Q 25 ,..., Q 32 are parallel connected transistors whose respective gate width to gate length ratios are scaled so that their respective currents are scaled or weighted in powers of two.
  • respective gate width to gate length ratios may be 256 5 : 128 5 : 64 5 : 32 5 : 16 5 : 8 5 : 4 5 : 2 5 and 321.5 5 for non-digitally controlled transistor Q 33 .
  • Each digitally controlled device or transistor is controlled by a logic signal applied to a respective two-transistor switch circuit associated with the transistor.
  • the circuit defined by NMOSFET transistors Q 250 and Q 251 cause current to flow through transistor Q 25 when a high level logic signal is applied to the gate of transistor Q 250 and a complementary low logic signal is applied to the gate of transistor Q 251 .
  • the logic signals for controlling which of the current-carrying transistors are to be turned on are controlled by a register R 2 which stores an 8-bit digital word and its 8-bit complement representing a desired current control signal to turn on respective ones of the eight current conducting transistors Q 25 ,...Q 32 .
  • this group of transistors is used for "localized" control of LED current.
  • the digital word stored in register R 2 is specific for this driver chip and will be determined by adjustment of driver current to the LED's driven by this driver chip until the LED's each provide a desired light output level.
  • This digital word may be input to the register R2 from memory in the LCU or from a separate memory such as a ROM provided on the printhead.
  • This digital word may also be changed in response to the temperature of the driver chip as will be described below. Briefly, the level of current from an extra current mirror channel (#65) on each driver chip is used as a measure of temperature.
  • a voltage generated by this current is digitized and compared by the LCU with a value based on the digital words in register R1 and R2.
  • the LCU "writes" a new digital word into register R2, if a change in current level is required according to an algorithm stored in memory.
  • the LCU is programmed to provide or default to a particular set of digital words for placement into registers R 1 and R 2 .
  • the LCU may be programmed to maintain a count of prior activations of each LED and adjust a control voltage according to a program based on the aging characteristics of the printhead.
  • This digital word controls 8 current-carrying NMOSFET transistors Q 5 ,..., Q 12 .
  • Associated with this group of transistors is a continuously conducting NMOSFET transistor Q 13 .
  • Exemplary gate width to length ratios for weighted digitally controlled transistors Q 5 - Q 12 are 896 5 : 448 5 : 224 5 : 112 5 : 56 5 : 28 5 : 14 5 : 7 5 and 4027 5 for non-digitally controlled transistor Q 13 .
  • the 8-bit word and its 8-bit complement stored in register R 1 is the same as that stored in identical registers R 1 on the other driver chips. As the printhead ages, a new 8-bit digital word and its 8-bit complement is calculated by the LCU and input into the registers R 1 .
  • the calculation of this 8-bit word for aging may be based on empirical determinations made using similar printheads or based upon a calibration of this printhead using an optical sensor that senses the output from each or selected LED's or by sensing patches recorded on the photoconductor.
  • a third factor for adjustment to maintain LED uniformity of light output from chip-to-chip is a temperature-compensated current source 172.
  • This current source includes a temperature sensor and circuitry which will assist in boosting current to the LED's in response to increases in temperature.
  • Various circuits for accomplishing this are well known for example, see Gray and Meyer, Analysis and Design of Analog Integrated Circuits, 2nd edition, pages 733-735 and figure 12.28, the contents of which are incorporated by this reference. In this text description is provided of so-called V T (thermal voltage) - referenced current sources.
  • V T thermo voltage
  • the operation of the circuit of FIGS. 6A, B, C, and D will now be described.
  • the temperature adjusted current I o is conducted to ground via NMOSFET transistor Q 33 and some or all or none of the transistors Q 32 , Q 31 ,... and Q 25 depending upon the digital 8-bit signal and its 8-bit complement stored in register R 2 .
  • the voltage level at the source terminal of Q 33 is determined.
  • switching transistors are associated with each of these digially controlled transistors.
  • transistor Q 25 is controlled by switching transistors Q 250 and Q 251 in response to a signal causing Q 250 to conduct and Q 251 to turn off. The others are controlled similarly.
  • This voltage level, V TC is also applied to the gate of transistor Q 13 and thereby controls the current conducted by transistor Q 13 .
  • transistor Q 13 is the non-digitally controlled transistor associated with the digitally controlled transistor group Q 5 ,..., Q 11 , Q 12 . In accordance with the digital word stored in register R 1 selected ones of these transistors are caused to conduct thereby affecting the bias current level I (CHIP BIAS) through PMOSFET transistor Q 425 .
  • the current through PMOSFET transistor Q 425 is equal to the current conducted by the master circuit comprised of transistor Q 424 , which current is replicated or scaled by current mirrors of PMOSFET slave transistors Q 429 and Q 429' ,...etc., i.e., the current controlling transistors to LED 1 , LED 3 ---LED 127 , respectively, as well as the extra temperature sensing circuit using channel 65.
  • Transistor Q 429 is caused to conduct when its respective logic transistors Q 426 , Q 427 are appropriately signaled by data signals indicating a pixel to be printed.
  • transistor Q 427 turns on and biases the gate of transistors Q 429 to the level V G2 . Since transistors Q 424 and Q 428 have identical biasing, the current through transistor Q 429 will mirror or be scaled to that of transistor Q 424 for the time period for exposing a pixel as controlled by the duration of the logic low signal on line 45 1 (AN). As is noted in FIG. 6C, the current through Q 429 is fed to LED 1 , for the recording of a pixel. Identical current levels will be developed in the other channels directly providing current to respective other LED's. Thus, all LED's driven by this driver chip receive the same current for periods determined by their respective enablement signals and the currents thereto are appropriately adjusted to maintain constant the intensity of the LED's.
  • lines SEL1 and SEL2 establish a two-bit selection of four possible operating modes of the token system.
  • the options for these modes include a normal mode; i.e., one where the token is used for controlling image data to the appropriate registers 24 for latching image data; a load V REF mode wherein the digital current regulation word for loading register R 1 , the global bias, is established; a load R REF mode wherein the digital current regulation word for loading register R 2 , the local bias, is established.
  • the fourth mode is referred to as a bias monitor mode and is used to check on the level of current sent to the LED's by sequentially operating channel 65 of each driver chip.
  • the token bit for image data has been described above and is made when the "00" two-bit signal is established by the LCU at the inputs (SEL 2, SEL 1) of the 3:1 multiplexers 60 and the logic device 62 which forms a part of the circuitry of FIG. 5 referred to as the "serial interface for V REF /R REF loading and bias monitoring.”
  • the logic set may be in the form of interconnected logic AND gates. With a "00" signal, this serial interface is disabled. Data over lines DIO-DI5 is then appropriately latched by the master image data flip-flops 25 in registers 24 as described above during shifting of the token bit over the token line LTOKEN and token registers 29. Data is then transferred in accordance with the techniques described above to control the duration of on-time for recording respective pixels.
  • a global bias adjustment is called for by the LCU in response to a determination by the LCU that the criterion for the need for such adjustment is met.
  • a criterion may be a count of printing activations or time.
  • the LCU provides a signal "01" to lines SEL2, SEL1 during a non-production interval, as well as calculates, in accordance with an updating formula based on empirical data determined from aging this or similar printheads, an updated 8-bit digital word to be transmitted to all the driver chips.
  • This updated current regulating data is transmitted serially over a single line DI5 of the image data bus (DI0-DI5) to the data input of a series of cascaded flip-flop registers 70-77 which form on each driver chip the register R 1 for storing signals V REF(0-7) .
  • the data over DI5 is shifted through these registers 70-77 in response to the token clock (TCLK) operating through an AND gate 80. Since DI5 is a line forming a part of the data bus the signal on line DI5 is available to all the driver chips and is latched simultaneously by the other driver chips. Thus, the R 1 registers of all driver chips are loaded simultaneously with the current control data signals V REF(0-7) in the above manner.
  • the LCU In order to load the "localized” current regulation signals R REF(0-7) into registers R 2 , the LCU provides a "10" signal to SEL2 and SEL1. This enables latches 90-97 to be responsive to the token clock through AND gate 82.
  • the token bit carried on line LTOKEN is input via direction control gate 87 to latch register 90 and then shifted through associated latches 91-97 in response to the token clock signal TCLK.
  • the respective outputs of latches 90-97 are input to the clock inputs of registers R 2 storing the R REF(0-7) signals.
  • the data on line DI5 is latched by the token bit in latches 90-97, into the respective flip-flops 98a-h that comprise registers R 2 .
  • the token bit is shifted out of this driver chip (R REF token) and into an adjacent driver chip for latching DI5 into the R 2 register flip-flops for the current drivers in the next driver chip and so on.
  • the current control data from the LCU for register R 2 is specific or local to each driver chip even though this data is carried on a data line of an image data bus that is commonly connected to all the R 2 registers of the driver chips located on one side of the row of LED's.
  • bias monitor In this mode, current from an extra or 65th current driver channel on each driver chip is monitored by the LCU. In this mode, monitoring is done to determine whether or not an acceptable current level is being provided by the current drivers and therefore whether or not the power to the printhead should be effectively shut down or adjusted to avoid damage or to better control output of the LED's. Additionally or alternatively, the monitoring of current serves to provide an indication of LED temperature and is useful to provide for a determination of when data should be modified to correct for loss of intensity of light output by the LED's as they heat up during use. Although the use of V REF and R REF adjustments are used to control the level of current to the LED's driven by a particular driver chip, finer control can also be provided by control also of the pulsewidth duration of the LED's through correction of image data.
  • a problem situation that is monitorable is where a cooling fan for the printhead fails and the temperature of the printhead rises during printing.
  • the current level detected serves as a measure of temperature and when compared with the digital words stored in registers R 1 and R 2 indicates that a problem exists; i.e., the current level being generated is not within an expected range based on the control signals stored in registers R 1 and R 2 .
  • the LCU In the bias monitor mode, the LCU provides a signal "11" to lines SEL1 and SEL2. This causes the token clock to be clocked through AND gate 99 to enable a bias monitor register 100 which receives at its "D” input an output from a logic AND gate 101 which has as its inputs the token bit and a single bit "data" signal on data line DI5, representing whether or not the LCU is calling for monitoring of the current on this driver chip.
  • line DI5 is available to all driver chips (of the odd-numbered driver chips) but it is the token bit that is shifted from driver chip to driver chip that determines which driver chip is to latch this data into its respective register.
  • the outputs (regular and inverse) of the register 100 are switched and enables transistor Q T1 (FIG. 6D) which controls current through a calibrated temperature stable fixed resistor R (FIG. 3) that is commonly connected to the respective transistors Q T1 , Q T3 , Q T55 of all driver chips located on one side of the row of LED's.
  • the voltage level across the resistor R, 88 is related to the current on line 217 provided by transistor Q T1 , and this voltage level is sensed and converted by an analog to digital converter 89. A digital representation of this voltage signal is fed back to the LCU.
  • the LCU determines if the current is at an appropriate level in that chip.
  • One possible response by the LCU may be to remove power to the printhead by opening a suitable switch to the power supply supplying the printhead such as removing voltages V cc and V DD to the current source 172 via switch S (FIG. 6A). Note that because of the similar circuitry in channel 65 to that for the other driver channels on that chip, the current in channel 65 is similar to that of such other channels and thus is a measure of current that will flow to each LED for which the corresponding driver channel is enabled.
  • the entering of the bias monitor mode is advantageously done after V REF and/or R REF changes have been made to allow the LCU to determine that a safe and/or appropriate level of current to the LED's will be provided.
  • the LCU is programmed to enter this calibration mode after such changes and on any power-up operation or during an interframe. Assuming that sufficient time exists during recording this mode can also be entered during recording or during an interline time period.
  • the LCU may be programmed to provide current regulation data to the printhead to lower the current level until a safe level of current is detected. If none is detected, then the shutdown signal is generated to remove power to the printhead.
  • the LCU in this mode may count the token clock pulses and is thus able to determine which of the driver chips has the unsafe level of current. Since the voltage signal sensed by the A/D converter is also related to the temperature of the LED's driven by that driver chip such signal may also be used by the LCU to provide fine adjustment of current to the LED's by changing the 8-bit local current regulating signal R REF stored in registers R 2 in response to an algorithm relating temperature measured with signals to be fed to a respective driver chip's registers R 2 .
  • the signal relative to temperature may also be used to adjust the data signals to regulate or correct the on-time of the LED's using pulsewidth modulation.
  • the LCU may calculate a new correction program based on the fall off of intensity with temperature for the LED's. This new program is then input to the PROM 16a to adjust the corrected data sent to the printhead.
  • the 65th channels on the even driver chips are also commonly connected to the input of the A/D converter 89 (FIG. 3).
  • a reading of the voltage generated by a respective 65th driver channel on say an even-numbered driver chip is determined by having a logic high signal on the DI5 line on the even side with a corresponding low level signal on the DI5 line on the odd side since logic AND gate 101 (FIG. 5) on each driver chip passes the token bit only when the respective (odd or even) DI5 line is logic high.
  • FIGS. 7-9 Description will now be made of the embodiment of FIGS. 7-9 wherein similar numbers to that of the prior embodiment relate to similar structures.
  • image data and recording of same is handled in a similar way to that described above and is in accordance also with the description of U.S. Patent 4,746,941.
  • eight bits of image data are used instead of six but the principle of operation is similar using an 8-bit comparator for determining exposure duration.
  • the next line of data is sent down the data bus D o -D 7 and is latched in consecutive order by the respective master-slave latch registers 24 in accordance with the presence of a token bit in a respective register.
  • the token bit is shifted down the 64-bit bidirectional token bit shift register 28 and image data on lines D o -D 7 is latched in a respective latch register 24.
  • the token bit then exits the shift register and is shifted into the shift register of the next driver chip.
  • Current monitoring is also activated during a portion of the period that the token bit is present in the driver chip's token bit shift register.
  • a signal from the LCU is used to generate current in the 65th driver channel. The means for activation of the 65th driver channel will now be described further with reference also to FIG. 9.
  • a latch 111 coupled with the extra, or in this example the 65th, driver channel has its output enabled or say placed logic high in response to the location of the token bit in a specific stage (N) of the token bit shift register 28.
  • the output of token bit register stage N is coupled via the logic gates 186, 190 and 187, 191, respectively, to the preset and clear inputs of latch 111.
  • Current to the 65th driver channel terminates when the token bit has moved a fixed number of stages (say M stages) down the token bit shift register 28 in this same driver chip 40.
  • the latch (111) output is disabled or cleared.
  • the output of token bit register stage N + M is coupled via the logic gates 188, 190 and 189, 191, respectively, to the preset and clear inputs of latch 111.
  • the outputs of all the current monitors or 65th channels of all the odd-numbered driver chips are connected in parallel to a current to voltage converter which may be similar to that described above. These outputs are multiplexed by multiplexer 106 with the similar outputs of the current monitors to the even-numbered driver chips.
  • An A/D converter 89 converts the analog signal which is also related to the temperature of that driver chip (and approximates the temperature of the LED's driven by that driver chip) to a digital signal that is communicated over appropriate lines to the LCU.
  • the LCU by keeping track of the counts of the token clock for use in shifting image data, knows which driver chip the token bit is located in and thus which driver chip's 65th channel is being activated at this time. Note that while data for recording the next line of pixels is being sent over bus lines D o -D 7 and latched in appropriate master registers in response to the token bit, the previous line of pixels, whose data is stored in the slave registers of latches 24, is being printed by the LED's while the 65th channel driver channel is also activated.
  • the LCU recognizes that for a certain part of the period for which a token bit is resident within a driver chip (and for which the 65th channel monitoring is activated) the monitored current input to the multiplexer 106 must be odd.
  • the LCU is programmed to consider the current monitored signal from the A/D converter 89 as representing the current in driver chip #1, even though the token bit is simultaneously also in the driver chip #2.
  • the LCU recognizes that when the token has moved 33 clock pulses into a token shift register of a driver chip (but less than 64 clock pulses) the signals generated by the A/D converter to the LCU represent current to the LED's in a driver chip that is the even-numbered driver chip of the pair of driver chips having the token bit. Additionally, a select signal is provided by the LCU to multiplexer 106, which controls which of the current signals, odd or even, is to be sent to the LCU. The overall clock token count determines which odd and even pair of driver chips the token is in. If desired, the extra current to voltage converter and analog multiplexer may be omitted as in the printhead of FIG. 3.
  • a token direction signal biases line 220 at one logic level and through inverter 221, biases line 222 at an opposite logic level.
  • Tdir biases line 220 for transmission of the token bit that travels from left to right (Lbit) in FIG. 10.
  • the tristate inverters 31 used for transmission of the right to left going token bit are disabled.
  • the token bit is synchronized with pulses of the token clock (TCLK) and upon entering the driver chip, triggers the D input of the first token register of the token bit shift register to switch its outputs so that the Q output of the register is changed to enable the eight-bit latch 24 (FIG.
  • the current is monitored by the LCU via A/D converter 89 and in accordance with a program in the LCU the current is related to the temperature of the driver chip. This current is monitored until the token bit reaches the 32nd token register upon which event the Q output of this register resets latch 111. With movement of the token bit into the 33rd token register of driver chip #1, the LCU commences to monitor the current in the 65 driver channel of driver chip #2 as described above. As noted above, monitoring of the current is done first in driver chip #1 and then driver chip #2. The token bit then passes into driver chips #3 and #4 for monitoring the current in these chips as well as for latching of image data for these chips on lines D o -D 7 .
  • FIGS. 11-13 an improvement over the circuit of FIG. 10 is illustrated wherein in addition to use of the token bit for simultaneously controlling distribution of image data and use in monitoring current on driver chip temperature, there is also provided the use of the token bit for controlling the change of digital current regulation data in the driver chip just prior to recording each line of pixel data.
  • R REF or V REF digital current regulation data was provided during interframe or other non-production periods when no printing was occurring.
  • the digital current regulation data is provided during printing. This allows current not only to be monitored in real time but also to be changed more promptly as required.
  • a logic circuit 246 is provided in each driver chip to allow the circuit to discriminate between image data signals that control the pulsewidth time duration exposures used for recording the next row of image pixels or current regulation data signals which control the level of current to each LED activated during recording of the next row of pixels.
  • Data for adjusting R REF is provided by the LCU based upon the temperature-related current signals generated by each of the respective current drivers for the 65th current channel of each driver chip.
  • the LCU calculates a new 8-bit digital word for each driver chip to control the respective level of current in that driver chip.
  • a token bit is also generated on line Lbit and a control line labelled LD/Run is adjusted to a logic low level.
  • the line T dir is made a logic high level so that the logic circuit 246 has the four output lines thereof at suitable logic levels to disable the tristate inverters 31 associated with the image data token registers as well as disable the register 111 for disenabling the 65th current driver circuit.
  • the Q output of this register changes to provide a load signal to the latch register 113 (FIG. 8) for loading current regulation data carried on lines D o -D 7 .
  • the Q output of latch 112 is output to the Lbit input of the next driver chip so that with the next operation of the token clock, the output of Q changes. This provides the needed token pulse to the D input of the register 112 of the next driver chip.
  • the LCU at this time has also changed the current regulation data upon lines D o -D 7 to be appropriate for proper regulations of current in this next driver chip.
  • the token bit is simultaneously applied to odd and even-numbered driver chips so that current regulation data is provided simultaneously to an odd-numbered driver chip as well as to an even-numbered driver chip.
  • the LCU changes the LD/Run line to a logic high level and a new token bit is sent by the LCU to the first driver chips (odd and even) on the printhead for latching the image data signals on data bus lines D o -D 7 .
  • the register 111 will be set by the token bit to commence operation of the 65th channel current driver as described for the embodiment of FIGS. 7-9. Another difference in the embodiment of FIG.
  • 11 is the use of the first token register (rather than the second token register) to commence drive to the 65th channel current driver.
  • Other token registers may be designed for determining when the 65th channel is to be operated. It may be desirable for the LCU to have a small programmed delay as to when the LCU actually reviews the current data from the A/D converter 89 (FIG. 7). This delay will allow the driver current in the 65th current channel to stabilize.
  • An improved printer apparatus has been described which provides for fine control over adjustments of current to the recording elements as well as for correction of pulsewidth durations as required for temperature compensation. There is also ensured that destructive current levels will not be generated when current to the recording elements are adjusted.
  • this multibit data signal may be adjusted to correct for say the decrease in light output by the LED's driven by this driver chip due to the higher temperatures of the LED array chip driven by this driver chip.
  • the odd and even data from RIP 16 may be first modified by a correction PROM 16a before this data is sent to the printhead.
  • the correction PROM stores correction information so that an 8-bit word from RIP 16 is converted to a new 8-bit word that is corrected based on the temperature of the printhead to adjust pulsewidth duration.
  • the LCU signals the PROM as to the correction factor based on the temperature related data provided in reading the 65th driver current channels.
  • adjustability of the printhead to provide for uniformity is advantageously provided in several ways namely adjustment of current through use of current regulation data signals (V REF and/or R REF ) by using an image data bus during say an interframe to adjust a bias current I CHIP BIAS (FIGS. 6A, B, C and D) to the constant current driver circuits and by use of the adjustment to image data during production periods.
  • V REF and/or R REF current regulation data signals
  • I CHIP BIAS bias current regulation data signals
  • FIGS. 11-13 A further improvement is provided in the embodiment of FIGS. 11-13 demonstrating that data for providing further fine tune adjustment of current can be provided during each line of recording.
  • the described driver circuit retains the desirable feature of two-way addressability described in the prior art. That is, provision is made for digitally addressing each chip to correct for differences in light output by LED's driven by one chip versus those driven by another chip on the same printhead. These differences can arise due to processing condition differences arising during manufacture of the driver chips and for their respective driven LED's as well as nonuniformities arising from temperature differences.
  • a second provision for digital addressability is retained to provide for global changes due to aging. By providing both addressable portions on each driver chip problems associated with noise are minimized.
  • providing a non-digitally controlled transistor on each addressability portion simplifies calibration and allows for more accuracy in control of uniformity.
  • a temperature compensated current source 172 advantageously and promptly increases current on a real-time basis by altering current to a series of digitally addressable transistors. This provides for instantaneous changes in current levels to the LED's for providing at least some correction for temperature excursions and thus provides an additional device for complementing the main temperature control which is provided through selection of transistors in one series of digitally addressable transistors.
  • a printhead has also been described which provides efficient use of the electrical lines provided thereon.
  • Multibit image data is effectively latched into appropriate registers in accordance with a token bit.
  • Current regulation is effectively controlled using digitally addressed current regulation. Data for the image signals and current regulations are carried over the same lines, thereby reducing the need for additional lines. This reduces the number of bonding pads and connections required to be made in fabricating the printhead.
  • an LED printhead having an improved driving circuit for generating driving current to the recording elements that provides for turn-on times that are relatively independent of the number of recording elements turned on and further provides for constancy in light output by making the driving current insulated from changes in the driver voltage.
  • Modifications to the circuit may, of course, be made.
  • transistors Q425 and Q423 are used effectively as resistors and may be also eliminated.

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Claims (18)

  1. Berührungsloser Drucker mit
    - einem Aufzeichnungskopf (20) mit einer Vielzahl von Aufzeichnungselementen (30) zum Aufzeichnen auf ein Aufzeichnungsmedium (12);
    - Treibermitteln (40) mit einer Vielzahl von Stromtreiberkanälen zum wahlweisen Ansteuern der Vielzahl von Aufzeichnungselementen (30) gemäß der jeweiligen Bilddatensignale, wobei die Treibermittel (40) einen zusätzlichen Stromtreiberkanal (65) aufweisen, der weder einem Aufzeichnungselement noch irgendeinem lichtemittierenden Element zugeordnet ist, zum Erzeugen eines Stroms, welcher dem den Aufzeichnungselementen (30) Zugeführten Strom entspricht;
    - Mitteln (88, 89, 13) zum Überwachen eines dem Strom in dem zusätzlichen Treiberkanal (65) entsprechenden Parameters, wobei der Drucker eine Vielzahl von Treiberbausteinen (40) umfaßt, jeder Treiberbaustein (40) eines der Treibermittel (40) aufweist und die Überwachungsmittel außerhalb der Treiberbausteine (40) befindliche Mittel zum Empfangen von Signalen bezüglich des Parameters von jedem der Vielzahl der Treiberbausteine (40) aufweisen.
  2. Drucker nach Anspruch 1, gekennzeichnet durch eine Vielzahl von Token-Bit-Registern (29, R1, R2, 100), wobei mindestens eines der Register (100) jedem Treiberbaustein (23) zugeordnet ist; Mittel (16) zum Erzeugen eines Token-Bit-Signals; und vom Token-Bit-Signal abhängige Mittel (19, 23) die auswählen, welcher strombezogene Parameter des zusätzlichen Stromtreiberkanals (65) des Treiberbausteins zu überwachen ist.
  3. Drucker nach Anspruch 1, gekennzeichnet durch Mittel (13, S) zum Abschalten der Stromzufuhr zu den Aufzeichnungselementen (30) in Abhängigkeit vom Abtasten eines Strompegels, der für eine Aufzeichnung ungeeignet ist.
  4. Drucker nach Anspruch 1, gekennzeichnet durch Mittel (R1,R2,13) zum Einstellen der jeweiligen Ströme in einer Vielzahl von Stromtreiberkanälen in Abhängigkeit von dem Parameter, der dem im zusätzlichen Kanal (65) abgetasteten Strom entspricht.
  5. Drucker nach den Ansprüchen 1, 2, 3 oder 4, dadurch gekennzeichnet, daß die Treibermittel (40) einen Stromspiegel umfassen, der eine Hauptschaltung (Q424, Q425) aufweist und die Stromtreiberkanäle (23) der Hauptschaltung (Q424, Q425) untergeordnet sind.
  6. Drucker nach Anspruch 5, gekennzeichnet durch eine Vielzahl von digital adressierbaren Transistoren (Q5 - Q12, Q25 - Q32) zum Verändern eines Strompegels in der Hauptschaltung (Q424, Q425).
  7. Drucker nach den Ansprüchen 1, 2 oder 4, gekennzeichnet durch
    - Busmittel (D10 - D15) für Bilddaten zur Weiterleitung von Bilddatensignalen;
    - die Treibermittel (40), die entsprechende Datenregister (24) aufweisen, welche jedem Aufzeichnungselement (30) zum Speichern der Bilddatensignale zugeordnet sind;
    - Mittel zum gemeinsamen Verbinden der Datenbusmittel (D10 - D15) mit der Vielzahl der Datenregister (24), die der entsprechenden Vielzahl der Aufzeichnungselemente (30) zugeordnet sind;
    - Mittel (16) zum Erzeugen eines Token-Bit-Signals;
    - Mittel (28), die ein mehrstufiges Token-Bit-Schieberegister mit einer Vielzahl entsprechender Stufen (29) aufweisen zum sequentiellen Abgeben des Token-Bit-Signals in den jeweiligen Stufen und zum sequentiellen Auswählen eines entsprechenden Datenregisters (24) zur Aufnahme von Bilddatensignalen.
  8. Drucker nach Anspruch 2, dadurch gekennzeichnet, daß
    - die Aufzeichnungselemente (30) in einer Reihe angeordnet sind;
    - die Token-Bit-Register als zwei mehrstufige Token-Bit Schieberegister und die Treiberbausteine (40) in einer Folge von zwei Reihen angeordnet sind, wobei die Reihe der Aufzeichnungselemente (30) zwischen diesen beiden Reihen liegt;
    - Mittel (29) vorgesehen sind, welche die jeweiligen Token-Bit-Signale synchron durch das Token-Bit-Schieberegister (28) einer entsprechenden Reihe von Treiberbausteinen schieben; und
    - Mittel vorgesehen sind, welche auf die Abgabe eines Token-Bit-Signals in eine bestimmte Stufe (100) eines Registers ansprechen, das einem entsprechenden Treiberbaustein (40) zum Steuern der Stromüberwachung in einem zu sätzlichen Stromtreiberkanal (65) dieses Treiberbausteins zugeordnet ist.
  9. Drucker nach Anspruch 8, dadurch gekennzeichnet, daß die Aufzeichnungselemente (30) LEDs sind.
  10. Drucker nach Anspruch 8, gekennzeichnet durch Mittel (13, 15, 16) zum Angleichen von Bilddatensignalen in Abhängigkeit von in einem zusätzlichen Stromtreiberkanal (65) abgetastetem Strom.
  11. Drucker nach den Ansprüchen 1, 2 oder 8, gekennzeichnet durch Mittel (13, 15, 16) zum Angleichen von Bilddatensignalen an die Aufzeichnungselemente (30) in Abhängigkeit von dem Parameter, der dem in dem zusätzlichen Kanal (65) abgetasteten Strom entspricht.
  12. Drucker nach den Ansprüchen 1, 2 oder 8, gekennzeichnet durch Mittel (13, 16, R1, R2) zum Einstellen des Stroms für die Aktivierung der Vielzahl der Aufzeichnungselemente (30) in Abhängigkeit von einem Pegel eines Parameters, der dem in dem zusätzlichen Kanal (65) abgetasteten Strom entspricht.
  13. Drucker nach Anspruch 12, dadurch gekennzeichnet, daß die Treibermittel (40) einen Stromspiegel umfassen, der eine Hauptschaltung (Q424, Q425) aufweist und die Stromtreiberkanäle (23) der Hauptschaltung untergeordnet sind.
  14. Drucker nach Anspruch 13, gekennzeichnet durch eine Vielzahl von digital adressierbaren Transistoren (Q5 - Q12, Q25 - Q32) zum Verändern eines Strompegels in der Hauptschaltung (Q424, Q425).
  15. Drucker nach den Ansprüchen 12, 13 oder 14, gekennzeichnet durch
    - Busmittel (D10 - D15) für Bilddaten zur Weiterleitung von Bilddatensignalen;
    - eine Vielzahl von Bilddatenregistern (24) zum Speichern der Bilddatensignale, wobei die Bilddatenregister (24) jeweils den Aufzeichnungselementen (30) zum speichern der jeweiligen Bilddatensignale zugeordnet sind, um ein entsprechendes Aufzeichnungselement zum Aufzeichnen freizugeben;
    - Mittel (25, 26), die die Datenbusmittel (D10 - D15) mit der Vielzahl der Bilddatenregister (24) gemeinsam verbinden;
    - Mittel (16) zum Erzeugen eines Token-Bit-Signals; und
    - ein mehrstufiges Token-Bit-Schieberegister zum sequentiellen Abgeben des Token-Bit-Signals in den jeweiligen Stufen (29) zum sequentiellen Auswählen eines entsprechenden Datenregisters (24) zur Aufnahme von Bilddatensignalen.
  16. Drucker nach Anspruch 7 oder 15, gekennzeichnet durch Mittel (13, 16) zum Erzeugen von Stromregulierungsdaten in mindestens einer Zeile (D15) der Bilddatenbusmittel (D10 - D15) zum automatischen Steuern eines Strompegels zum Aktivieren der Aufzeichnungselemente (30) und Mittel (13, 16) zum Erzeugen eines Token-Bit-Signals, um auszuwählen, welcher Treiberbaustein (40) die Stromregulierungsdaten empfangen soll.
  17. Drucker nach Anspruch 16, gekennzeichnet durch Mittel (13, 16) zum Erzeugen von Stromregulierungssignalen während der Aufzeichnung durch die Aufzeichnungselemente (30) und Mittel (246), welche die Datenregister für die Aufnahme von Stromregulierungssignalen als Bilddatensignale sperren.
  18. Drucker nach den Ansprüchen 1 - 17, dadurch gekennzeichnet, daß der auf den Strom bezogene Parameter Strom ist.
EP91912735A 1990-06-26 1991-06-25 Drucker mit leuchtdiodenanordnung Expired - Lifetime EP0487715B1 (de)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US54350790A 1990-06-26 1990-06-26
US54389290A 1990-06-26 1990-06-26
US07/543,929 US5253934A (en) 1990-06-26 1990-06-26 L.E.D. array printer with extra driver channel
US543507 1990-06-26
US543929 1990-06-26
US543930 1990-06-26
US07/543,930 US5126759A (en) 1990-06-26 1990-06-26 Non-impact printer with token bit control of data and current regulation signals
US543892 1990-06-26
PCT/US1991/004488 WO1992000196A1 (en) 1990-06-26 1991-06-25 L.e.d. array printer

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EP0487715A1 EP0487715A1 (de) 1992-06-03
EP0487715B1 true EP0487715B1 (de) 1996-10-16

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JPH06143647A (ja) * 1992-06-08 1994-05-24 Eastman Kodak Co 感熱プリンタ
US5859657A (en) * 1995-12-28 1999-01-12 Eastman Kodak Company Led printhead and driver chip for use therewith having boundary scan test architecture
JP3906535B2 (ja) 1997-11-07 2007-04-18 ソニー株式会社 ダウンロードシステム、及び記録媒体
JP3732345B2 (ja) 1998-02-10 2006-01-05 株式会社沖データ 駆動回路、ｌｅｄヘッド及びプリンタ
DE69926229T2 (de) * 1998-05-01 2006-05-24 ZBE, Inc., Santa Barbara Verfahren und gerät zum aufnehmen von digitalen bildern auf fotosensitivem material
WO2000048840A1 (fr) * 1999-02-17 2000-08-24 Matsushita Electric Industrial Co., Ltd. Dispositif de formation d'images
JP4137088B2 (ja) 2004-06-02 2008-08-20 キヤノン株式会社 ヘッド基板、記録ヘッド、ヘッドカートリッジ、記録装置、及び情報入出力方法
JP4194580B2 (ja) 2004-06-02 2008-12-10 キヤノン株式会社 ヘッド基板、記録ヘッド、ヘッドカートリッジ、及び記録装置
US9974130B2 (en) 2015-05-21 2018-05-15 Infineon Technologies Ag Driving several light sources
US9781800B2 (en) 2015-05-21 2017-10-03 Infineon Technologies Ag Driving several light sources
US9918367B1 (en) 2016-11-18 2018-03-13 Infineon Technologies Ag Current source regulation

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JPS5627370A (en) * 1979-08-10 1981-03-17 Canon Inc Driving device of thermal head
US4746941A (en) * 1987-10-13 1988-05-24 Eastman Kodak Company Dot printer with token bit selection of data latching
US4952949A (en) * 1989-11-28 1990-08-28 Hewlett-Packard Company LED printhead temperature compensation

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EP0487715A1 (de) 1992-06-03
DE69122718D1 (de) 1996-11-21
WO1992000196A1 (en) 1992-01-09
JPH05501684A (ja) 1993-04-02
JP3256225B2 (ja) 2002-02-12
DE69122718T2 (de) 1997-04-03

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