EP0476722B1 - Datenverarbeitungssystem - Google Patents

Datenverarbeitungssystem Download PDF

Info

Publication number
EP0476722B1
EP0476722B1 EP91120043A EP91120043A EP0476722B1 EP 0476722 B1 EP0476722 B1 EP 0476722B1 EP 91120043 A EP91120043 A EP 91120043A EP 91120043 A EP91120043 A EP 91120043A EP 0476722 B1 EP0476722 B1 EP 0476722B1
Authority
EP
European Patent Office
Prior art keywords
register
memory
instruction
task
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91120043A
Other languages
English (en)
French (fr)
Other versions
EP0476722A3 (en
EP0476722A2 (de
Inventor
Hiroyuki Kida
Hideo Maejima
Ikuro Masuda
Shirou Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60072646A external-priority patent/JPH0658629B2/ja
Priority claimed from JP60177542A external-priority patent/JPH0724025B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of EP0476722A2 publication Critical patent/EP0476722A2/de
Publication of EP0476722A3 publication Critical patent/EP0476722A3/en
Application granted granted Critical
Publication of EP0476722B1 publication Critical patent/EP0476722B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Definitions

  • the present invention relates to a data processing system according to the preamble portion of claim 1.
  • a data processing system is known from US-A-4 352 157.
  • microprogram control system A microprogram-controlled data processing system is generally constructed using an instruction decoder which generates the microprogram ROM address from the instruction word.
  • instruction decoder which generates the microprogram ROM address from the instruction word.
  • this system necessitates a large scale hardware for the instruction decoder, and a microprogram control system coping with this problem by elimination of the instruction decoder is proposed in Japanese Patent Unexamined Publication No. 57-203141.
  • this system sets the instruction word directly in part of the microprogram ROM address information, and therefore as the instruction word length increases from 8 bits to 16 bits and to 32 bits the length of the microprogram ROM address increases with it, resulting disadvantageously in an expanded microprogram ROM address decoder.
  • Another hardware scheme for upgrading the performance of microcomputers is the general-purpose register system, in which a microcomputer is provided therein with many registers so that various operations take place among registers with the intention of high-speed processing.
  • the program includes frequent task switching such as procedure call/return, the contents of the general-purpose registers need to be saved and resumed to/from the stack (a first-in-last-out memory) frequently at each switching.
  • the time used for the saving and resuming operations increases the total processing time, and speedup of processing can be hampered.
  • the time used for the saving and resuming operations is enormous for a system having a large number of general-purpose registers.
  • the GB-A-1 233 270 shows furthermore a digital computer arranged to execute a plurality of programs concurrently, wherein the temporary registers in which data used and generated during the execution of the programs is held are comprised only of storage locations in main store, wherein a set of storage locations being allotted to each program.
  • An object of this invention is to provide a data processing system having enhanced functions and performance and a versatile and flexible data processing system of the type of multiple register sets system capable of defining arbitrarily the number of registers for storing parameters used commonly among procedures and the number of registers for storing data specific to each procedure.
  • the object is solved according to the features of the independent claim.
  • the dependent claims show advantageous embodiments of the invention.
  • the data processing system is of the type of instruction decoding system in which an instruction word (machine word) read out of the main memory is arranged into an intermediate machine instruction word in the orthogonal format suitable for the decoding hardware arrangement and then the intermediate machine word is decoded.
  • An instruction word in the orthogonal format is defined here to be an instruction word having information bits representing operand specifiers for identifying an operation code spesifying the operation to be executed and locations in the main storage containing operands.
  • the bit positions for the operation code and operand specifying differ depending on each instruction so that information on the operation and operands is contained in the limited instruction word with less redundancy.
  • this type of instruction has been decoded or used for microprogram ROM address generation, and therefore the system needs to incorporate a large scale address generating hardware for the decoders and the like.
  • the system performs instruction decoding by initially converting an instruction word into an instruction word of the orthogonal format suitable for decoding, noting the facts that the bit arrangement of instruction words which are not orthogonal is not completely random, but has some rule, and translation of instruction words not orthogonal into orthogonal instruction words is relatively easy, and the decoding hardware and ROM capacity can be reduced when the microprogram ROM address is generated by decording an orthogonal instruction word.
  • the system incorporates decoders for arranging instruction words into intermediate machine words separately for each instruction format so that decoding of intermediate machine words takes place commonly for every instruction format, with the intention that instruction words of different formats or different word length can be processed.
  • the inventive system can deal with instruction words in different formats without modifying or adding the hardware arrangement within the processor, except for the instruction word storage and the translation unit which arranges instruction words into intermediate machine words for decoding, and the hardware arrangement used for instruction decoding can be reduced to 1/5 to 1/10 of the counterpart of the conventional instruction decoder system.
  • the system can process instruction words having at least two instruction formats.
  • the inventive system is provided with instruction-controlled registers and memory capable of arranging a register set in correspondence to the contents of the registers, so that register sets for procedures are placed in the memory in accordance with the register contents.
  • the number of register sets provided in the memory is made variable depending on each process, whereby the registers are used efficiently.
  • the remaining portion of the memory where register sets are not placed can be used as part of the main memory, whereby the hardware resources can be used efficiently.
  • a single register in a physical sense is used to set data used commonly by several tasks in transacting parameters among procedures so as to eliminate the need of data transfer among registers when the procedure is changed, whereby overhead of data processing is reduced and the processing speed of the data processing system is enhanced.
  • the inventive system merely needs the switching of register sets at the switching of tasks caused by the occurrence of interrupt events, eliminating the need for data saving and restoration to/from the main memory or the like, whereby tasks can be switched quickly and the processing speed can be enhanced.
  • the present invention improves the decoding function for instructions in reading the microprogram ROM without increasing the scale of hardware.
  • the invention can provide a high performance, high functioning data processing system without a significant increase in the hardware arrangement, but through the efficient use of the hardware resources while employing the general-purpose register system.
  • Fig. 2 shows an embodiment of this invention, which is applied to a microcomputer 10 constructed on a single semiconductor substrate.
  • the arrangement includes a central processing unit 101 as a nucleus, a main memory 102, a peripheral circuit 103 having the timer function and input/output function, a direct memory access controller 104, and an address translator 105.
  • a processor section 20 enclosed by the dashed line in Fig. 2 will be described in detail in connection with Figs. 1 and 3.
  • Fig. 1 shows an embodiment of the processor section 20, and it consists of an instruction word memory/translation unit 201, a microprogram memory/control unit 202 including a microprogram ROM (Read Only Memory) as a principal element, a decoder unit 203, an operation unit 204, a bus interface unit 205, a first main memory 206 operative for reading and writing, a second memory 207 operative for only reading, an address input/output buffer 2082, a data input/output buffer 2083, a clock and power supply buffer 2084, and an input/output buffer 2081 for signals, except the address/data clock and power supply, transmitted or received by the processor section 20 to/from the other functional blocks 103, 104 and 105 in Fig. 2.
  • a microprogram memory/control unit 202 including a microprogram ROM (Read Only Memory) as a principal element, a decoder unit 203, an operation unit 204, a bus interface unit 205, a first main memory 206 operative for reading
  • the contents of the program (instruction) fetching register (instruction address register) in the bus interface unit 205 are read out over the bus 212 into the main memories 206 and 207 in the processor 20 and, at the same time, into the address input/output buffer 2082 so that the contents are sent out over the bus 222 outside of the processor 20.
  • An instruction word is read out of the first main memory 206 or second main memory 207 by being addressed by the above input onto the bus 213, or an instruction word on the bus 223 is read in through the data input/output buffer 2083 onto the bus 213.
  • Information on the bus 213 is fed into the instruction word memory/translation unit 201.
  • the instruction word received by the instruction memory/translation unit 201 is held in it and at the same time decoded into information to be sent to the microprogram memory/control unit 202.
  • the microprogram memory/control unit 202 receives the information provided by the instruction word memory/translation unit 201 over the bus 231, and sends it as a microinstruction string over the bus 232.
  • the microinstruction from the microprogram memory/control unit 202 is sent over the bus 232 into the decoder unit 203, which decodes the microinstruction into signals 233 which directly control the operation unit 204 and signals 234 which directly control the bus interface unit 205.
  • the operation unit 204 implements data operations specified by the signals 233.
  • the bus interface unit 205 performs the timing control for data transfer within the processor 20 or between the processor 20 and other functional blocks using the bus 211, input/output buffer 2081, bus 221 and signal lines 235 and 236.
  • the clock and power voltage supplied to the buffer 2084 are distributed to the units using a signal line 214.
  • Fig. 3 shows an example of the arrangement of the instruction word memory/translation unit 201, microprogram memory/control unit 202, decoder unit 203 and operation unit 204.
  • the instruction word transferred over the bus 213 to the instruction word memory/translation unit 201 is held temporarily in the instruction word memory 301 and then transferred to the first instruction decoding means, i.e., the instruction decoder 302.
  • Fig. 4 shows typical instruction formats of instruction words read into the instruction memory 301.
  • An instruction of this type implements an operation between a first operand specified by the first operand code and a second operand specified by the second operand code and stores the result in the location of the second operand.
  • the type of operation specified in the operation code designates one of the arithmetic or logic operations.
  • An instruction of this type causes the program sequence to branch to the program address indicated by an operand specified by the first operand code upon fulfillment of the branch condition given in the operation code. If the branch condition is not met, the instruction causes the program sequence to proceed to the next instruction word.
  • An instruction of this type tests the value of a bit position specified by the bit number, i.e., a first operand, in the second operand specified by the second operand code, and memorizes the bit value. Thereafter, the instruction implements one of operations (clear, set, change, test) indicated by the bit operation type in the operation code for the specified bit, and stores the result in the corresponding bit position of the second operand when necessary.
  • the instructions categorized in (1), (2) and (3) are systematized at the sacrifice of orthogonality due to the restriction in word length of an instruction as a result of formatting for the intended functions in a limited word length in accordance with a certain rule.
  • the embodiment shown in Fig. 3 operates in the instruction decoder 302 to decode instruction words read out of the instruction word memory 301 so that information of various kinds necessary for the instruction execution is converted into instructions having a complete orthogonal code system (will be termed "intermediate machine words" hereinafter).
  • Each intermediate machine word has an operation code for specifying the operation to be executed and information bits representing some operand specifier codes which identifies the location in the main memory where the operand is contained.
  • the intermediate machine word is stored in the memory 303, and then fed to the microprogram memory/control unit 202 and the second instruction decoding means, i.e., the decoder unit 203.
  • Some of intermediate machine words include at least one operand specifier, and information of as to whether the operand indicated by the operand specifier is a source operand or a destination operand is entirely expressed in the operation code.
  • control signals 233 produced by these decoders in the decoder unit 203 control the operation unit 204 so as to execute an intended operation indicated by the intermediate machine word.
  • Fig. 5 shows another embodiment of the instruction word memory/translation unit, in which there are two instruction decoders for decoding an instruction held in the instruction memory means 301 into an intermediate machine word.
  • the system is provided with an instruction decoder 302 for decoding instructions in instruction system A and an instruction decoder 502 for decoding instructions in instruction system B.
  • Information created by the instruction decoder 302 is sent over the bus 3021 to the multiplexer 503.
  • information created by the instruction decoder 502 is sent over the bus 5021 to the multiplexer 503.
  • the multiplexer 503 selects one of the buses 3021 and 5021 basing on the contents of the flip-flop 504, and stores the selected contents in the memory 303.
  • the two instruction decoders 302 and 502 generate exactly the same intermediate machine word. Namely, if instruction words of different instruction systems have the same instruction function, they have the same information stored in the memory 303, the most hardware 500 in the processor 20 controlled by the intermediate machine word (hardware in the processor 20 excluding the instruction memory/translation unit 201 in Fig. 2) can be used and controlled commonly by instruction words of different instruction systems.
  • the flip-flop 504 is set to the predetermined signal level which is received at the terminal 505 and detected by the control circuit 506 when the processor 20 is reset.
  • the terminal 505 uses the lowest-order bit of the address bus.
  • Fig. 6 shows still another embodiment of the instruction word memory/translation unit 201, in which instruction words read into the instruction memory 301 through the bus 213 and intermediate machine words created by the instruction decoder 302 and instruction decoder 502 and stored in the memory 303, shown in Fig. 5, are stored together in the main memory 600.
  • the main memory stores instruction codes of two instruction systems, one type of codes being fed via the instruction memory 301 to the instruction decoder 302, translated into intermediate machine words by the decoder 302, fed over the bus 3021 to the multiplexer 603, selected by the multiplexer 603 and stored in the memory 303, while another type of codes being fed through the instruction memory 601 and bus 6011 to the multiplexer 603, selected by it and stored in the memory 303.
  • the multiplexer 603 selects one of information on the bus 3021 and bus 6011 depending on the contents of the flip-flop 604.
  • the instruction words stored in the main memory 600 have the definition of the instruction which can switch the multiplexer 603, and by executing the instruction the flip-flop 604 can be controlled through the control line 6041.
  • the flip-flop 604 may be controlled by detecting the signal level received at the terminal 605 by the control circuit 606 as shown in Fig. 7.
  • the multiplexer 603 and memory 303 are designed to control the contents of the instruction memory 601 in byte (8 bits) units, allowing applications which do not need the instruction memory 601 to enter information to the multiplexer 603 in the same word length as of the bus 213.
  • Fig. 8 is a block diagram showing separately the functions of the instruction memory/translation unit 201 shown in Fig. 3. The functions of the blocks are as follows.
  • Instruction memory means 301 (1) Instruction memory means 301
  • the arrangement of the operation code and operand code differs depending on each instruction word.
  • an instruction word read out of the instruction memory means 301 over the bus 3011 is collated with the code pattern which has been defined in the code collation means 802 so that the coincidence is detected.
  • Code arrangement information for translating an instruction word into an intermediate machine word having the orthogonal instruction format is defined and stored in this memory means.
  • the defined arrangement information is read out of the memory means over the bus 8031 in response to the signal 8021 from the code collation means 802.
  • the intermediate machine word has its operation code for specifying the operation to be executed and its operand specifier for identifying the memory location containing the operand being arranged in separate bit positions.
  • Some instructions except those which do not need operands include at least one operand specifier.
  • Fig. 9 shows an embodiment of the instruction memory/translation unit shown in Fig. 8, and it consists of an instruction memory means 301 made up mainly of a first-in-first-out (will be termed simply “FIFO” hereinafter) memory 901 and its control circuit 911, a code collation means 802 and code arrangement information means 803 made up mainly of programmable logic arrays (will be termed simply "PLA” hereinafter), and an arrangement means 804 made up mainly of a switch array using, for example, metal oxide semiconductor (will be termed "MOS” hereinafter) transistors.
  • Fig. 10 shows the timing relationship of signals a through j in Fig. 9 together with the basic clocks ⁇ 1 and ⁇ 2 .
  • an instruction word read out of the main memory is fed over the bus a and latched in the data buffer b.
  • the latched data is transferred over the bus 213 to the FIFO memory 901 in synchronism with the basic clock ⁇ 2 .
  • the control circuit 911 controls the writing of data on the bus 213 into the FIFO memory through the signal line 9110.
  • an instruction to be executed is read out of the FIFO memory 901 onto the bus c and it is latched in the FIFO buffer 921.
  • the code collation means 802 and code arrangement information memory means 803 are formed of dynamic PLAs 902 and 903 made solely of NMOS transistors, except for the precharging circuit and driver.
  • an input latch 912 and output latches 913 and 914 are added.
  • the timing of signals after the signal d has been entered to the latch 912 until the output h of the latch 913 and the output i of the latch 914 are determined is as shown in Fig. 10.
  • the signal h is the instruction code prior to arrangement, and the signal i is arranged information.
  • the arrangement means 804 produces a signal j by making arrangement for the signal h in accordance with the signal i.
  • Fig. 11 shows in detail the instruction memory means in Fig. 9.
  • the FIFO memory 901 is formed of a single-port random access memory (will be termed simply "RAM" hereinafter).
  • the data lines 1100 are charged by the precharging circuit during the period of the basic clock ⁇ 1 , and they carry data during the period of the basic clock ⁇ 2 .
  • Sense amplifiers are provided for the amplification of read-out data.
  • the control circuit 911 consists of a write pointer (shown by WP in Fig. 11) for specifying the write location in writing an instruction word on the bus 213 into the FIFO memory 901, a read pointer (shown by RP in Fig. 11) for specifying the read location in reading out an instruction word from the FIFO memory 901, and +1 adders for incrementing the pointers.
  • Fig. 12 is a logic circuit diagram showing in detail the control circuit 911 shown in Fig. 11.
  • the figure shows an embodiment of the case where the FIFO memory 901 has a capacity of eight words (one word has the same word length as of the bus 213), i.e., each of the write pointer and read pointer is of three bits.
  • a bus 9111 is provided for transferring the contents of the write pointer and read pointer. Both pointers can be reset by the RESET ⁇ signal which becomes active when the FIFO memory 901 is cleared by the reset operation for the processor 20 or when a prefetched instruction in the FIFO memory is invalidated due to the execution of a branch instruction.
  • Signal 1200 is the signal indicating that there is no memory space in the FIFO memory 901 for fetching an instruction from the main memory, i.e., the FIFO memory 901 is filled with a prefetched instruction word and there is no space physically.
  • Signal 1201 is the signal indicating that there is a memory space of eight words available in the FIFO memory 901 for fetching instructions from the main memory, i.e., there is no instruction word prefetched in the FIFO memory 901.
  • Signal 1202 is the incrementing signal for the write pointer
  • signal 1203 is the incrementing signal for the read pointer
  • signal 1204 is the signal outputting the value of the write pointer onto the bus 9111
  • signal 1205 is the signal outputting the value of the read pointer onto the bus 9111.
  • Fig. 13 shows another embodiment of the instruction memory means 301 in Fig. 9, in which the FIFO memory 901 is controlled by the PLA.
  • the arrangement implements concurrently the control for fetching an instruction word from the main memory to the FIFO memory through the 32-bit bus and the control for transferring the contents of the FIFO memory to the instruction decoder in 16-bit word length.
  • the PLA which controls the data input/output to/from the FIFO memory satisfies the FIFO control state diagram shown in Fig. 14.
  • the PLA 1300 changes in its state in the range of ten states from S 1 to S 10 as shown in Fig. 14, and it becomes the S 1 state from any state by receiving the FIFO reset signal.
  • the states S 1 and S 6 indicate that the FIFO memory 1301 is empty (indicated by E in Fig. 14), i.e., no instruction word is yet fetched to the FIFO memory.
  • the states S 3 , S 5 , S 8 and S 10 indicate that the FIFO memory is full (indicated by F in Fig. 14) and there is no space in the FIFO memory 1301 for fetching a new instruction word.
  • the state of the PLA (S 1 -S 10 ) is memorized in the state memory 1302, which is revised by the signal 13002 when the PLA 1300 issues a new state.
  • Fig. 15 shows another embodiment of the FIFO memory 901 shown in Fig. 11, in which the FIFO memory 901 is controlled for reading and writing through the provision of the input data word length (number of bits of the bus 213) twice the output data word length.
  • the arrangement includes two word lines (15001 and 15002) for the read/write control of memory cells 1110.
  • Fig. 16 is a detailed logic circuit diagram of the control circuit 1510 for controlling the input/output operation of the FIFO memory 1500 in Fig. 15.
  • a feature of this arrangement as compared with Fig. 12 is the presence of two read pointers (RP H and RP L ), which allows the handling of data in the FIFO memory in both half-word length and full-word length.
  • Fig. 17 shows as an example the arrangement of the control circuit for setting the head of data always at the high-order bit in handling data in the FIFO memory 1500 in half-word length.
  • the flip-flop 1700 is reset by the signal 17001 at a time point when the FIFO memory 1500 and control circuit 1510 are reset (state 0). Thereafter, the flip-flop 1700 selects the latch 1702 for the output destination.
  • the flip-flop 1700 is set (state 1) by the signal 17002.
  • the flip-flop selects the latch 1701 for the output destination.
  • the flip-flop 1700 is reset (state 0) by the signal 17002.
  • Fig. 18 shows in detail part of the flip-flop shown in Fig. 17, and Fig. 19 shows its operation on a timing chart.
  • Fig. 20 shows an embodiment of the code collation means 802, code arrangement information memory means 803 and arrangement means 804 shown in Figs. 8 and 9.
  • Signal lines d, e, f, g, h, i and j correspond to the signals referred to by the same symbols in Fig. 9, and their timing relationship is shown in Fig. 10.
  • the code collation means 802 is formed of an AND-type dynamic PLA, while the code arrangement information memory means 803 is formed of an OR-type dynamic PLA.
  • the arrangement means 804 is made of n-channel MOS transistors as shown in the figure.
  • the most noticeable feature of the arrangement is that instead of generating signals to be input to the microprogram memory/control unit 202 and decoder unit 203, i.e., information j to be stored in the memory 303, by decoding an instruction word (signal line d) to make a new binary code (identical to information j) different completely from the instruction word, information j is created by using part of the binary code expressing the instruction word or completely arranging again the code.
  • Another feature is that for the arrangement of the binary code of an instruction word, arrangement information is defined so that instruction words having the completely same procedure of the arrangement format will fall in the same arrangement even if their codes are completely different.
  • This embodiment realizes the function of the conventional instruction decoder for generating the microprogram address to be inputted to the microprogram memory/control unit from the instruction word using the hardware structure about 1/5 - 1/10 in scale as compared with the conventional decoder.
  • Fig. 21 shows another embodiment of the arrangement means 804, which differs from the embodiment of Fig. 20 in that information j can be specified arbitrarily in accordance with the output of the OR array of the PLA (the code arrangement information memory means 803).
  • the embodiment of Fig. 20 provides information j by arranging part or whole of the instruction code, whereas the new embodiment can produce a code as information j independent of the instruction code. Namely, information j having an arbitrary code pattern can be obtained for any binary code expressing an instruction word merely by changing the contents of the code arrangement information memory means 803.
  • Fig. 22 shows an embodiment of the code collation means 802 in Fig. 8, which is constructed using memory cells capable of access for reading and writing so that its contents can be translated dynamically.
  • Information for collating instruction codes is defined word by word sequentially in the memory cells 2210 through the bus 22001. After all bits of the memory cells 2210 have been defined, an instruction word intended for collation is put onto the data lines 22101 through the bus d.
  • the memory cells 2210 compare the defined data with data on the data lines 22101, and drives signal lines with inconsistent results to the low level. If consistent results are reached for all bits of a word, the signal lines 22102 retain the high level. At least one of the signal lines 22102 for coincident detection is used to drive the code arrangement information memory means 803 in the next stage.
  • Fig. 23 shows in detail an example of the memory cell 2210 in Fig. 22.
  • the memory cell 2210 is written data by being controlled through the signal line W.
  • the data lines D and lines are driven to the high level during the precharging cycle.
  • the signal line C is driven to the low level, and therefore the precharging operation is desirable for the code arrangement information memory means 803.
  • Fig. 24 shows part of the processor shown in Fig. 1 pertinent to the multiple register system.
  • the bus interface unit 205 in Fig. 1 is split into a bus interface unit 2101 and another bus interface unit 2102, while the instruction word translation unit 201, microprogram memory/control unit 202 and decoder unit 203 are shown as a unitary control unit 2000.
  • the bus input/output units 2081, 2082 and 2083 in Fig. 1 are shown as a bus input/output unit 2103.
  • the bus interface unit 2101 includes an address generator 2104, task number specifier 2105, task number memory 2106, base address specifier 2107 and task boundary detection circuit 2108, all controlled by the control unit 2000.
  • the bus interface unit 2102, address generator 2104, task number memory 2106 and base address specifier 2107 are connected to the D-bus 1a and A-bus 1b, while the main memory 102, operation unit 204 and task number specifier 2105 are connected to the D-bus 1a.
  • the control unit 2000 provides a control signal 1c to the operation unit 204, the control signal 1d to the bus interface unit 2102, a control signal 1e and register specifying information 1g included in the signal If from the bus interface unit to the address generator 2104, a control signal 1h to the task number specifier 2105, a control signal 1i to the taks number memory 2106, and a control signal j to the base address specifier 2107.
  • the task number specifier 2105 is designed to receive the event occurrence signal 1k in response to an interrupt request from a peripheral unit (not shown) and the event occurrence signal 1l at the time of procedure call/return.
  • the operation unit 204 is connected with the bus interface unit 2102 through a data transfer bus 1m.
  • the signal 1n carries the task number obtained in the task number specifier 2105, and the signal 1p carries physical address information issued by the address generator 2104 to the main memory 102.
  • An instruction word read out of the main memory outside of the processor 20 is fed over the D-bus 1a to the bus interface unit 2102.
  • the instruction word is also transferred in some cases to the control unit 2000 as signal 1f.
  • the control unit 2000 decodes the input instruction word and, if it is an instruction using a register, sends register specifying information which is set in the register specifying field in the instruction word to the address generator 2104 and the control signal 1c to the operation unit 204.
  • the task number specifier 2105 responds to the event occurrence signal 1k or 1l, which arise in response to an external interrupt request or the execution of an internal subroutine interrupt, to select a task corresponding to the event and at the same time issues a task number for identifying a register set corresponding to the task to the specified address generator 2104 in accordance with the procedure described later.
  • the address generator 2104 generates a physical address corresponding to the main memory 102 from the task number 1n and register specifying information 1g in accordance with the procedure described later, and sends it to the main memory 102.
  • the main memory 102 reads out the contents of the location corresponding to the given physical address, and sents it over the D-bus 1a.
  • the operation unit 204 takes data on the D-bus 1a in response to the control signal 1c, and implements the specified operation. After the operation, the resultant data is fed over the D-bus 1a and written into the memory specified by the instruction.
  • the task number specifier 2105 issues a task change request by the signal 1q, and the control unit 2000 operates to save various data such as the task number pertinent to the task in execution through the D-bus 1a to the stack in the main memory.
  • the control unit 2000 further implements the control so as to modify the environment to meet the task of the higher priority event.
  • the task number specifier 2105 issues a task number which identifies a register set corresponding to the new task. In this way, each time an event occurrence signal 1k or 1l has been applied its priority is compared with that of the current task and the task is replaced when the latter event is higher in priority.
  • the task number 1n has exceeded the number of tasks 1r preset in the task number memory 2106, it is detected by the task boundary detection circuit 2108 and indicated to the control unit by the signal 1s so that the control unit performs the predetermined process.
  • Fig. 25 shows the detailed arrangement of the task number specifier 2105, which consists of a first flip-flop group 2111 and second flip-flop group 2112 for timing the event occurrence signals 1k, a priority arbitration circuit 2113 for testing the priority among the events, a task number register 2114 for holding the task number, an adder/subtracter 2115 for incrementing or decrementing by one the contents of the task number register 2114 depending on the value 1h-3 which is part of the control signal 1h, and a task number latch 2116 for temporarily holding the task number.
  • the event occurrence signals 1k entered asynchronously with the basic clocks ⁇ 1 and ⁇ 2 in the processor 20 are sampled by the first flip-flop group 2111 and synchronized with the basic clock ⁇ 2 by the second flip-flop group 2112. Synchronized event signals are delivered to the priority arbitration circuit 2113, and an event signal which is determined to be higher in priority than the current task causes the issuance of the event occurrence detect signal 1q to the control unit 2000.
  • the control unit 2000 issues a control signal 1h to replace the task number which has been effective until the event has occurred with the new task number in the task number register 2114.
  • the control unit 2000 issues a signal 1l so as to replace the task immediately.
  • the task number register 2114 is connected to the D-bus 1a with the intention of allowing the instruction to access to the task number register 2114 for reading or revising the contents.
  • the task number indicated by the task number register 2114 immediately before the execution of the instruction i.e., the task number before revision
  • the task number indicated by the task number register 2114 immediately before the execution of the instruction i.e., the task number before revision
  • the stack pointer in the register set specified by the revised task number after the execution of the instruction In order to retrieve the former task number which has been saved, there is provided an instruction which reads out the contents of the stack indicated by the stack pointer in the register set specified by the current task number and sets it in the task number register 2114.
  • Fig. 26 shows in detail the arrangement of the address generator 2104.
  • the address generator 2104 is to produce physical address information for the main memory 2107 basing on the task number 1n and register specifying information 1g, and it consists of a global base register 2121, a local base register 2122, a comparator 2123, an area determination circuit 2124 and a RAM physical address generating circuit 2125.
  • the global base register 2121 and local base register 2122 can be accessed by the instruction for revising the contents.
  • the comparator 2123 operates to compare the contents 3a of the global base register 2121 and the register number included in the register designating information 1g and also compare the contents 3b of the local base register 2122 with the register number in 1g.
  • the results of comparison are delivered as signals G and L, respectively, to the area determination circuit 2124.
  • the area determination circuit 2124 determines one of the global area, local common area and local bank area in accordance with the signals G and L, and provides information as a control signal 3c necessary for generating the physical address of the main memory 102.
  • the RAM physical address generating circuit 2125 produces the physical address of the on-chip RAM from the task number 1n and register number included in the register specifying information lg in accordance with the control signals 3c and le.
  • the main memory 102 has a capacity of 1152 bytes, 64 bytes for each task. Accordingly, sixteen 32-bit registers can be provided for each task.
  • the registers for task #2n+1 are grouped into a global area, local common area and local bank area, as shown in Fig. 27(a). These areas include registers as follows.
  • the registers for task #2n+2 are grouped into the three areas as in case (1). These areas include registers as follows.
  • Fig. 28 These access operations are shown in Fig. 28.
  • a corresponding register for task #0 is accessed.
  • a corresponding register for the previous task is accessed.
  • a register in the local bank area is specified, a corresponding register for the current task is accessed.
  • Fig. 29 shows in detail the arrangement of the comparator 2123.
  • the comparator 2123 consists of a comparison circuit 2131 capable of identifying a global area and a comparison circuit 2132 capable of identifying a local bank area.
  • the comparison circuit 2131 compares the register number A included in the register specifying information 1g with the global base value B which is the output 3a of the global base register 2121, and produces an output signal G at logical level "1" if A is smaller than B, or otherwise produces a "0" output.
  • the comparison circuit 2132 consists of a comparison circuit 2133 capable of identifying a local bank area when switching has been made from an odd-numbered task to an even-numbered task, and a comparison circuit capable of identifying a local bank area when switching has been made from an even-numbered task to an odd-numbered task, both circuits having their outputs 6a and 6b at logical level "1" when the register number A belongs to the local bank area.
  • a multiplexer 2136 selects one of the outputs 6a and 6b to produce a signal L in accordance with the output 6 of the flip-flop 2135 which is controlled by the signal 1e from the control unit 2000.
  • Fig. 30 shows the process carried out by the area determination circuit 2124.
  • the relevance of the global area is tested basing on the value of the signal G.
  • Fig. 31 shows the procedure of physical address generation by the main memory address generating circuit 2125.
  • the main memory 102 has a capacity of 1152 bytes and therefore the physical address ranges from 0 to 1151.
  • the following describes the operation of the case of 16 tasks provided in the main memory 102.
  • the low-order four bits of the task number 1n provided by the task number specifier 2105 are effective to indicate the task number.
  • the physical address is generated in accordance with the following procedure.
  • the address generator receives a task number (t3t2t1t0) 2 which is based on the register number (r3r2r1r0) 2 included in the register specifying information 1g and the signal 3c provided by the area determination circuit 2124.
  • T1 shifted to the left with a "0" being entered to the lowest-order bit.
  • the register number is shifted to the left with a "0" being entered to the lowest-order bit.
  • Offset value (080) 16 is added to the A1 to obtain the result A2.
  • the offset value at this time is determined uniquely from the total capacity of the main memory 102, and it takes the above-mentioned value for a 1152 byte main memory.
  • the main memory 102 is accessed with high-order nine bits "1 0 0 1 r3r2r1r0" of A2 being set to the high-order nine bits of the address. Namely, four bytes are accessed concurrently. This operation results from the assumption of 32-bit registers, and is confined to this embodiment.
  • Fig. 32 shows the relationship between the off-chip main memory 2142 and on-chip main memory 102 based on the contents of the main memory base register 2141 included in the base address specifier 2107.
  • the main memory base register 2142 can be accessed by the instruction for setting the contents arbitrarily.
  • an address space ranging from that address up to 1152 is assigned to the on-chip main memory 102. Accordingly, when the address of the memory specified by the bus interface unit 2102 is included in the above-mentioned address space, the processor 20 makes access to the main memory 102.
  • the main memory 102 in the processor 20 is arranged in arbitrary location of the off-chip main memory 2142 by merely changing the contents of the main memory base register 2141.
  • This embodiment is provided with an address detection means for distinguishing the register area in the main memory 102 and other area so that the area defined to be register sets for the task process is not accessed as a memory area.
  • Fig. 33 shows the arrangement of the task boundary detection circuit 2108.
  • the task number 1n is compared with the number of tasks lr which is set in the task number memory 2106, and if the task number 1n has exceeded the number of tasks lr, it is indicated by the signal ls to the interrupt vector generating circuit 2143 in the control unit 2000, which then executes a predetermined exceptional process.
  • the task number memory 2106 can be accessed by the instruction for revision, and the memory contents signifies the number of tasks as follows.
  • Fig. 34 shows an embodiment of the microprogram memory/control unit 202.
  • Part of the microprogram address to be set in the microprogram address register 2403 is selected by the selector 2402.
  • the selected signal 2402a is merged with the signal 2406e which is part of the output from the microinstruction register 2406, and the result is held in the microprogram address register 2403.
  • the output of the microprogram address register 2403 is delivered to the address decoder 2404 and, at the same time, incremented by the +1 adder 2408 and the resultant signal 2408a is fed to the selector 2402.
  • the address decoder 2404 decodes the microprogram address and sends the result to the microinstruction memory 2405.
  • the microinstruction memory 2405 reads out a specified microinstruction and sets it in the microinstruction register 2406.
  • the microinstruction register 2406 provides three major outputs including signal 2406a which is the signal for controlling the decoder unit 203 and operation unit 204, signal 2406b which is the signal for specifying a branch destination address when the microprogram makes branching, and signal 2406c which is the signal for controlling the next address of the microprogram.
  • a control circuit 2407 responds to the signal 2406c to produce a signal 2407a for controlling the selector 2402 and a signal 2407b for controlling the stack 2409 used for saving the microprogram address.
  • Fig. 35(a) shows an embodiment of the microprogram address register 2403, address decoder 2404, microinstruction memory 2405 and microinstruction register 2406 shown in Fig. 34.
  • Each bit of the microprogram address register 2403 is formed of a flip-flop 2503 as shown in Fig. 35(b), for example.
  • the address decoder 2404 is formed of an AND-type dynamic PLA, while the microinstruction memory 2405 is formed of an OR type dynamic PLA.
  • the microinstruction register 2406 is formed of a dynamic latch.
  • Fig. 36 shows the timing relationship of the signals together with the basic clocks ⁇ 1 and ⁇ 2 . As can be seen from Fig. 36, one clock period is needed to obtain the output of the microinstruction register 2406 after the output 2403a of the microprogram address register 2403 has settled.
  • Fig. 37 shows the timing relationship of the signals when the microprogram memory/control unit 202 is halted without suspending the basic clocks ⁇ 1 and ⁇ 2 .
  • Signal 24A is the signal for halting the microprogram memory/control unit 202, and the signal at high level causes the microprogram address register 2403 to stay unchanged and the microinstruction register 2406 to produce a low level output for all bits.
  • this special value (all low bits) of the microinstruction register to be a "no operation" command for the application system, the microprogram memory/control unit 202 can apparently be halted.
  • Fig. 38 shows the arrangement of the operation control decoder 2030 in the decoder unit 203.
  • the decoder 2030 consists of a decoder control latch 2800, a first register control decoder 2810, a second register control decoder 2820, an operation circuit control decoder 2840 and delay circuits 2830 and 2850.
  • the first register control decoder 2810 specifies the source register which contains data to be operated
  • the second register control decoder 2820 specifies the destination register in which the operation result is stored
  • the operation circuit control decoder 2840 specifies the type of operation (addition, subtraction, logical sum, logical product, exclusive logical sum).
  • the signal 2801 is delayed for one clock period by the delay circuit 2830. Because of different timing of use of the output signals 2841 and 2842 from the operation circuit control decoder 2840, the signal 2842 is delayed by the delay circuit 2850.
  • Fig. 39 shows an embodiment of the decoder control latch 2800, first register control decoder 2810, second register control decoder 2820 and delay circuit 2830 shown in Fig. 38.
  • the most noticeable feature of this embodiment is that the first and second register control decoders 2810 and 2820 are arranged by AND-type dynamic PLAs, whose output lines 2812 are precharged using p-channel MOS transistors, a specific level (high level in this embodiment) of the signals 2812 outputted during the precharging period is defined to be the unselected state for the input/output of the register, only signal lines 2812 which meet the PLA logic following the precharging period are discharged, and the register input/output lines 2813 are made the register selection stage.
  • Fig. 40 shows the timing relationship of the signals of the first register control decoder 2810 in relation with the basic clocks. It takes one clock period after the output 2801 of the decoder control unit 2800 has settled until the register contents are read out by the register read-out control signal 2811.
  • This embodiment can be realized by hardware as little as about one third of the static PLA structure. Only selected ones of the signal lines 2812 carry discharge currents, which reduces the power dissipation, and the circuit is operative in the register access timing comparable to the conventional static decoder. When logical sum for the output lines of the PLA is required, it can be achieved by the wired-OR configuration for the output lines.
  • Fig. 41 shows, as an example, the arrangement of the operation unit 204.
  • the unit 204 consists of a temporary register 3100 for holding data, a status register 3110 for holding the state of the operation result, an operation circuit 3120, a source latch 3130 for temporarily holding data to be operated, a shift circuit 3140 operative to shift one bit right or left for the operation result, a destination latch 3150 for temporarily holding the operation result, a read data register 3160 for temporarily holding data read on the bus 213 and a write data register 3170 for temporarily holding data sent out over the bus 213.
  • one of operation data is fed over the bus 31A into the source latch 3130.
  • the contents of the source latch 3130 and read data register 3160 are entered to the operation circuit 3120, which implements an operation specified on the signal line 2823.
  • the result of operation is held temporarily in the destination latch 3150, and then it is fed over the bus 31B to a register specified by the signal 2813.
  • Signals produced as a result of operation indicative of the sign of the result, the result of zero, the occurrence of carry (borrow), the occurrence of overflow are fed over the signal lines 31C into the status control circuit 3180, and then the states of the signals specified by the signal 2803 which is part of a microinstruction are stored in the status register 3110.
  • Figs. 42, 43 and 44 are schematic diagrams showing an example of the functional blocks shown in Fig. 41.
  • the buses 31A and 31B are precharged during a high period of the basic clock ⁇ 1 , and they transfer data in a high period of the basic clock ⁇ 2 .
  • Each bit of the temporary register 3100 is made up of a write gate 3101-0 connected to the bus 31B-0, a drive gate 3103-0, a feedback gate 3102-0, and a read gate 3104-0 connected to the bus 31A-0.
  • the temporary register is written by making the control signal 3200a high so that data on the write bus 31B-0 is conducted through the write gate 3101-0, and it is read out by making the control signal 3200b high so that the output of the drive gate 3103-0 is conducted through the read gate 3104-0 onto the read bus 31A-0.
  • the status control circuit 3180 is formed of a PLA which receives the microinstruction 2803 and status information 31C reflecting the operation result, and produces the set signal 3281 written in the status register and data 3282 to be written.
  • the status register 3110 is similar to the temporary register 3100, but has an additional input gate 3110-0 as shown for the lowest-order bit. It should be noted that the write operation of data 3282 through the gate 3110-0 takes place during the precharge period for the buses 31A and 31B in the operation unit 204.
  • the circuit implements the addition, logical sum, logical product and exclusive logical sum operations in accordance with the control signals on three control lines 3321.
  • the circuit shifts data by one bit right or left in accordance with the states of the signal lines 3341.
  • a high state of signal line 3341R causes a right shift, while a high state of signal line 3341L causes a left shift.
  • the read data register 3160 holds data on the bus 213 and transfers it to one input of the operation circuit 3120 or onto the bus 31A.
  • the write data register 3170 holds data to be sent over the bus 213, and it receives data on the bus 31B which carries the operation result.
  • Fig. 44 shows the arrangement of the casw ehere the bus 213 has 16 bits and the read data register 3160 and write data register 3170 have 32 bits each.
  • Control signals 236a, 236b, 236c and 236d for controlling the input/output to the bus 213 operate on the above two registers so that their high-order 16 bits and low-order 16 bits are controlled independently.
  • Fig. 45 shows an embodiment of the processor 20 incorporating a main memory 3500 capable of access for at least reading.
  • a level detect/memory circuit 3531 detects and memorizes the level at terminal 3530. The operation of the processor 20 will be described for the following two cases.
  • the contents of the memory address register 1 (shown by MAR1 in Fig. 45) are fed over the bus 212 through the buffer 3520 to the terminal 3521.
  • the multiplexer 2 (shown by MPX2 in the figure) 3550 selects the contents on the bus 212 and supplies a selected one to the main memory 3500.
  • the buffer 3510 selects data on the bus 213 received at the terminal 3511.
  • the buffer 3510 selects data on the bus 3501.
  • the buffer 3510 is controlled by the output 3561 of the decoder 3560 which discriminates whether the address carried by the bus 212 indicates the main memory 3500 in the processor 20.
  • the output 3512 of the buffer 3510 is selected by the multiplexer 1 (shown by MPX1 in the figure) 3540 and sent to the instruction memory means 301.
  • the contents of the instruction address register (IAR) are set in the memory address register 2 (MAR2) and transferred over the bus 3502 to the multiplexer 2 (MPX2) 3550.
  • the multiplexer 2 (MPX2) selects the contents of the bus 3502 and supplies a selected one to the main memory 3500.
  • the output of the main memory 3500 is fed over the bus 3501, selected by the multiplexer 1 (MPX1), and transferred to the instruction memory means 301.
  • the effective address which has been calculated by the operation unit 204 and held in the data address register (DAR) is transferred to the memory address register 1 (MAR1) and transferred over the bus 212 to the buffer 3520.
  • the contents of the buffer 3520 are fed through the terminal 3521 to the main memory outside of the processor 20.
  • Data to be read or written is transacted through the terminal 3511 and bus 213 between the operation unit 204 in the processor 20 and the main memory outside of the processor 20 or the main memory in connection with the bus 213 within the processor 20.
  • the level detect/memory circuit 3531 providing a high output 3522
  • instruction fetching takes place with the main memory 3500 within the processor 20 and data reading/writing takes place with a main memory other than 3500.
  • This concurrent operation for instruction fetching and data reading/writing is the feature of this embodiment, and it reduces the instruction processing time.
  • Fig. 46 shows an embodiment of the processor 20 which is operative in variable memory access cycles (instruction fetch cycle, data read cycle and data write cycle). The length of the memory access cycles is varied in accordance with the contents of the register 3600 which can be accessed for reading or writing by the instruction.
  • Fig. 47 shows, as an example, memory access cycles determined by the values of the register 3600.
  • Register contents "0" shown in Fig. 47 (a) achieves the fastest memory access.
  • the access cycle of the main memory used in combination with the processor 20 can be varied by setting the register using the instruction, whereby the system can be adapted to the variation of access cycle which results from the change in the main memory used, without adding extra control circuits outside of the processor 20.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Executing Machine-Instructions (AREA)

Claims (8)

  1. Datenverarbeitungssystem des Typs mit Mehrfachregistersatz-System, das einen Hauptspeicher (2142) zum Speichern von Anweisungen und Operanden enthält und so beschaffen ist, daß es als Antwort auf die Anweisungen eine Datenverarbeitung ausführt,
    wobei das System umfaßt:
    eine Tasknummerspezifizierungseinrichtung (2105) zum Spezifizieren einer Tasknummer (1n), die einen beliebigen von mehreren Registersätzen identifiziert;
    eine Taskanzahlspeichereinrichtung (2106) zum Speichern der Gesamtzahl der Tasks;
    einen Lese/Schreib-RAM-Speicher (102), der den gesamten Hauptspeicher (2142) oder einen Teil desselben bildet und eine Kapazität besitzt, die größer ist als eine Speicherkapazität, die zum Bilden der Registersätze in der von der Taskanzahlspeichereinrichtung (2106) spezifizierten Anzahl erforderlich ist; und
    eine Adreßerzeugungseinrichtung (2104), die mit dem Hauptspeicher verbunden ist so beschaffen ist, daß sie aus der in einem Anweisungswort enthaltenen Registerspezifizierungsinformation (lg) und auf der Grundlage der Tasknummer eine physikalische Adresse des Speichers erzeugt; wobei
    das System so arbeitet, daß es auf eine Speicherstelle zugreift, die durch eine von der Adreßerzeugungseinrichtung (2104) erzeugte physikalische Adresse angegeben wird, wenn die Anweisung eine Anweisung mit Zugriff auf ein Register ist,
    dadurch gekennzeichnet, daß
    auf den Speicher aufgrund einer Bestätigung zugegriffen wird, daß die von der Tasknummerspezifizierungseinrichtung (2105) spezifizierte Tasknummer eine Gesamtanzahl von Tasks, die in der Taskanzahlspeichereinrichtung (2106) gespeichert ist, nicht überschreitet,
    die Registersätze im Schreib/Lese-Speicher angeordnet sind,
    eine Einrichtung vorgesehen ist, um die erzeugte Anzahl von Registersätzen veränderlich zu machen, indem in die Taskzahlspeichereinrichtung geschrieben wird, und
    eine Einrichtung (2121, 2122) vorgesehen ist, um für jede Task die Anzahl der Register zum Speichern von Daten, die für die Task spezifisch ist, zu spezifizieren.
  2. Datenverarbeitungssystem nach Anspruch 1, dadurch gekennzeichnet, daß
       eine Einrichtung vorgesehen ist, um Register zum Speichern von Parametern zu definieren, die üblicherweise in Prozeduren verwendet werden.
  3. Datenverarbeitungssystem nach Anspruch 1, in dem die Taskanzahlspeichereinrichtung (2106) einen Speicher enthält, der von einem Anweisungswort adressiert werden kann, wobei in den Speicher durch Ausführen des Anweisungswortes geschrieben werden kann.
  4. Datenverarbeitungssystem nach Anspruch 1, in dem die Tasknummerspezifizierungseinrichtung (2105) ein Tasknummerspezifizierungsregister (2114) enthält, auf das von einem Anweisungswort zugegriffen werden kann und in das durch Ausführen der Anweisung geschrieben werden kann, wobei das System Taskprozesse implementiert, indem es die Inhalte des Tasknummerspezifizierungsregisters jedesmal dann, wenn eine Taskumschaltungsanforderung auftritt, mit einer konstanten Nummer vergleicht.
  5. Datenverarbeitungssystem nach Anspruch 1, das ferner eine Adressierungseinrichtung (2125) enthält, die eine willkürliche physikalische Adreßstelle des Hauptspeichers (2142) angeben kann, wobei das System auf einen im voraus bestimmten entsprechenden Abschnitt des Speichers zugreift, wenn auf einen kontinuierlichen Speicherbereich des Hauptspeichers (102) von einer ersten physikalischen Adresse bis zu einer zweiten physikalischen Adresse, die sich von der ersten physikalischen Adresse unterscheidet, die beide von der Adreßspezifizierungseinrichtung angegeben werden, zugegriffen wird.
  6. Datenverarbeitungssystem nach Anspruch 1, das ferner eine Erfassungseinrichtung (2108) enthält, die erfaßt, daß eine von der Tasknummerspezifizierungseinrichtung spezifizierte Tasknummer eine Gesamtzahl von Tasks, die von der in der Taskanzahlspeichereinrichtung (2106) gespeicherten Information angegeben wird, überschritten hat.
  7. Datenverarbeitungssystem nach Anspruch 1, in dem die Adreßerzeugungseinrichtung (2104) umfaßt:
    ein erstes beschreibbares Register (2121, 2122), das von einem Anweisungswort spezifiziert werden kann; und
    eine Identifizierungseinrichtung (2123, 2124), die eine Serie von Registern identifizieren kann, die von einer Registernummer bis zu einer weiteren Registernummer numeriert sind, die beide in einem Registersatz gesetzt sind, wobei das erste Register Inhalte besitzt, die eine der zwei Registernummern spezifizieren können, und wobei das System auf ein Register mit einer entsprechenden Registernummer in einem Registersatz zugreift, die von einer Tasknummer angegeben wird, die unabhängig von einer aktuellen Tasknummer bestimmt worden ist, wenn eine Anweisung während der Ausführung einer Task ein Register spezifiziert hat, das in der Serie von Registern enthalten ist.
  8. Datenverarbeitungssystem nach Anspruch 1, in dem die Adreßerzeugungseinrichtung (2104) umfaßt:
    ein erstes beschreibbares Register (2121, 2122), das von einem Anweisungswort spezifiziert werden kann; und
    eine Identifizierungseinrichtung (2123, 2124), die eine Serie von Registern identifizieren kann, die von einer Registernummer bis zu einer weiteren Registernummer numeriert sind, die beide in einem Registersatz gesetzt sind, wobei das erste Register Inhalte besitzt, die eine der zwei Registernummern spezifizieren können, und wobei das System auf ein Register mit einer entsprechenden Registernummer in einem Registersatz zugreift, die von einer Tasknummer angegeben wird, die einer aktuellen Tasknummer unmittelbar vorausgeht, wenn während der Ausführung einer Task, die wenigstens einem Taskwechsel folgt, von einer Anweisung auf ein Register zugegriffen worden ist, das in der Serie von Registern enthalten ist.
EP91120043A 1985-04-08 1986-04-08 Datenverarbeitungssystem Expired - Lifetime EP0476722B1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP60072646A JPH0658629B2 (ja) 1985-04-08 1985-04-08 データ処理装置
JP72646/85 1985-04-08
JP177542/85 1985-08-14
JP60177542A JPH0724025B2 (ja) 1985-08-14 1985-08-14 マルチレジスタセツト方式のマイクロコンピユ−タ
EP86104747A EP0199173B1 (de) 1985-04-08 1986-04-08 Datenverarbeitungssystem

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP86104747.0 Division 1986-04-08
EP86104747A Division EP0199173B1 (de) 1985-04-08 1986-04-08 Datenverarbeitungssystem

Publications (3)

Publication Number Publication Date
EP0476722A2 EP0476722A2 (de) 1992-03-25
EP0476722A3 EP0476722A3 (en) 1992-09-09
EP0476722B1 true EP0476722B1 (de) 1997-02-26

Family

ID=26413782

Family Applications (2)

Application Number Title Priority Date Filing Date
EP86104747A Expired - Lifetime EP0199173B1 (de) 1985-04-08 1986-04-08 Datenverarbeitungssystem
EP91120043A Expired - Lifetime EP0476722B1 (de) 1985-04-08 1986-04-08 Datenverarbeitungssystem

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP86104747A Expired - Lifetime EP0199173B1 (de) 1985-04-08 1986-04-08 Datenverarbeitungssystem

Country Status (4)

Country Link
US (1) US5455955A (de)
EP (2) EP0199173B1 (de)
KR (1) KR900003591B1 (de)
DE (2) DE3689595T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6349945A (ja) * 1986-08-20 1988-03-02 Nec Corp デ−タ処理装置のプロセス・ロ−ルイン方式
US5307464A (en) * 1989-12-07 1994-04-26 Hitachi, Ltd. Microprocessor and method for setting up its peripheral functions
JP3097981B2 (ja) * 1993-07-16 2000-10-10 株式会社日立製作所 データ処理装置
US5729723A (en) * 1992-11-16 1998-03-17 Hitachi, Ltd. Data processing unit
JP2725546B2 (ja) * 1992-12-07 1998-03-11 株式会社日立製作所 デ−タ処理装置
JP3339132B2 (ja) * 1993-09-14 2002-10-28 ソニー株式会社 中央処理装置
GB2289353B (en) * 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Data processing with multiple instruction sets
GB2307072B (en) * 1994-06-10 1998-05-13 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
IL110181A (en) * 1994-06-30 1998-02-08 Softchip Israel Ltd Install microprocessor and peripherals
US6496922B1 (en) 1994-10-31 2002-12-17 Sun Microsystems, Inc. Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation
US5740406A (en) * 1995-05-15 1998-04-14 Nvidia Corporation Method and apparatus for providing fifo buffer input to an input/output device used in a computer system
KR100618756B1 (ko) * 1996-01-24 2007-05-04 선 마이크로시스템즈 인코퍼레이티드 네트워크또는로컬메모리로부터수신된명령세트를실행하는프로세서및컴퓨터시스템
KR100584964B1 (ko) 1996-01-24 2006-05-29 선 마이크로시스템즈 인코퍼레이티드 스택 메모리 구조에서의 캐싱 장치
US5867681A (en) * 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
EP0862111B1 (de) * 1997-02-27 2010-07-21 International Business Machines Corporation Dynamische Übersetzung zwischen verschiedenen Befehlskodes durch Wiederzusammensetzung von Befehlselementen
US5925124A (en) * 1997-02-27 1999-07-20 International Business Machines Corporation Dynamic conversion between different instruction codes by recombination of instruction elements
JPH113225A (ja) * 1997-06-13 1999-01-06 Nec Corp 情報処理装置
US5958038A (en) * 1997-11-07 1999-09-28 S3 Incorporated Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation
US6708268B1 (en) * 1999-03-26 2004-03-16 Microchip Technology Incorporated Microcontroller instruction set
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
GB2367915B (en) 2000-10-09 2002-11-13 Siroyan Ltd Instruction sets for processors
US7707389B2 (en) 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1543371A (fr) * 1967-09-05 1968-10-25 Ibm France Dispositions relatives au bloc de travail d'un calculateur
US3736567A (en) * 1971-09-08 1973-05-29 Bunker Ramo Program sequence control
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
GB2002553A (en) * 1977-08-10 1979-02-21 Itek Corp High speed, real-time computer emulator
JPS5616248A (en) * 1979-07-17 1981-02-17 Matsushita Electric Ind Co Ltd Processing system for interruption
DE2937777C2 (de) * 1979-09-19 1982-04-08 Ibm Deutschland Gmbh, 7000 Stuttgart Steuereinrichtung in einer elektronischen Datenverarbeitungsanlage zur Programmunterbrechung und für die Durchführung erzwungener Operationen
US4354228A (en) * 1979-12-20 1982-10-12 International Business Machines Corporation Flexible processor on a single semiconductor substrate using a plurality of arrays
CA1126406A (en) * 1980-03-31 1982-06-22 Northern Telecom Limited Sequence control circuit for a computer
JPS5775335A (en) * 1980-10-27 1982-05-11 Hitachi Ltd Data processor
US4445170A (en) * 1981-03-19 1984-04-24 Zilog, Inc. Computer segmented memory management technique wherein two expandable memory portions are contained within a single segment
JPS58116571A (ja) * 1981-12-29 1983-07-11 富士通株式会社 マイクロコンピユ−タに於ける命令暗号化方式及びその実施に使用されるマイクロコンピユ−タ
US4594661A (en) * 1982-02-22 1986-06-10 International Business Machines Corp. Microword control system utilizing multiplexed programmable logic arrays
US4583193A (en) * 1982-02-22 1986-04-15 International Business Machines Corp. Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus
US4484268A (en) * 1982-02-22 1984-11-20 Thoma Nandor G Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays
US5043870A (en) * 1982-02-24 1991-08-27 At&T Bell Laboratories Computer with automatic mapping of memory contents into machine registers during program execution
DE3376893D1 (en) * 1982-10-18 1988-07-07 Nec Corp Information processing apparatus and its instruction control system
JPS59501684A (ja) * 1982-10-22 1984-10-04 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン 目的命令ストリ−ムへ殆んど実時間で插入するためのソ−スおよび目的命令ストリ−ムの外部における加速式命令写像
US4713750A (en) * 1983-03-31 1987-12-15 Fairchild Camera & Instrument Corporation Microprocessor with compact mapped programmable logic array
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
US4825363A (en) * 1984-12-05 1989-04-25 Honeywell Inc. Apparatus for modifying microinstructions of a microprogrammed processor

Also Published As

Publication number Publication date
EP0199173A3 (en) 1989-10-25
US5455955A (en) 1995-10-03
EP0476722A3 (en) 1992-09-09
DE3650602T2 (de) 1997-06-12
DE3650602D1 (de) 1997-04-03
EP0476722A2 (de) 1992-03-25
EP0199173B1 (de) 1994-02-02
EP0199173A2 (de) 1986-10-29
KR860008500A (ko) 1986-11-15
DE3689595D1 (de) 1994-03-17
DE3689595T2 (de) 1994-05-19
KR900003591B1 (ko) 1990-05-26

Similar Documents

Publication Publication Date Title
EP0476722B1 (de) Datenverarbeitungssystem
US5511173A (en) Programmable logic array and data processing unit using the same
JP3683230B2 (ja) データ処理装置、命令セット切換方法、データ処理アーキテクチャおよびデータ処理装置作動方法
US3983539A (en) Polymorphic programmable units employing plural levels of sub-instruction sets
US4558411A (en) Polymorphic programmable units employing plural levels of sub-instruction sets
US4774688A (en) Data processing system for determining min/max in a single operation cycle as a result of a single instruction
US3983541A (en) Polymorphic programmable units employing plural levels of phased sub-instruction sets
EP0405495B1 (de) Logikvorrichtung und Verfahren zur Verwaltung einer Befehlseinheit in einer Pipeline-Verarbeitungseinheit
US5249280A (en) Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory
US5682531A (en) Central processing unit
US6338134B1 (en) Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data
US5097407A (en) Artificial intelligence processor
US4388682A (en) Microprogrammable instruction translator
KR20000076310A (ko) 리스크 구조를 갖는 8 비트 마이크로콘트롤러
GB2024475A (en) Memory access controller
US6012138A (en) Dynamically variable length CPU pipeline for efficiently executing two instruction sets
US5034879A (en) Programmable data path width in a programmable unit having plural levels of subinstruction sets
US5301338A (en) System including central processing unit
US4975837A (en) Programmable unit having plural levels of subinstruction sets where a portion of the lower level is embedded in the code stream of the upper level of the subinstruction sets
US5832533A (en) Method and system for addressing registers in a data processing unit in an indexed addressing mode
KR20010007093A (ko) 마이크로 명령을 기초로 프로그램 가능한 명령을 실행하는하드웨어 장치
EP0177268B1 (de) Programmierbare Datenpfadbreite in einer programmierten Einheit mit mehreren Niveaus von Unterbefehlssätzen
KR100278136B1 (ko) 데이타처리장치 및 데이타처리방법
GB2069733A (en) Conditional instruction execution in a pipelined processor
US5649229A (en) Pipeline data processor with arithmetic/logic unit capable of performing different kinds of calculations in a pipeline stage

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AC Divisional application: reference to earlier application

Ref document number: 199173

Country of ref document: EP

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19920805

17Q First examination report despatched

Effective date: 19950908

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AC Divisional application: reference to earlier application

Ref document number: 199173

Country of ref document: EP

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REF Corresponds to:

Ref document number: 3650602

Country of ref document: DE

Date of ref document: 19970403

ET Fr: translation filed
ITF It: translation for a ep patent filed

Owner name: MODIANO & ASSOCIATI S.R.L.

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19990318

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19990325

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19990630

Year of fee payment: 14

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20000408

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20000408

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20001229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20010201

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050408