EP0445083B1 - Oscillateur de phase à tension augmentée pour l'entraînement d'un multiplicateur de tension - Google Patents

Oscillateur de phase à tension augmentée pour l'entraînement d'un multiplicateur de tension Download PDF

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Publication number
EP0445083B1
EP0445083B1 EP91830037A EP91830037A EP0445083B1 EP 0445083 B1 EP0445083 B1 EP 0445083B1 EP 91830037 A EP91830037 A EP 91830037A EP 91830037 A EP91830037 A EP 91830037A EP 0445083 B1 EP0445083 B1 EP 0445083B1
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EP
European Patent Office
Prior art keywords
voltage
phase
node
boosted
nand
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Expired - Lifetime
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EP91830037A
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German (de)
English (en)
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EP0445083A1 (fr
Inventor
Luigi Pascucci
Marco Olivo
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STMicroelectronics SRL
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SGS Thomson Microelectronics SRL
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/03—Logic gate active element oscillator

Definitions

  • the present invention relates to an entirely integrated CMOS high voltage generator particularly suited for EEPROM memory devices and more in particular the invention concerns a voltage-boosted phase oscillator for driving a voltage mulplier circuit.
  • a peculiar circuit called voltage multiplier or voltage booster is used, which permits to obtain a voltage in the order of several decades of volts and is capable of delivering a current in the order of several decades of micro-ampers (»A) starting from a supply voltage of e.g. 5V.
  • This type of circuit is amply described in literature and is commonly associated with an oscillator which produces two phase signals, opposite in phase to one another, which are needed for driving the electrical charge transfer through the various stages of the voltage multiplier, in an unique direction from a supply terminal to an output storage capacitor, across which the multiplied voltage is produced.
  • Each stage of the multiplier is basically constituted by a transfer diode and by a storage capacitor.
  • the oscillation of the driving oscillator may be controlled by an output voltage regulating network in order to keep the output voltage constant independently of the load and/or of variations of the supply voltage.
  • a ring oscillator which is implemented by simply connecting in cascade an odd number of inverters and by closing in a ring the chain of inverters, thus preventing the occurrence of a stable state of the ring.
  • the instability is further ensured by the large gain of the CMOS gates which are normally used as inverters.
  • the voltage multiplier utilizes single type, n-channel transistors, preferably of the so-called natural or depletion type which advantageously offer a threshold voltage close to 0V and an internal resistance under conduction which is decisively lower than that of the so-called enhancement type transistors.
  • the circuit which is conceptually similar to the basic circuit made with diodes, requires for its functioning two pairs of phase signals, namely: FBX and FBN (voltage-boosted phases) and FX and FN (normal voltage level phases).
  • the phases of the two pairs are out of phase by 180°.
  • the normal level phases commonly have an amplitude equal to the supply voltage VCC, while the voltage-boosted phases have an amplitude larger than VCC.
  • the limiting factor to ideality of operation of a voltage multiplier is represented by the inevitable presence of a threshold voltage of the transistors, which does not permit an ideal transfer of the charge from each stage to the successive stage and this becomes seriously penalizing when trying to obtain relatively high output voltage starting from a supply voltage (VCC) which is comparable, as order of magnitude, to the threshold voltage.
  • VCC supply voltage
  • the threshold voltage of MOS transistors suffer of the so-called "body effect" and the greater becomes the voltage, the greater becomes the threshold voltage, which tends to become equal to the amplitude of the phase signals provided by the driving oscillator. Therefore by increasing the number of the stages of the multiplier, a saturation condition is eventually reached which determines the maximum output voltage which can be practically obtained.
  • the availability of a pair of voltage-boosted phase signals permits to obviate to this phenomenon by increasing the gate voltage of the transistors which transfer the charges from each stage to the successive stage, e.g. of the transistor N2 of Fig. 1.
  • the large capacitors C1 and C2 which provide the electric charges to the system for boosting the voltage on the output node OUT are connected to the normal, "not-boosted", phases FX and FN generated by the driving oscillator, while to the voltage-boosted phases FBX and FBN are connected smaller capacitors CB1 and CB2 because the circuit nodes driven by these transistors do not draw current, in fact they are connected to the gates of the transistors N2 and N1, respectively, which represent nodes having a substantially infinite impedance.
  • the nodes of the multiplier circuit driven by the voltage-boosted phases will be at a comparably higher voltage than the corresponding nodes driven by the normal phases FX and FN.
  • the phases FX and FBX be rising in voltage
  • the complementary phases FN and FBN be dropping in voltage
  • the nodes 1 and 3 will be coupled respectively by the capacitors C1 and CB1 and therefore will rise in voltage, on the contrary the voltage of nodes 2 and 4 will drop.
  • the nodes 1 and 3 are not coupled among each other because the transistor N1 is off because the voltage of the node 4 is lower than the voltage of the node 3, being the node 4 driven by a dropping phase, and effectively the node 3 "sees" the infinite impedance of the gate of the transistor N2.
  • the node 3 may thus reach a voltage higher than the node 1 and the tranfer of charges from the node 1 to the node 2 may take place substantially without the loss of a threshold voltage until the voltage of the node 3 becomes greater than the voltage of the node 1 by at least the threshold voltage of the transistor N2 with the relative "body effect".
  • any,two complementary phase signals must essentially be always disoverlapped, i.e. they must never be simultaneously "high", because if such a condition would happen, a decrease of efficiency if the charge transfer process toward the output of the voltage multiplier, due to a back-flow of electrical charges caused by the simultaneous conduction of two adjacent stages of the circuit, would be observed.
  • a main aim of the present invention is to provide an oscillator having voltage-boosted phases for driving a voltage multiplier of the type described above, wherein the disoverlapping of the relative phases is positively ensured during every oscillation and under every operating condition of the oscillator.
  • an oscillator circuit which comprises two intermeshed ring oscillators, wherein each ring oscillator is formed by an odd number of inverting stages in the form of multi-input NAND gates connected in cascade through a closed loop and generates a normal, not boosted, phase signal and a voltage-boosted phase signal, derived from the normal phase signal, in phase among each other and in phase opposition in respect to a normal phase and a similarly derived voltage-boosted phase which are produced by the other of the two intermeshed ring oscillators.
  • the frequency of oscillation is established by a double RC network, common to both loops.
  • the synchronization of the respective oscillations of the two intermeshed ring oscillators is established by means of a plurality of flip-flops connected in cascade, wherein each flip-flop is formed by two NAND-type, logic gates, which, singularly, form as many inverting stages of the two intermeshed ring oscillators.
  • the oscillation and the arresting of the oscillation is controlled by means of an enable/disable logic signal which is fed to a first common input of a first pair of NAND gates, which constitute, respectively, a first inverting stage of the two intermeshed ring oscillators while to a second input of each of the two pair of NAND gates is respectively fed the phase signal produced by the relative ring oscillator.
  • the two NAND gates of said first pair constitute a first inverting stage of a relative bootstrap circuit for deriving a voltage-boosted phase signal from the normal phase signal produced by the respective ring oscillator.
  • FIG. 2 A functional diagram of the voltage-boosted phase oscillator circuit of the invention is shown in Fig. 2.
  • the circuit of a first ring oscillator which generates a normal phase FX is evidenced in the figure by the use of a thick line for indicating the respective connections among the various components of such a first ring oscillator.
  • the first oscillator is formed by employing a first pair of NAND gates E and E′, three SR flip-flops in cascade, each respectively formed by two cross-coupled NAND gates: respectively A-A′, B-B′, C-C′ and by two inverters D and D′.
  • each NAND gate represents an inverter if the other input of the gate is at a logic "1" condition.
  • the set condition of a flip-flop made with NAND gates is obtained viceversa by imposing a logic "0 ⁇ " state to the said other input.
  • the second ring oscillator is formed by the following "inverting stages": E′ ⁇ A′ ⁇ A ⁇ B ⁇ B′ ⁇ C′ ⁇ D ⁇ (E′).
  • the intrinsic frequency of oscillation of the two rings is established by means of a double RC network. Both the two identical RC networks are common to both rings.
  • the oscillation and the stopping of the oscillation of the two intermeshed ring oscillators is effected by feeding a logic signal to a common input node of the two NAND gates E and E′. Oscillation being enabled by applying a logic "1" signal to said common input node and the stopping of oscillation being determined when said logic signal assumes a logic "0 ⁇ " value.
  • the two ring oscillators oscillate in phase opposition to each other and the respective phase signals FX and FN are perfectly synchronized in phase opposition to each other and the presence in each of the ring oscillators of the flip-flops ensures the impossibility for one of the two phases to be at a logic high level simultaneously with the other phase.
  • a voltage-boosted phase is derived having an amplitude which is substantially double the amplitude of the normal phase which is generated by the ring oscillator and whose amplitude is substantially equal to the supply voltage (VCC).
  • the voltage-boosted phase FBX is obtained by means of the circuit formed by a first inverting stage represented by the NAND gate E, by a second inverting stages INV2, by the transistors Ns, Nd and Nb and by the capacitors Cb and Ca. The operation of this voltage boosting circuit is as follows.
  • nodes a) at a logic low level, b) at VCC, e) at a low logic level, c) at VCC less a threshold because of the presence of the transistor Nd and d) at a logic low level, and to apply a rising ramp (FX) to node a) and by suppose that the node b) "react” with a certain delay due to the delay introduced by the first "inverting stage” which is represented by the NAND gate E and that therefore the node b) remain for such a delay period to its current level equal to VCC, a "bootstrap" effect is obtained on node c) because of the capacitor Cb, and therefore the entire voltage present on the node a) may tranfer to the node d) without the loss of a threshold value relative to the transistor Ns.
  • FX rising ramp
  • the transistor Ns is well switched-on and the transistor Nb is cut-off because the node b) is still at VCC. If this delay step lasts for a sufficient period of time, it is possible to pre-charge completely the output capacitor Ca of the circuit to the VCC voltage, which represents a prime condition for the effectiveness of the circuit. At this point, the rising signal on node a) finally propagate to node b) which thence assumes the logic low level (ground potential), thus cutting-off the transistor Ns.
  • the node d) is therefore isolated, and as soon as the signal from node b) propagates to node e), the voltage, now rising on e), projects the voltage of the node d) toward a level which is markedly higher than VCC, ideally toward a value which is twice the VCC value. Naturally this ideality of operation will be missed if the capacitors have losses and if the node d) must deliver a non-negligeable current to the driven circuit.
  • the transistor Nd which could also be diode-connected, has instead its base driven by the voltage-boosted phase of the other ring (FBN). This permits to recharge the node c) not to a voltage equivalent to the supply voltage VCC less a threshold value, but to a full VCC voltage, thus improving the efficiency of the "bootstrapping" of the node c).
  • FIG. 3 A preferred embodiment of the circuit of the invention is depicted with greater details in Fig. 3.
  • the circuit of Fig. 3 is functionally equivalent to the circuit of Fig. 2.
  • the two NAND gates E and E′ are depicted in a detailed manner, each having a respective virtual ground terminal which is driven by a signal SWGNDX and SWGNDN, respectively, derived from the other ring oscillator.
  • SWGNDX and SWGNDN respectively
  • a substantial delay in the propagation time of the signal through the same NAND gate is achieved so as to better ensure a complete re-charging of the respective capacitors Ca and C′a, as previously described.
  • the disoverlap condition of the boosted phases is further ensured, because the "bootstrapping" of the phase FBX cannot take place until the phase FBN has reached ground potential, and viceversa.
  • the node a rises in voltage and simultaneously the node c) rises too because of the coupling provided by the bootstrap capacitor Cb and of the isolation provided by the transistor Nb, which is deeply cut-off being the node b) high.
  • the node c) has been well precharged to VCC by means of the transistor Nd, whose gate had been previously driven by the boosted phase FBN, i.e. by a signal which easily reaches a level almost twice the value of the supply voltage VCC.
  • the phases FN and FBN have decayed, i.e. have dropped in voltage to a ground potential, thus provoking the dropping of the node e′).
  • the NAND gate E having now its ground terminal to 0, may finally perform its logic function of inverting the input signal, and therefore the output node b) goes to OV.
  • the node c) is therefore pulled to ground by the transistor Nb, which is now conducting, thus cutting-off the transistor Ns and isolating the node d).
  • the signal once the delay introduced by the second inverter INV2 has elapsed, propagates also toward the node e), which, by rising to VCC, couples the node d) through the capacitor Ca, and the phase FBX rises toward a level which is close to twice the value of the supply voltage VCC.
  • the “duration" of the "high" semi-period of the phases FX and FBX is determined by the succession of the two SR flip-flops formed by the NAND gates A-A′ and B-B′, and connected among each other by interposing between the outputs of the first flip-flop (A-A′) and the inputs of the second flip-flop (B-B′) two identical RC networks, the time constant of which, summed together, determines the permanence at the logic value "1" of the phases FX and FBX, and therefore also the permanence to the logic level "0 ⁇ " of the dual phases FN and FBN.
  • phase FN cannot rise again until the node b) performs the setting of the flip-flop A-A′, which propagates to the third flip-flop C-C′ thus activating the rise of the phase FN and the fall of the phase FX.
  • the outputs of an SR flip-flop implemented with NAND gates always encounter during a commutation the condition of both being at a logic state "1", as a consequence the phase signals FX and FN will never simultaneously be at a logic "1", thus ensuring the required "disoverlapping" for a correct operation of the voltage multiplier.
  • the node f When the node f) goes to a logic "1", it activates through the transistor Ne the discharging to ground potential of the phase FBX, but before that, also the phase FX drops to ground potential, the signal from the node f) must still propagate through the second gate (B) of the second flip-flop and then across another gate (C) of the third flip-flop before, having been inverted by the inverter D′, finally reaches the FX phase rail.
  • Everything which has been said in relation to FX and FBX is similarly true also for the phases FN and FBN when, in a dual mode, the following half-period of operation is considered, i.e. when the discharge of FBX and FX permits the rise of FN and the initiation of the pre-charge cicle of the capacitor Ca′ which leads to the generation of the voltage-boosted phase FBN, thus achieving the objective of synchronizing both pair of phases.
  • the circuit is preferably made with depletion type n-channel transistors, even though in a less efficient way the circuit could also be made with common enhancement type transistors.
  • transistors Ne and Ne′ used for discharging the boosted phases to ground are preferably of the enhancement type which hold more securely in a cut-off condition.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Dc-Dc Converters (AREA)
  • Logic Circuits (AREA)

Claims (4)

  1. Oscillateur à sorties complémentaires à tension surélevée pour piloter un multiplieur de tension réalisé avec des dispositifs à effet de champ et utilisant une paire de signaux complémentaires non en recouvrement normaux (FX, FN) et une paire de signaux complémentaires non en recouvrement surélevés en tension (FBX, FBN), caractérisé en ce qu'il comprend :
       deux oscillateurs en anneau entremêlés dont chacun est constitué d'un nombre impair d'étages inverseurs sous forme de portes NON ET à plusieurs entrées (E, A, A′, B′, B, C, D′ et E′, A′, A, B, B′, C′, D), reliées en cascade selon une boucle fermée, chacun produisant un signal normal non-surélevé (FX, FN) et un signal surélevé en tension (FBX, FBN) en coïncidence de phase l'un avec l'autre et en opposition de phase avec le signal normal (FN, FX) et le signal surélevé en tension (FBN, FBX) produit par l'autre des deux oscillateurs en anneau entremêlés, et deux réseaux RC identiques communs aux deux oscillateurs en anneau pour déterminer la fréquence d'oscillation ;
       des paires desdites portes NON ET (E-E′, A-A′, B-B′, C-C′) appartenant à l'un et à l'autre oscillateur en anneau, respectivement, formant une pluralité de bascules, connectées en cascade, une première paire de portes NON ET (NAND E, NAND E′) constituant un premier étage inverseur de l'un et de l'autre des deux oscillateurs en anneau entremêlés, ayant une première entrée pour recevoir un signal de commande et une seconde entrée pour recevoir le signal normal (FX, FN) produit par l'oscillateur en anneau respectif.
  2. Oscillateur selon la revendication 1, comprenant en outre deux circuits surélévateurs pour fournir lesdits signaux (FBX, FBN) à tension surélevée à partir des signaux normaux (FX, FN) produits par les oscillateurs en anneau respectifs, chaque circuit surélévateur comprenant un premier étage inverseur constitué d'une première porte NON ET (NAND E, NAND E′) des oscillateurs connectée entre un noeud d'entrée (a, a′) du circuit surélévateur sur lequel le signal normal (FX, FN) est présent ; un premier transistor de transfert (Ns, Ns′) fonctionnellement connecté entre le noeud d'entrée (a, a′) et un noeud de sortie (d, d′) du circuit sur lequel le signal (FBX, FBN) surélevé en tension est produit et ayant une grille connectée à un premier noeud intermédiaire (c, c′) qui est maintenu à une tension sensiblement égale à la tension d'alimentation (Vcc) du circuit au moyen d'un second transistor (Nd, Nd′) qui est fonctionnellement connecté entre le premier noeud intermédiaire (c, c′) et un rail de tension d'alimentation (Vcc), le premier noeud intermédiaire (c, c′) étant couplé, par un troisième transistor (Nb, Nb′) dont la base est connectée au noeud d'entrée (a, a′), à un deuxième noeud intermédiaire (b, b′) qui coïncide avec le noeud de sortie du premier étage inverseur (NON ET E, NON ET E′) ; un premier condensateur surélévateur (Cb, Cb′) connecté entre le noeud d'entrée (a, a′) et le premier noeud intermédiaire (c, c′) ; un deuxième condensateur de sortie (Ca, Ca′) connecté entre le noeud de sortie (d, d′) et un troisième noeud intermédiaire (e, e′) du circuit ; et un second inverseur (INV2, INV2′) connecté entre le deuxième noeud intermédiaire (b, b′) et le troisième noeud intermédiaire (e, e′) du circuit ;
       le second transistor du circuit surélévateur du premier oscillateur en anneau (Nd, Nd′) étant commandé par le signal (FBN, FBX) surélevé en tension produit par le circuit surélévateur de l'autre oscillateur en anneau.
  3. Oscillateur selon la revendication 2, dans lequel le troisième noeud intermédiaire (e, e′) du circuit surélévateur du premier oscillateur en anneau est connecté à un noeud de potentiel commun bas de la porte NON ET (NAND E′, NAND E) qui constitue un premier inverseur de l'autre des deux oscillateurs en anneau entremêlés pour assurer un écart de recouvrement entre les signaux (FBX, FBN) surélevés en tension produits.
  4. Oscillateur selon la revendication 1, dans lequel les signaux surélevés en tension (FBX, FBN) atteignent, pendant une première transition haut-bas, le potentiel de la masse avant les signaux normaux respectifs (FX, FN) dont ils sont dérivés, en étant déchargés vers la masse par un transistor (Ne, Ne′) qui est piloté par la tension présente sur un noeud intermédiaire du circuit oscillateur en anneau respectif sur lequel la transition est anticipée dans le temps par rapport à la transition d'un noeud de sortie du signal normal (FX, FN) produit par l'oscillateur en anneau respectif.
EP91830037A 1990-02-16 1991-02-07 Oscillateur de phase à tension augmentée pour l'entraînement d'un multiplicateur de tension Expired - Lifetime EP0445083B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT08360490A IT1246238B (it) 1990-02-16 1990-02-16 Oscillatore a fasi survoltate per il pilotaggio di un moltiplicatore di tensione
IT8360490 1990-02-16

Publications (2)

Publication Number Publication Date
EP0445083A1 EP0445083A1 (fr) 1991-09-04
EP0445083B1 true EP0445083B1 (fr) 1995-05-10

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EP91830037A Expired - Lifetime EP0445083B1 (fr) 1990-02-16 1991-02-07 Oscillateur de phase à tension augmentée pour l'entraînement d'un multiplicateur de tension

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US (1) US5097226A (fr)
EP (1) EP0445083B1 (fr)
JP (1) JPH06224702A (fr)
DE (1) DE69109521T2 (fr)
IT (1) IT1246238B (fr)

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FR2696598B1 (fr) * 1992-10-01 1994-11-04 Sgs Thomson Microelectronics Circuit élévateur de tension de type pompe de charge avec oscillateur bootstrapé.
TW271011B (fr) 1994-04-20 1996-02-21 Nippon Steel Corp
FR2735921B1 (fr) * 1995-06-21 1997-08-22 Sgs Thomson Microelectronics Circuit generateur de phases pour circuit d'alimentation negative du type pompe de charge
FR2742942B1 (fr) * 1995-12-26 1998-01-16 Sgs Thomson Microelectronics Generateur de creneaux de haute tension
JPH09331236A (ja) * 1996-06-12 1997-12-22 Mitsubishi Electric Corp 電圧制御発振器および電圧制御発振器を有する非接触ｉｃカード
DE69619112D1 (de) * 1996-10-11 2002-03-21 St Microelectronics Srl Verbesserte positive Ladungspumpe
EP0856935B1 (fr) * 1997-02-03 2003-11-05 Denso Corporation Circuit pompe de charge
FR2768573B1 (fr) * 1997-09-12 1999-11-26 Sgs Thomson Microelectronics Circuit generateur de tension du type pompe de charge, avec circuit de commande auto-oscillant
IT1302081B1 (it) * 1998-02-27 2000-07-20 Sgs Thomson Microelectronics Generatore di fasi di tensione con aumentata capacita' di pilotaggio
US6483886B1 (en) * 1999-01-08 2002-11-19 Altera Corporation Phase-locked loop circuitry for programmable logic devices
JP2002091604A (ja) 2000-09-19 2002-03-29 Mitsubishi Electric Corp クロック発生回路
US6686806B2 (en) 2000-12-14 2004-02-03 Tropian, Inc. Ring VCO based on RC timing
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US6943638B1 (en) * 2005-01-07 2005-09-13 Toppoly Optoelectronics Corp. Voltage controlled oscillator and electronic system using the same
JP4835009B2 (ja) * 2005-03-15 2011-12-14 ミツミ電機株式会社 発振回路及び発振制御方法
US20070143127A1 (en) * 2005-12-21 2007-06-21 Dodd Matthew L Virtual host
US7760558B2 (en) * 2008-01-15 2010-07-20 Spansion Llc Voltage booster by isolation and delayed sequential discharge
US7583133B2 (en) * 2008-01-25 2009-09-01 Texas Instruments Incorporated Self-oscillating regulated low-ripple charge pump and method

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JPH0624429B2 (ja) * 1985-04-26 1994-03-30 松下電器産業株式会社 レベル変換回路

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Publication number Publication date
IT9083604A0 (it) 1990-02-16
DE69109521D1 (de) 1995-06-14
JPH06224702A (ja) 1994-08-12
IT9083604A1 (it) 1991-08-16
US5097226A (en) 1992-03-17
EP0445083A1 (fr) 1991-09-04
IT1246238B (it) 1994-11-17
DE69109521T2 (de) 1996-03-14

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