EP0441692B1 - Verfahren zur Steuerung eines Matrixbildschirms, bestehend aus zwei unabhängigen Teilen und Einrichtung zu seiner Durchführung - Google Patents

Verfahren zur Steuerung eines Matrixbildschirms, bestehend aus zwei unabhängigen Teilen und Einrichtung zu seiner Durchführung Download PDF

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Publication number
EP0441692B1
EP0441692B1 EP91400260A EP91400260A EP0441692B1 EP 0441692 B1 EP0441692 B1 EP 0441692B1 EP 91400260 A EP91400260 A EP 91400260A EP 91400260 A EP91400260 A EP 91400260A EP 0441692 B1 EP0441692 B1 EP 0441692B1
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EP
European Patent Office
Prior art keywords
rows
screen
displayed
informations
memory
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EP91400260A
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English (en)
French (fr)
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EP0441692A1 (de
Inventor
Thierry Leroux
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3644—Control of matrices with row and column drivers using a passive matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only

Definitions

  • the present invention relates to a method for controlling a matrix screen comprising two independent parts and a device for its implementation. It applies in particular to all matrix screens ordered in two independent parts and in particular to video screens (for example, liquid crystal screens or fluorescent microtip screens).
  • a matrix screen of this type and in accordance with the prior art is described, as described in document EP-A-0 206 178.
  • Such a screen consists of a first part 10 and of a second part 12 independent but contiguous.
  • Each part 10, 12 of the screen comprises N control lines crossed with M addressing columns.
  • the lines of the first part 10 are successively selected simultaneously with the lines of the second part 12: the line 1 of the first part 10 with the line N + 1 of the second part 12, the line 2 with the line N + 2 and so on.
  • the selection of the lines is carried out by a first register 6 for the first part 10 and a second register 8 for the second part 12.
  • Signals DP for the register 6 and DS for the second register 8 provide the data concerning the line to be selected.
  • a line scanning signal HL controls the selection of the lines.
  • the registers 6 and 8 are respectively connected to means 9 and 11 amplifiers and impedance adapters for applying a determined potential to the selected lines.
  • the information to be displayed is contained coded in binary form in a first and a second registers 14, 16 which allow the addressing of the columns.
  • the first and second registers 14, 16 are connected to decoders 21, 23 which allow the application to the columns of the screen of the potentials corresponding to the information to be displayed on the pixels of the selected lines.
  • the information to be displayed during the next selection is recorded in a first and a second buffer registers 18, 20.
  • the first and second buffer registers 18, 20 are respectively connected to the first and second registers 14, 16 for transferring the information to be displayed.
  • the information to be displayed is delivered in series, line after line.
  • An intermediate memory 24 is therefore necessary: at a given instant, the information provided relates to only one line whereas two lines are displayed simultaneously (and also, it is necessary to fill the two buffer registers 18, 20).
  • This memory 24 therefore records the information to be displayed as it arrives and delivers to the buffer registers 18, 20 the information necessary for display. For this, it must be able to record the information to be displayed on all the lines of each part 10, 12 of the screen. It must therefore have a minimum capacity of 2N MK bits where: 2N is the number lines of the screen, M is the number of columns, and K is the number of bits necessary for coding the information to be displayed on a pixel.
  • the object of the present invention is to reduce the size of this intermediate memory and thus to reduce the cost of this type of screen.
  • the invention recommends the simultaneous selection of a line of a first type of parity of the first part and of a line of a second type of parity of the second part. Then, all the lines of the first type of the first part and all the lines of the second type of the second part having been selected, one simultaneously selects a line of the second type of parity of the first part and a line of the first type of parity of the second part so as to select all the lines.
  • this control method makes it possible to reduce the memory capacity to N / 2 MK bits, that is to say to reduce it by a factor of 4 compared to to that of the devices of the prior art.
  • the lines of a first type of parity are understood to mean the odd lines and the lines of a second type of parity to mean the even lines or the reverse.
  • the total number of lines of the screen is odd, to have two parts comprising an identical number N of lines, one uses for one of the parts a fictitious line which is not displayed but which is taken into account by screen electronics at the time level.
  • N the total number of lines of the screen
  • the memory is at least capable of simultaneously containing the information to be displayed on N / 2 lines of the screen.
  • the memory once records the information relating to the N lines of one of the types of parity of the screen, but at the same time as it performs these operations of writing information from the source, it transmits, during read operations, information to one or the other of the buffer registers of the device, so that at a given moment, the memory contains only N / 2.MK bits relating to the information of N / 2 lines .
  • the memory write and read control means is produced by a counter with two binary states having a counting input capable of receiving a pulse signal for synchronizing the delivery of the information to be displayed on a line and a second input capable of receiving a reset signal, this counter delivering on an output a pulse at each transition to its initial state and on another output connected to the memory a control signal L / E.
  • the means for generating write and read addresses is produced by a counter with N / 2 binary states having a counting input connected to the output of the counter with two binary states delivering pulses to each transition to its initial state and a second input capable of receiving a reset signal, this counter delivering on an output a pulse at each transition to its initial state and on another output connected to the memory an address signal AD .
  • the first and second means for controlling the switching of the first and second switching means are produced by a single circuit.
  • said single circuit is a counter with two binary states having a counting input connected to the output of the counter with N / 2 binary states delivering on an output a pulse at each change to its initial state and a second input capable of receiving a reset signal, this counter delivering on an output connected to the first and second switching means a control signal HB.
  • the device comprises: at least one register having a first input capable of receiving a clock signal and a second input capable of receiving a data signal.
  • the device comprises: a first register having N stages for the selection of the N lines of the first type of parity of the first and the second parts of the screen, and having a first input capable of receiving a clock signal and a second input capable of receiving a first data signal (DLI), a second register having N stages for the selection of the N lines of the second type of parity of the first and of the second parts of the screen and having a first input capable of receiving the clock signal and a second input capable of receiving a second data signal (DLP).
  • a first register having N stages for the selection of the N lines of the first type of parity of the first and the second parts of the screen, and having a first input capable of receiving a clock signal and a second input capable of receiving a second data signal (DLP).
  • DLP second data signal
  • Figures 2, 3, 4 and 6 schematically represent different variants of a circuit for the selection of a matrix screen having two parts 10, 12 independent but contiguous so as to ensure the continuity of the rows and columns.
  • the screen can be of the liquid crystal or fluorescent microtip type.
  • Each part 10, 12 comprises an even number N of lines; for the first part 10, these lines are numbered from 1 to N; for the second part 12, they are numbered from N + 1 to 2N.
  • the lines of the screen are therefore divided into odd lines and successive pairs.
  • Each part of the screen further comprises M columns. Screen pixels are formed at each crossing of rows and columns.
  • each line of a first type of parity of the first part 10 of the screen is selected simultaneously with a line of a second type of parity of the second part 12
  • each line of the second type of parity of the first part 10 is selected simultaneously with a line of the first type of parity of the second part 12.
  • FIG. 2 schematically represents a matrix screen comprising two contiguous parts 10, 12 provided with a line selection circuit according to the invention.
  • the selection circuit comprises two registers 26, 28 with N stages respectively supplied with data signals DLI, DLP relating to the odd and even lines to be selected and delivered by a control circuit not shown.
  • the register 26 is connected to means 34 of impedance amplifiers and adapters, themselves connected to the odd lines of the first part 10 and of the second part 12.
  • the register 28 is connected to means 38 amplifiers and impedance adapters, themselves connected to the even lines of the first part 10 and the second part 12.
  • the signals DLI, DLP, respectively applied to the registers 26, 28 indicate the lines to be selected during the first selection.
  • the lines to be selected at the start of the frame time are lines 1 and N + 2
  • the signals DLI and DLP correspond respectively to binary elements of which only the first binary element is non-zero for DLI and of which only the N / 2 + 1 binary element corresponding to the line N + 2 is non-zero for DLP.
  • the following selections are obtained by shifting the signals contained in the registers by applying clock pulses HL to inputs of registers 26 and 28.
  • the register 26 selects, one after the other, the odd lines of the first part 10.
  • the register 28 selects, one after the other, the even lines of the second part 12.
  • each odd line of the first part 10 is selected simultaneously with the selection of an even line of the second part 12 to which it is paired.
  • the numbered line 1 is selected simultaneously with the numbered line N + 2 and so on until the last odd numbered line N-1 of the first part 10 selected simultaneously with the numbered line 2N of the second part 12.
  • the register 28 selects, one after the other, the even lines of the first part 10.
  • the register 26 selects, one after the other, the odd lines of the second part 12.
  • each even line of the first part 10 is selected simultaneously when selecting an odd line from the second part to which it is paired.
  • the line numbered 2 is selected simultaneously with the line numbered N + 1 and so on until the last even line of the first part 10 numbered N selected simultaneously with the line numbered 2N-1 of the second part 12.
  • FIG. 3 schematically represents an alternative embodiment of a selection circuit. This variant allows the selection of the successive odd (respectively odd) lines of the first part 10 simultaneously with the successive even (odd) lines of the second part 12 with which they are paired.
  • the selection circuit further comprises four registers 26a, 28a, 30a, 32a with N / 2 stages connected as above to means 34a, 38a, 36a, 40a, amplifiers and impedance adapters.
  • the four registers are not interconnected but an identical clock signal HL and applied to an input of each of the registers controls the selection of a line.
  • data signals DLI1, DLP1, DLI2, DLP2 delivered by a control circuit not shown are respectively applied to the registers 26a, 28a, 30a, 32a.
  • these data signals introduce into the stages of the corresponding registers signals corresponding to binary elements of which only the stage corresponding to a line to be selected contains a non-zero binary element.
  • the signals contained in the registers undergo an offset at each clock pulse so as to select the lines to be.
  • registers 26a and 32a (containing a non-zero binary element) each select a line while registers 28a and 30a (containing only zero binary elements) do not select one; the situation is reversed during the next half-frame.
  • FIG. 4 schematically represents another variant of a selection circuit according to the invention.
  • the latter consists of two registers 42, 44 with N stages respectively connected to means 46, 48 amplifiers and impedance adapters.
  • the amplifier and impedance adapter means 46 is connected to the lines of the first part 10; the means 48 amplifier and impedance adapter is connected to the lines of the second part 12.
  • Data signals DL1 and DL2 delivered by a control circuit not shown, allow the selection of the lines of each part.
  • HL clock pulses supplied to inputs of registers 42 and 44 control the offsets of the information contained in registers 42 and 44 and therefore each new selection of a pair of lines.
  • This type of selection circuit requires clock pulses having an asymmetric timing diagram.
  • the stages of the registers supplied by the signals DL1 and DL2 allow, during a first half of the duration of a frame, the simultaneous selection of an odd line of the first part 10 with an even line of the second part 12 During the second half of the duration of a frame, they allow the simultaneous selection of a line pair of the first part 10 with an odd line of the second part 12. During each half-frame, the lines which should not be displayed are selected for too short a time to be effective.
  • FIG. 5A we see the timing diagram of the clock pulses HL for the selection of the odd lines of the first part 10 and the even lines of the second part used during the first half of a frame time.
  • Two different periods TL1 and TL2 are used for the selection of the odd and even lines of the first part 10 (and of the even and odd lines to which they are paired).
  • the duration of a period TL1 separating two clock pulses during the selection of an odd line of the first part 10 (or of an even line of the second part) is substantially equal to the usual duration of selection of a line.
  • the duration of a period TL2 separating two clock pulses during the selection of an even line of the first part (or of an odd line of the second part) is much less than the usual duration of selection d 'a line. In this way, the even lines of part 10 and the odd lines of part 12 are selected for too short a time for a display to be initiated on these lines.
  • FIG. 5B shows the chronogram of the clock pulses HL for the selection of the even lines of the first part 10 and of the paired odd lines of the second part 12 used during the second half of a frame time.
  • TL1 has a duration much less than the usual duration for selecting a line while TL2 has a duration substantially equal to the usual duration for selecting a line. In this way, the selection of the lines which should not support a display is carried out only for too short a time for a display to be initiated and their selection is of no consequence.
  • FIG. 6 schematically represents another alternative embodiment of a line selection circuit according to the invention.
  • This circuit uses only a register 50 to 2N stages connected to an amplifier means 52 and impedance adapter itself connected to the lines of the two parts 10, 12 of the screen.
  • the signals DL correspond to the set of signals DL1 and DL2 in FIG. 4.
  • the register 50 therefore contains two non-zero binary elements.
  • the clock pulses H delivered on an entry of the register present an asymmetric chronogram in a manner analogous to those of FIGS. 5A and 5B.
  • the pulses corresponding to the timing diagram of FIG. 5A are applied during a first half-frame and the pulses corresponding to the timing diagram of FIG. 5B are applied during the following half-frame.
  • FIG. 7 diagrammatically represents a circuit for addressing the columns of the screen according to the invention.
  • a source 22 delivers information coded in binary in an order relating to the successive lines of the screen. This source also delivers TL clock pulses in synchronism with the delivery of information. to be displayed on one line of the screen and TT frame pulses. Each piece of information to be displayed on a pixel of the screen is binary coded by a number of K bits.
  • the output of the source delivering the information to be displayed is connected to an input of a memory 62 of capacity at least capable of simultaneously containing the information to be displayed on N / 2 lines of the screen, to an input of a circuit 64 for addressing the columns of the first part of the screen and to an input of a circuit 66 for addressing the columns of the second part of the screen.
  • the circuit 64 comprises: a switching means 68 of the multiplexer type connected on the one hand to the source 22 and on the other hand to an output of the memory 62, a buffer register 70 connected to an output of the switching means 68, a register 72 connected to an output of the buffer register 70 and a decoder 21 connected by an input to the register 72 and at the output to the columns of the first part 10 of the screen.
  • the circuit 66 comprises, connected in a similar manner to the preceding circuit, a switching means 74 of the multiplexer type, a buffer register 76, a register 78 and a decoder 23 connected to the columns of the second part 12 of the screen.
  • the decoders 21 and 23 carry out an adaptation between the information in binary form contained in the registers 72 and 78 and the information to be applied to the columns.
  • the addressing circuit also comprises, a control means 80 for writing and reading from the memory and delivering on an output connected to an input of the memory 62 a L / E signal for writing or of reading.
  • This means 80 can be implemented by a counter with two binary states having first and second data inputs connected to the outputs of the source 22 delivering the clock pulses and the frame pulses, the latter performing a reset of the counter. 80.
  • the counter From the reset to zero, following the first clock pulse TL, the counter delivers for example a read signal in memory 62; following the second clock pulse the counter delivers a write signal to memory 62.
  • the counter operates in this way for successive clock pulses until the new reset to zero during a frame pulse.
  • the memory only records the information relating to lines of a single type of parity.
  • the memory records only the information to be displayed on the even lines of the screen.
  • the latter transmits the information relating to a selected even line by means of switches 68 or 74 depending on whether the selected line is included in part 10 or 12 of the screen.
  • this counter 80 delivers pulses IC1 on an output each time it regains its initial state, that is to say every two clock pulses.
  • the addressing circuit further comprises means 82 for generating write and read addresses connected by an output to an input of memory 62.
  • This means 82 can be implemented by a counter with N / 2 binary states having a counting input connected to an output of the counter 80 with two binary states for receiving the pulses IC1. It also has a second input connected to the output of the source 22 delivering the frame pulses which allow resetting of the counter 82.
  • the means 82 supplies the memory with a signal AD designating the addresses of the writes and readings in memory 62.
  • Each address is composed by a word of L bits with L integer and respecting the condition: (Log N / 2) / Log 2 ⁇ L ⁇ 1 + (Log N / 2) / Log 2
  • the signal AD designates a particular address common to the reading of a line from one part of the screen and the writing of a line from the other part of the screen.
  • the addresses of reading and writing of these lines correspond respectively to 1, 2, ... N / 2 coded in binary.
  • Each AD address being maintained during a read pulse and a write pulse, the information of the corresponding line stored in the memory at the address AD is read and then replaced by information corresponding to a line of the other part of the screen.
  • These two lines are lines of the same order in each part, i.e. 2 and N + 2 or N + 2 and 2, 4 and N + 4 or N + 4 and 4 ... N and 2N or 2N and N.
  • the counter with N / 2 binary states delivers an IC2 pulse on an output.
  • the addressing circuit finally comprises means for controlling the switches of the switching means 68, 74. These means are produced by a counter 84 with two binary states.
  • This counter 84 has a counting input connected to an output of the counter with N / 2 binary states for the reception of the pulses IC2. It also has a second input connected to the output of the source 22 delivering frame pulses which trigger its reset.
  • the counter 84 delivers a signal HB whose binary value determines whether the multiplexers 68 and 74 deliver to the buffer registers 70 and 76 the information coming directly from the source 22 and relating to the odd lines or coming from the memory 62 and relating to the even lines .
  • the multiplexer 68 delivers on its output the information coming from the source 22, while the multiplexer 74 delivers on its output the information coming from the memory 62.
  • the multiplexer 68 delivers on its outputs information from memory 62, while multiplexer 74 delivers information from source 22 at its output.
  • the selection by the circuit for selecting the lines to be displayed begins synchronously with the delivery by the source 22 of the information to be displayed on an odd line of the screen. This synchronism is obtained by virtue of the clock pulses TL and of frame TT which are transformed or not to form the clock pulses triggering the register or registers of the selection circuit.
  • the information to be displayed on the even lines of the screen is recorded in the memory 62.
  • the registers 72 and 78 record the information contained in the buffer registers 70 and 76 respectively. This information decoded by the decoders 21 and 23 is displayed on the selected lines of the first and second parts of the screen.
  • the buffer registers 70 and 76 then record the information to be displayed during the next selection.
  • This information comes either directly from the source 22 or from the memory 62 via the multiplexers 68 and 74 controlled by the signal HB. There is therefore constantly a time lag between the delivery of the information by the source 22 and its display. This offset is equal to half a frame time for the information to be displayed on an even line while it is only equal to the time for selecting a line for the information to be displayed on an odd line.
  • the first frame allows the initialization of counters, registers and filling the memory with the information to be displayed on half of the even lines of the next frame.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Controls And Circuits For Display Device (AREA)

Claims (10)

  1. Verfahren zur Steuerung eines Matrixbildschirms, gebildet durch einen ersten Teil (10) und einen zweiten Teil (12), jeder eine gerade Anzahl N Zeilen umfassend, wobei die Zeilen von jedem der Teile (10, 12) aufgeteilt sind in Zeilen eines ersten Paritätstyps und Zeilen eines zweiten Paritätstyps, aufeinanderfolgend,
    dadurch gekennzeichnet,
    daß es für jedes Teilbild darin besteht:
    A) nacheinander die aufeinanderfolgenden Zeilen des ersten Paritätstyps des ersten Teils (10) anzusteuern; nacheinander die aufeinanderfolgenden Zeilen des zweiten Paritätstyps des zweiten Teils (12) anzusteuern, wobei jede Zeile des ersten Typs des ersten Teils (10) simultan mit einer Zeile des zweiten Typs des zweiten Teils (12) angesteuert wird, mit der sie gepaart ist,
    B) dann nacheinander die aufeinanderfolgenden Zeilen des zweiten Paritätstyps des ersten Teils (10) anzusteuern, nacheinander die aufeinanderfolgenden Zeilen des ersten Paritätstyps des zweiten Teils (12) anzusteuern, wobei jede Zeile des zweiten Typs des ersten Teils (10) simultan mit einer Zeile des ersten Typs des zweiten Teils (12), mit der sie gepaart ist, angesteuert wird,
    C) für jede angesteuerte Zeile Informationen sichtbar zu machen, die sichtbar gemacht werden sollen.
  2. Verfahren nach Anspruch 1, wobei die sichtbar zu machenden Informationen von einer Quelle (22) mit einem regelmäßigen Rythmus geliefert werden und in einer die aufeinanderfolgenden Zeilen des Bildschirms betreffenden Reihenfolge, dadurch gekennzeichnet:
    D) daß man in dem Maße, wie die auf den Zeilen eines der Paritätstypen sichtbar zu machenden Informationen angeliefert werden, sie abspeichert in einem Speicher (62),
    E) daß, parallel zu jeder Ansteuerung einer Zeile des ersten Teils (10), gepaart mit einer Zeile des zweiten Teils (12), wobei jede Ansteuerung, die synchron mit der Anlieferung der auf einer Zeile des anderen Paritätstyps des Bildschirms sichtbar zu machenden Informationen durch die Quelle (22) beginnt,
    a) man in einem ersten Register (72), aus einem ersten Pufferregister (70), die auf der genannten, angesteuerten Zeile des ersten Teils (10) sichtbar zu machenden Informationen speichert,
    b) man in einem zweiten Register (78), aus einem zweiten Pufferregister (76), die auf der genannten, angesteuerten Zeile des zweiten Teils (12) sichtbar zu machenden Informationen speichert,
    c) man die durch die Quelle (22) gelieferten und auf der Zeile des genannten, anderen Paritätstyps der nachfolgenden Ansteuerung sichtbar zu machenden Informationen in dem Pufferspeicher speichert, der der besagten Zeile zugeordnet ist,
    d) man aus dem Speicher (62) die Informationen, die auf der Zeile mit der in D) definierten Parität der nachfolgenden Ansteuerung sichtbar zu machenden Informationen in den Pufferspeicher überträgt, der der besagten Zeile zugeordnet ist.
  3. Vorrichtung zur Anwendung des Verfahrens nach Anspruch 1, dadurch gekennzeichnet, daß sie umfaßt, zum Adressieren der Spalten eines Matrixbildschirms, gebildet durch einen ersten Teil (10) und einen zweiten Teil (12), jeder eine gerade Anzahl N Zeilen umfassend, wobei die Zeilen von jedem der Teile (10, 12) aufgeteilt sind in Zeilen eines ersten Paritätstyps und Zeilen eines zweiten Paritätstyps, aufeinanderfolgend,
    - eine Quelle (22), die geeignet ist, auf einem Ausgang sichtbar zu machende Informationen zu liefern, in einer die aufeinanderfolgenden Zeilen des Bildschirms betreffenden Reihenfolge, und Taktpulse (TL) zu liefern, synchron zu der Anlieferung der auf einer der Zeilen des Bildschirms sichtbar zu machenden Informationen, und Vertikal- bzw. Teilbildimpulse (TT),
    - einen Speicher (62), geeignet zum Speichern der auf den Zeilen eines der Paritätstypen des Bildschirms sichtbar zu machenden Informationen, verbunden mit dem Ausgang der Quelle,
    - eine erste und eine zweite Verteilereinrichtung (68, 74), einerseits verbunden mit dem Ausgang der Quelle und andererseits mit dem Ausgang des genannten Speichers (62),
    - eine Einrichtung (80) zum Steuern des Einschreibens oder Auslesens des Speichers, verbunden mit dem genannten Speicher (62) und mit der Quelle (22), um die Taktpulse (TL) zu erhalten und die Vertikal- bzw. Teilbildimpulse (TT) und so beschaffen, daß:
    * in dem Maße, wie die auf den Zeilen des Bildschirms sichtbar zu machenden Informationen angeliefert werden durch die Quelle (22), jede zweite Information gespeichert wird in einem Speicher (62), der somit nur die auf den Zeilen des ersten Paritätstyps des Bildschirms sichtbar zu machenden Informationen speichert,
    * bei jedem an den Speicher (62) gelieferten Lesebefehl dieser die Informationen überträgt, die eine Zeile des ersten Paritätstyps betreffen, angesteuert mittels der ersten oder der zweiten Verteilereinrichtung (68, 74), je nach dem, ob die angesteuerte Zeile im ersten oder zweiten Teil des Bildschirms enthalten ist,
    - eine Einrichtung (82) zum Erzeugen der Schreib- und Leseadressen, verbunden mit dem genannten Speicher,
    - einen ersten Pufferspeicher (70), verbunden mit einem Ausgang der ersten Verteilereinrichtung (68),
    - einen zweiten Pufferspeicher (76), verbunden mit einem Ausgang der zweiten Verteilereinrichtung (74),
    - eine Einrichtung zum Steuern der Verteilung der ersten Verteilereinrichtung, verbunden mit der ersten Verteilereinrichtung (68) und so beschaffen, daß sie feststellt, ob die Verteilereinrichtungen (68) dem Pufferspeicher (70) Informationen liefern, die direkt von der Quelle (22) kommen und die Zeilen des zweiten Paritätstyps betreffen, oder von dem Speicher (62) kommen und die Zeilen des ersten Paritätstyps betreffen,
    - eine Einrichtung zum Steuern der Verteilung der zweiten Verteilereinrichtung, verbunden mit der zweiten Verteilereinrichtung (74) und so beschaffen, daß sie feststellt, ob die Verteilereinrichtungen (74) dem Pufferspeicher (76) Informationen liefern, die direkt von der Quelle (22) kommen und die Zeilen des zweiten Paritätstyps betreffen, oder von dem Speicher (62) kommen und die Zeilen des ersten Paritätstyps betreffen,
    - ein erstes Register (72), mit dem Eingang verbunden mit einem Ausgang des ersten Pufferregisters (70) und imstande, Informationen zu liefern, die auf einer angesteuerten Zeile des ersten Teils (10) des Bildschirms sichtbar gemacht werden sollen,
    - ein zweites Register (78), mit dem Eingang verbunden mit einem Ausgang des zweiten Pufferregisters (76) und imstande, Informationen zu liefern, die auf einer angesteuerten Zeile des zweiten Teils (12) des Bildschirms sichtbar gemacht werden sollen.
  4. Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, daß der Speicher (62) wenigstens imstande ist, simultan die auf N/2 Zeilen des Bildschirms sichtbar zu machenden Informationen zu speichern.
  5. Vorrichtung nach Anspruch 4, dadurch gekennzeichnet, daß die Einrichtung (80) zum Steuern des Einschreibens oder Auslesens des Speichers (62) gebildet wird durch einen Zähler mit zwei Binärzuständen, der einen Zähleingang aufweist für ein Liefersynchronisierungs-Pulssignal (TL) der auf einer Zeile sichtbar zu machenden Informationen, und einen zweiten Eingang für ein Rückstellungssignal (TT), wobei dieser Zähler bei jedem Übergang in seinen Initialzustand auf einem Ausgang einen Impuls liefert und auf einem anderen Ausgang ein Steuersignal L/E.
  6. Vorrichtung nach Anspruch 5, dadurch gekennzeichnet, daß die Einrichtung (82) zum Erzeugen der Schreib- und Leseadressen gebildet wird durch einen Zähler mit N/2 Binärzuständen, einen Zähleingang aufweisend, verbunden mit dem Ausgang des Zählers mit zwei Binärzuständen, der bei jedem Übergang in seinen Initialzustand Impulse liefert, und einen zweiten Eingang zum Empfangen eines Rückstellungssignals (TT), wobei dieser Zähler an einem Ausgang einen Impuls liefert bei jedem Übergang in seinen Initialzustand und auf einem anderen Augang, verbunden mit dem Speicher, ein Adressensignal AD.
  7. Vorrichtung nach Anspruch 6, dadurch gekennzeichnet, daß die ersten und zweiten Einrichtungen zum Steuern der Verteilung der ersten und zweiten Verteilereinrichtungen (68,74) gebildet werden durch eine einzige Schaltung (84).
  8. Vorrichtung nach Anspruch 7, dadurch gekennzeichnet, daß die einzige Schaltung (84) ein Zähler mit zwei Binärzuständen ist, einen Zähleingang aufweisend, verbunden mit dem Ausgang des Zählers mit N/2 Binärzuständen, der auf einem Ausgang bei jedem Übergang in seinen Initialzustand einen Impuls liefert, und einen zweiten Eingang zum Empfangen eines Rückstellungssignals (TT), wobei dieser Zähler auf einem mit den ersten und den zweiten Verteilereinrichtungen verbundenen Ausgang ein Steuersignal HB liefert.
  9. Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, daß sie zum Ansteuern der Zeilen des Bildschirms wenigstens ein Register umfaßt, das einen ersten Eingang zum Empfangen eines Taktsignals und einen zweiten Eingang zum Empfangen eines Datensignals aufweist.
  10. Vorrichtung nach Anspruch 9, dadurch gekennzeichnet, daß sie umfaßt:
    ein erstes Register (26) mit N Stufen zur Ansteuerung von N Zeilen des ersten Paritätstyps des ersten und des zweiten Teils (10) des Bildschirms, das einen ersten Eingang zum Empfangen eines Taktsignals und einen zweiten Eingang zum Empfangen eines ersten Datensignals (DLI) aufweist,
    ein zweites Register (30) mit N Stufen zur Ansteuerung von N Zeilen des zweiten Paritätstyps des ersten und des zweiten Teils (12) des Bildschirms, das einen ersten Eingang zum Empfangen eines Taktsignals und einen zweiten Eingang zum Empfangen eines ersten Datensignals (DLP) aufweist.
EP91400260A 1990-02-06 1991-02-04 Verfahren zur Steuerung eines Matrixbildschirms, bestehend aus zwei unabhängigen Teilen und Einrichtung zu seiner Durchführung Expired - Lifetime EP0441692B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9001346A FR2657987B1 (fr) 1990-02-06 1990-02-06 Procede de commande d'un ecran matriciel comportant deux parties independantes et dispositif pour sa mise en óoeuvre.
FR9001346 1990-02-06

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EP0441692B1 true EP0441692B1 (de) 1995-05-03

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US5512915A (en) 1996-04-30
JPH04213494A (ja) 1992-08-04
DE69109322T2 (de) 1996-01-04
FR2657987A1 (fr) 1991-08-09
FR2657987B1 (fr) 1992-04-10
DE69109322D1 (de) 1995-06-08

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