EP0426305A1 - Méthode pour attaquer des fenêtres de différentes profondeurs - Google Patents

Méthode pour attaquer des fenêtres de différentes profondeurs Download PDF

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Publication number
EP0426305A1
EP0426305A1 EP90310819A EP90310819A EP0426305A1 EP 0426305 A1 EP0426305 A1 EP 0426305A1 EP 90310819 A EP90310819 A EP 90310819A EP 90310819 A EP90310819 A EP 90310819A EP 0426305 A1 EP0426305 A1 EP 0426305A1
Authority
EP
European Patent Office
Prior art keywords
windows
dielectric
etching
substrate
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP90310819A
Other languages
German (de)
English (en)
Inventor
Chih-Yuan Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0426305A1 publication Critical patent/EP0426305A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Definitions

  • This invention relates to a method of manufacturing integrated circuits having windows of different depths.
  • Integrated circuit technology has progressed to the point where some components of the most technologically sophisticated silicon integrated circuits have dimensions less then one micrometer. As will he readily appreciated by those skilled in the art, dimensions this small permit a relatively large number of devices to be fabricated per unit area on a silicon wafer, and also facilitate fabrication of circuits with a large number of components.
  • Devices are generally electrically contacted through openings, commonly referred to as windows, formed in a dielectric layer overlying a substrate.
  • the term, "substrate,” is used to mean material which lies beneath and supports another material.
  • the difficulties associated with electrically contacting the devices also increase because of the need to make the electrical contact areas as small as possible and because of the large number of contacts required.
  • the difference in heights may be as much as, for example, 500nm to 800nm. Consequently, overetching of the gate occurs in order to etch through the dielectric to the source and drain regions. Moreover, it is critical to open all windows to the source and drain regions, and a slight overetch of the source and drain regions is required to compensate for non-uniformities in the dielectric layer thickness, as well as for non-uniformities in the etching process to ensure opening of all windows. The overetch of the source and drain regions necessarily further overetches the gate windows as well.
  • nitride-to-oxide etch selectively is generally not large; e.g., 2:1 to 5:1, and is usually less uniform over the wafer as the selectivity becomes greater. As discussed in the last paragraph, a larger etch selectivity is desirable. Additionally, many phosphorous-doped dielectrics getter contaminants, and the nitride may impair the effectiveness of the gettering process.
  • a method of integrated circuit manufacture in which windows of different depths are opened to expose selected portions of a substrate by forming a planar layer of dielectric material on a substrate, etching the dielectric material to form first windows which expose portion of the substrate, and to partly etch second windows, selectively depositing a conductive material on the bottom of the first window, and etching said dielectric until the second windows are open; i.e., expose portions of said substrate.
  • the second windows are deeper than are the first windows.
  • the deposited conductive material has a high etching selectivity with respect to the dielectric materials. The etching selectivity prevents significant overetching of the material at the bottom of the first windows.
  • the first and second windows expose selected portions of gate runners on the field oxide, and selected portions of source/drain regions, respectively.
  • the deposited material is a metal.
  • FIGS. 1 and 2 are sectional views of devices of an integrated circuit at intermediate stages of fabrication according to the method of this invention. For reasons of clarity, the elements depicted are not drawn to scale.
  • FIG. 1 A sectional view of an integrated circuit, fabricated according to this invention, at an intermediate stage of fabrication is depicted in FIG. 1. Shown are substrate 1, and disposed thereover; gate electrode structure 3; source and drain regions 5, field oxide regions 7; gate runner 9 on the field oxide region; dielectric layer 11; and, photoresist 13. As depicted, the source and drain regions are on opposite sides of the gate electrode structure.
  • the gate structure 3 has insulating sidewalls 31, polysilicon layer 33, and silicide layer 35. Layers 33 and 35 are sequentially disposed over the substrate; i.e., layer 33 is nearer the substrate than is layer 35.
  • the gate runner has components 41,43, and 45, which are analogous to components 31,33, and 35, respectively, of the gate.
  • the gate runner depicted is connected to another device (not depicted), which is either above or below the plane of the figure.
  • dielectric layer 11 is about 1200nm thick.
  • the dielectric is about 500nm thick at its thinnest point.
  • the dielectric material is thicker over the source/drain regions than it is over the gate runners. It is typically a silica-based glass.
  • the silicide on the gate is formed by conventional techniques and is approximately 60nm thick. Other thicknesses and materials may be used as will be readily appreciated by those skilled in the art.
  • etching of the dielectric begins with a standard etch having a reasonable oxide to silicide selectivity. A reasonable selectivity is in 10:1 or 15:1. This window etch is continued until the first windows on the gate runner are opened. The second windows which will ultimately expose the source/drain regions are partly etched. The end point is detected using well-­known techniques. Some overetch is desirable to ensure that all windows on all gate runners are entirely opened. The amount of overetch is likely to be only 20nm to 30nm of silicide, and is less than half of the total amount of silicide. The small amount of overetching of the silicide will not result in the opening of any of the windows to the source and drain regions, considering the different depths and the etching selectivity.
  • a metal or other conductive material is now selectively deposited a the exposed portions of the gate runner; i.e., on the bottoms of the first windows.
  • a typical metal is tungsten which is easily deposited selectively using techniques that are well-known to those skilled in the art.
  • the selective tungsten thickness is not critical, and a layer between 20nm and 50nm thick is sufficient.
  • tungsten on the gate runners only has several advantages, as contrasted to selective deposition on both the gate runners and the source/drain regions.
  • etching of the second windows for the source/drain regions resumes and the structure depicted in FIG. 2 is ultimately obtained.
  • Metallizations 25 for all windows are performed using techniques well known to those skilled in the art.
  • a somewhat thicker dielectric layer approximately 1500nm, may be deposited and, after etching the first windows for the gate runners with the window photo-resist on, the window etching is terminated and the photoresist is stripped off.
  • the wafer is then put into a selective tungsten deposition reactor and tungsten is selectively deposited on the exposed window areas of the gate runners.
  • the wafer is then returned to the oxide etcher, and the window formation is completed.
  • the final oxide etch is performed with a non-masking etch, the initial dielectric thickness is sufficient so that the final oxide thickness is the same as it would have been if the photoresist had remained for the final etch, as previously described.
  • Another embodiment deposits a thin layer of silicon nitride, e.g. 20nm to 30nm after the dielectric layer has been planarized to the desired thickness.
  • the silicon nitride i.e., second dielectric layer
  • the etching chemistry is switched to an etching chemistry which will etch the first dielectric layer. This etching chemistry is continued until all window openings on the gate runners are opened.
  • the photoresist is then stripped and the wafer placed into a selective tungsten deposition reactor. Tungsten is selectively deposited on the portions of the gate runners exposed by the window openings.
  • the window etch is continued using the nitride as an etch mask.
  • the selective tungsten will also, of course, serve as an etch stop in the gate runner window.
  • the nitride layer can be stripped away after the windows in the source/drain region have been opened.
  • a metal need not be deposited on the bottom of the shallower, i.e., first window. Any conductive material that can be deposited selectively and which has a high etch selectivity with respect to the dielectric can be deposited. Other variations will be readily thought of by those skilled in the art.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
EP90310819A 1989-10-12 1990-10-03 Méthode pour attaquer des fenêtres de différentes profondeurs Withdrawn EP0426305A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/420,788 US4933297A (en) 1989-10-12 1989-10-12 Method for etching windows having different depths
US420788 1989-10-12

Publications (1)

Publication Number Publication Date
EP0426305A1 true EP0426305A1 (fr) 1991-05-08

Family

ID=23667847

Family Applications (1)

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EP90310819A Withdrawn EP0426305A1 (fr) 1989-10-12 1990-10-03 Méthode pour attaquer des fenêtres de différentes profondeurs

Country Status (3)

Country Link
US (1) US4933297A (fr)
EP (1) EP0426305A1 (fr)
JP (1) JPH03138934A (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
JP2578193B2 (ja) * 1989-02-01 1997-02-05 沖電気工業株式会社 半導体素子の製造方法
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
JP2892421B2 (ja) * 1990-02-27 1999-05-17 沖電気工業株式会社 半導体素子の製造方法
US5086017A (en) * 1991-03-21 1992-02-04 Industrial Technology Research Institute Self aligned silicide process for gate/runner without extra masking
US5298463A (en) * 1991-08-30 1994-03-29 Micron Technology, Inc. Method of processing a semiconductor wafer using a contact etch stop
KR940010197A (ko) * 1992-10-13 1994-05-24 김광호 반도체 장치의 제조방법
US5766552A (en) * 1993-04-20 1998-06-16 Actimed Laboratories, Inc. Apparatus for red blood cell separation
US5660798A (en) * 1993-04-20 1997-08-26 Actimed Laboratories, Inc. Apparatus for red blood cell separation
US5933756A (en) * 1995-10-18 1999-08-03 Ricoh Company, Ltd. Fabrication process of a semiconductor device having a multilayered interconnection structure
TW399266B (en) * 1997-02-04 2000-07-21 Winbond Electronics Corp Method for etching contact windows
JP3102405B2 (ja) * 1998-02-13 2000-10-23 日本電気株式会社 半導体装置の製造方法
US6197639B1 (en) * 1998-07-13 2001-03-06 Samsung Electronics Co., Ltd. Method for manufacturing NOR-type flash memory device
JP2000188332A (ja) * 1998-12-22 2000-07-04 Seiko Epson Corp 半導体装置及びその製造方法
CN100442490C (zh) * 2003-12-16 2008-12-10 国际商业机器公司 减小接触高度的双极型和cmos集成
US7528065B2 (en) * 2006-01-17 2009-05-05 International Business Machines Corporation Structure and method for MOSFET gate electrode landing pad
US8574980B2 (en) * 2007-04-27 2013-11-05 Texas Instruments Incorporated Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device
US7642153B2 (en) * 2007-10-23 2010-01-05 Texas Instruments Incorporated Methods for forming gate electrodes for integrated circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003587A1 (fr) * 1983-03-09 1984-09-13 Advanced Micro Devices Inc Procede et structure en sandwich de polycides inverses
EP0241729A2 (fr) * 1986-03-27 1987-10-21 General Electric Company Interconnexion de liaison sans rebord avec un stoppeur diélectrique de gravure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810795A (en) * 1972-06-30 1974-05-14 Ibm Method for making self-aligning structure for charge-coupled and bucket brigade devices
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4392150A (en) * 1980-10-27 1983-07-05 National Semiconductor Corporation MOS Integrated circuit having refractory metal or metal silicide interconnect layer
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
US4442591A (en) * 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
JPS6065545A (ja) * 1983-09-21 1985-04-15 Hitachi Micro Comput Eng Ltd 半導体装置の製造方法
KR940006668B1 (ko) * 1984-11-22 1994-07-25 가부시끼가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치의 제조방법
JPS63133550A (ja) * 1986-11-26 1988-06-06 Agency Of Ind Science & Technol 半導体装置の製造方法
JPS63133551A (ja) * 1986-11-26 1988-06-06 Agency Of Ind Science & Technol 半導体装置の製造方法
US4824521A (en) * 1987-04-01 1989-04-25 Fairchild Semiconductor Corporation Planarization of metal pillars on uneven substrates
JPS6411346A (en) * 1987-07-03 1989-01-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003587A1 (fr) * 1983-03-09 1984-09-13 Advanced Micro Devices Inc Procede et structure en sandwich de polycides inverses
EP0241729A2 (fr) * 1986-03-27 1987-10-21 General Electric Company Interconnexion de liaison sans rebord avec un stoppeur diélectrique de gravure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
RESEARCH DISCLOSURE, no. 305, September 1989, page 640, disclosure no. 30516, New York, US; "Process for borderless contacts to silicon" *

Also Published As

Publication number Publication date
US4933297A (en) 1990-06-12
JPH03138934A (ja) 1991-06-13

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