EP0411742A2 - Dispositifs de commutation des messages - Google Patents
Dispositifs de commutation des messages Download PDFInfo
- Publication number
- EP0411742A2 EP0411742A2 EP90303230A EP90303230A EP0411742A2 EP 0411742 A2 EP0411742 A2 EP 0411742A2 EP 90303230 A EP90303230 A EP 90303230A EP 90303230 A EP90303230 A EP 90303230A EP 0411742 A2 EP0411742 A2 EP 0411742A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- message switching
- message
- central
- switching unit
- map
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Definitions
- the present invention relates to a message switching arrangement.
- the present invention finds utility in the area of telecommunications, such digital telecommunication exchanges known as System X.
- System X digital telecommunication exchanges
- the function of such exchanges are described in an article by A.S. Philip, entitled “The System X Digital Switching Subsystem” published in Systems Technology No. 32, September 1979.
- An aim of the present invention is to provide a message switching arrangement which executes an algorithm in accordance with the above criteria.
- the present invention has the advantages of efficient use of the switching arrangement, whereby queuing delays are reduced, the same path is used for duplex operation and traffic is evenly distributed over the CMSUs.
- each message switching unit has an associated routing map which is addressed by the message switching unit and enables the message switching unit to route incoming messages to a particular outgoing time division multiplex timeslot.
- LAP Link Access Protocol
- the digital switching subsystem, DSS concentrates the timeslots 16's, the signalling channels, from the external pulse code modulation PCM links onto the outer or maintenance MSUs, using switch paths on the DSS.
- the function of the Message Switch is two fold. Firstly to provide port and LAP interchange of call control messages in the signalling channel to match the equivalent circuit switched paths through the DSS, and secondly to provide a message route between the Customer Service Module CSM and the CSM controller function, for maintenance messages.
- the call control messages are in LAP numbers 1 to 15 and 17 to 31.
- LAP 0 is not used as there is no traffic channel 0.
- the Message Switch terminates these LAPs and extracts the higher level message content for re-transmission to the destination.
- LAPs 33 to 47 and 49 to 63 For DPNSS, virtual LAPs exist on LAPs 33 to 47 and 49 to 63. These need to routed along with the real LAPs. There is a one-to-one relationship of the virtual LAPs and the real LAPs.
- the Message Switch function is realised by the addition of the MSU serial interface units to the DSS switch.
- the MSUs are arranged as a three stage switch for message routing in the following schematic way. All the connections are made by switch paths. There are nominally 24 paths which are made to each outer MSU from the external PCM links. Each outer MSU connects to all 8 central MSUs. The central MSUs are connected to all 32 Outer MSUs.
- the message routing capability is realised by a number of identical Message Switching Units (MSU) interconnected to form a three-stage message switch of the required capacity.
- MSU Message Switching Units
- Each MSU is essentially a fully available message switch in its own right, providing connections between 32 channels.
- the MSUs are interconnected via the circuit switch.
- the circuit switching function provides flexibility of circuit allocation and facilitates the implementation of a security scheme based on 1 in N redundancy of MSUs; it is not otherwise involved in message routing.
- the MSUs are arranged as a three stage switch as shown in Figure 1, the RX outer MSUs are the same as the TX outer MSUs hence only 32+8 MSUs are used.
- the outer switches consist of 32 MSUs and the central switches consist of 8 MSUs. This particular configuration offers enough MSUs both to the outer and central switches so as not to overload either layer.
- the outer which MSUs have a higher work load per message than the central MSUs.
- Some of the tasks performed by the outer MSU includes the acknowledgement at layer 2 to the sending terminal, addition of source and destination address of the received frame before sending to central MSU, and recalculation of the Frame Check Sequence (FCS).
- FCS Frame Check Sequence
- the task performed by the central MSUs is simply to route a message from one outer MSU to another.
- K (Li + Lo) Moduli Nc
- Li the full link address of the incoming DASS2/DPNSS link.
- Lo the full link address of the outgoing DASS2/DPNSS link.
- Nc Number of CMSUs.
- This algorithm is applied by the first stage routing function to derive the integer, K (less than Nc), as an index into the internal channel logical number to physical channel translation table in order to determine which of the available channels to the central stage is to be used.
- a translation is held between CMSU logical number and physical channel number for internal channels.
- the translation is used in selection of a central MSU for the routing of messages.
- OMSUs will normally set up the translation such that Logical CMSU n is accessed via channel n.
- OMSUs will change their CMSU Logical number to channel translations so as to map out faulty CMSUs specified in Switch Re-configuration messages.
- Message switching is achieved by utilising interconnected MSUs to route messages across the Message Switch.
- the outer MSUs route the messages by referring to the switch maps they hold, but the central MSUs route the messages according to their message content. Therefore, the maps on central MSUs are not utilised.
- the switching stages are referred to by number, the "receive" outer MSU is stage 1, the central MSU stage 2, and the transmit MSU stage 3.
- Stages 1 and 3 require routing maps.
- the maps hold details of the links, and they are symmetrical, i.e. one set of information about a link allows the MSU to perform stage 1 or stage 3 functions.
- the key-element in the switching is the map.
- the map has 32 x 32 entries, each entry is 4 bytes long, and each MSU has its own map. Thus the map is 4k bytes long.
- Data held in the Map allows the MSU to route incoming messages to the correct outgoing timeslot and LAP, and needs to be held on a dynamic basis.
- the map may be considered as an array, with one index being the incoming/outgoing timeslot number, and the other index being the LAP number.
- Two anomalies exist within the map. Firstly, the top "n" channels of the map will always be empty. These are the channels that cross-connect to the "n" stage MSUs. Secondly, there is no such thing as LAP 0, although space is allocated in the map for it.
- Channel n always links the outer MSU to central MSU n. This means that in the 32-8-32 configuration, channel 0 on the outer MSU is connected to CMSU 0, channel 1 to CMSU 1 etc.
- a message from the network will come in on a timeslot, the timeslot number gives one index into the Map. Reading the content of the message gives the LAP number and therefore the other index into the Map.
- the Map entry for the timeslot and LAP can be read, and the extended address, formed and appended to the message. When the lengths, CRC check fields etc. to satisfy the internal protocol have been added to the 64 byte block, it can be transmitted on an internal channel, decided upon by the algorithm. Note that what is referred to as "Far end” information in the Map, is the same as the "Destination" information in the extended address. It is not called destination information in the Map, because it serves to route data in two directions.
- a message coming in (to a stage 3 MSU) across the switch from a central MSU will have an extended address field appended.
- the stage 3 MSU can validate the extended address field.
- the Destination MSU should be itself.
- the Map is represented here for clarity as a two-dimensional array, however this does not constrain the implementation as a one-dimensional array may be more convenient to design around.
- routing information i.e. MSU, channel and LAP
- MSU Mobility Management Entity
- the Map is suitable for routing messages in either direction, i.e. incoming from network or incoming across the switch from a central MSU.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8917738A GB2235351A (en) | 1989-08-03 | 1989-08-03 | Message switching arrangement |
GB8917738 | 1989-08-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0411742A2 true EP0411742A2 (fr) | 1991-02-06 |
EP0411742A3 EP0411742A3 (en) | 1992-04-22 |
Family
ID=10661084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19900303230 Withdrawn EP0411742A3 (en) | 1989-08-03 | 1990-03-27 | Message switching arrangements |
Country Status (10)
Country | Link |
---|---|
EP (1) | EP0411742A3 (fr) |
JP (1) | JPH0371742A (fr) |
KR (1) | KR910005714A (fr) |
CN (1) | CN1049257A (fr) |
AU (1) | AU623007B2 (fr) |
CA (1) | CA2014198A1 (fr) |
FI (1) | FI903850A0 (fr) |
GB (1) | GB2235351A (fr) |
IE (1) | IE902104A1 (fr) |
PT (1) | PT94867A (fr) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3993873A (en) * | 1973-07-05 | 1976-11-23 | Danray, Inc. | Digital switching for PABX telephone communication systems |
EP0039134A1 (fr) * | 1980-04-24 | 1981-11-04 | THE PLESSEY COMPANY plc | Réseau de commutation utilisant des modules de commutation numérique |
EP0073917A1 (fr) * | 1981-09-01 | 1983-03-16 | International Business Machines Corporation | Système de réarrangement de voies dans un réseau de connexion avec blocage |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2447652A1 (fr) * | 1979-01-24 | 1980-08-22 | Materiel Telephonique | Operateur pour reseau de commutation de donnees numeriques par paquets |
US4817083A (en) * | 1987-03-06 | 1989-03-28 | American Telephone And Telegraph Company At&T Bell Laboratories | Rearrangeable multiconnection switching networks employing both space division and time division switching |
LU87095A1 (de) * | 1987-06-11 | 1988-04-05 | Siemens Ag | Schaltungsanordnung fuer eine zentralgesteuerte fernmeldevermittlungsanlage,insbesondere pcm-fernsprechvermittlungsanlage,mit einem zentralteil und mit diesem verbundenen anschlussgruppen |
-
1989
- 1989-08-03 GB GB8917738A patent/GB2235351A/en not_active Withdrawn
-
1990
- 1990-03-27 EP EP19900303230 patent/EP0411742A3/en not_active Withdrawn
- 1990-04-09 CA CA002014198A patent/CA2014198A1/fr not_active Abandoned
- 1990-04-13 KR KR1019900005152A patent/KR910005714A/ko not_active Application Discontinuation
- 1990-05-09 AU AU54890/90A patent/AU623007B2/en not_active Ceased
- 1990-05-30 JP JP2138665A patent/JPH0371742A/ja active Pending
- 1990-06-12 IE IE210490A patent/IE902104A1/en unknown
- 1990-07-31 PT PT94867A patent/PT94867A/pt not_active Application Discontinuation
- 1990-07-31 CN CN90106513A patent/CN1049257A/zh active Pending
- 1990-08-02 FI FI903850A patent/FI903850A0/fi not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3993873A (en) * | 1973-07-05 | 1976-11-23 | Danray, Inc. | Digital switching for PABX telephone communication systems |
EP0039134A1 (fr) * | 1980-04-24 | 1981-11-04 | THE PLESSEY COMPANY plc | Réseau de commutation utilisant des modules de commutation numérique |
EP0073917A1 (fr) * | 1981-09-01 | 1983-03-16 | International Business Machines Corporation | Système de réarrangement de voies dans un réseau de connexion avec blocage |
Non-Patent Citations (3)
Title |
---|
GLOBAL TELECOMMUNICATIONS CONFERENCE, SESSION 29, PAPER 8. vol. 2, 15 November 1987, TOKYO JP G.VALSECCHI ET AL.: 'Reliability and Maintainability in a Switching Network for Large Exchanges for the LINEA UT' * |
MINI MICRO CONFERENCE RECORD, SESSION 6, PAPER 3. 1984, NEW YORK US pages 1 - 13; A.UGGE: 'New Complex Functions for Modern Exchanges are Provided by Well-Proven VLSI Technologies' * |
PHILIPS TELECOMMUNICATION REVIEW. vol. 42, no. 3, September 1984, HILVERSUM NL pages 111 - 131; H.J.GOEBERTUS: '5ESS-PRX Architecture' * |
Also Published As
Publication number | Publication date |
---|---|
KR910005714A (ko) | 1991-03-30 |
EP0411742A3 (en) | 1992-04-22 |
CA2014198A1 (fr) | 1991-02-03 |
AU623007B2 (en) | 1992-04-30 |
IE902104A1 (en) | 1991-02-13 |
FI903850A0 (fi) | 1990-08-02 |
CN1049257A (zh) | 1991-02-13 |
GB8917738D0 (en) | 1989-09-20 |
GB2235351A (en) | 1991-02-27 |
JPH0371742A (ja) | 1991-03-27 |
AU5489090A (en) | 1991-02-07 |
PT94867A (pt) | 1992-04-30 |
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