EP0410897B1 - Gerät zur Wiedergabe von digitalen Signalen - Google Patents

Gerät zur Wiedergabe von digitalen Signalen Download PDF

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Publication number
EP0410897B1
EP0410897B1 EP19900402177 EP90402177A EP0410897B1 EP 0410897 B1 EP0410897 B1 EP 0410897B1 EP 19900402177 EP19900402177 EP 19900402177 EP 90402177 A EP90402177 A EP 90402177A EP 0410897 B1 EP0410897 B1 EP 0410897B1
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EP
European Patent Office
Prior art keywords
data
digital signal
address
reproduced
frame
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EP19900402177
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English (en)
French (fr)
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EP0410897A3 (en
EP0410897A2 (de
Inventor
Tadashi Fukami
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Sony Corp
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Sony Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing

Definitions

  • the invention relates to a digital signal reproducing apparatus and, more particularly, to a digital signal reproducing apparatus, such as a rotary-head digital audio tape recorder (R-DAT).
  • a digital signal reproducing apparatus such as a rotary-head digital audio tape recorder (R-DAT).
  • a rotary-head digital audio tape recorder R-DAT
  • a pair of tracks formed by a pair of magnetic heads are called an interleave pair, and a kind of interleaving is performed in which two tracks constitute one frame.
  • Frame addresses recorded on the tracks of the interleave pair have identical values, so that the interleave pair can be easily identified from their frame addresses upon playback.
  • a memory functioning as a buffer is provided for time-base expansion and also for performing the deinterleave operation.
  • US-A-4696008 discloses an apparatus wherein a reference address is generated based on counting blades. The reference address replaces the extracted address when both do not match.
  • an object of this invention to provide a digital signal reproducing apparatus capable of reading the reproduced data of the same frame address into the same block in a memory with high reliability, without lowering ECC correction capability, without performing forced interpolation, and without enlarging hardware size.
  • a digital signal reproducing apparatus for reproducing a digital signal from a recording medium, as defined in claim 1.
  • Fig. 1 shows the overall structure of an R-DAT tape recorder, in which a drum 1 has a diameter of 30 mm and rotates at 2000 rpm. A pair of magnetic heads 2A and 2B are attached to drum 1 and are separated by an angular interval of 180°. A magnetic tape 3 is obliquely wound around drum 1 over a wrap angle of 90°. Magnetic tape 3 extends between reel hubs 4A and 4B of a tape cassette and is driven at a linear speed of 8.15 mm/sec by a capstan 5 and a pinch roller 6 in the well-known manner.
  • Magnetic heads 2A and 2B alternately come into contact with magnetic tape 3, so that oblique tracks 7A and 7B are formed on magnetic tape 3, as shown in Fig. 2.
  • the tape width A of magnetic tape 3 is 3.81 mm
  • the magnetic gap of one rotary head 2A is inclined by an angle + ⁇ with respect to a line perpendicular to the track.
  • the magnetic gap of the other rotary head 2B is inclined by an angle by - ⁇ with respect to the line perpendicular to the track.
  • ⁇ 20°
  • the angles of the magnetic gaps of magnetic heads 2A and 2B are referred to as the + azimuth and -azimuth, respectively.
  • magnetic heads 2A and 2B are alternately selected by a head change-over switch 8.
  • a signal to be recorded from a terminal r of a recording/reproducing switch 9 is supplied to magnetic heads 2A and 2B through rotary transformers (not shown).
  • the signals being reproduced by magnetic heads 2A and 2B, and the rotary transformers are taken out at a terminal p of recording/reproducing switch 9.
  • An analog audio signal fed in at an input terminal 10 is supplied to an A/D converter 12 through a low-pass filter 11 and converted into a digital audio signal, typically using a sampling frequency of 48 kHz and 16-bit linear digitization.
  • the digital audio signal from A/D converter 12 is supplied to a recording signal processor 13 where error correction coding of the digital audio signal and the conversion into a recording format, which will be explained hereinafter, are performed.
  • an ID signal PCM-ID
  • PCM-ID to identify the on/off state of preemphasis for the signal to be recorded, the sampling frequency, the number of digitization bits, and the like is added.
  • subcodes such as program number, time code, and the like of the signal to be recorded and the ID signal (subcode ID) for the subcodes are formed by a subcode encoder (not shown) and are supplied to recording signal processor 13 and fed in at a terminal 14.
  • the serial recording data for each track is generated by recording signal processor 13 synchronously with the rotation of magnetic heads 2A and 2B, and the recording data is supplied to head change-over switch 8 through a recording amplifier 15 and terminal r of recording/reproducing switch 9. Thus, the recording data is alternately supplied to magnetic heads 2A and 2B by head change-over switch 8.
  • the signals reproduced by magnetic heads 2A and 2B are supplied to a reproducing amplifier 16 through head change-over switch 8 and through terminal p of recording/reproducing switch 9.
  • the output signal from reproducing amplifier 16 is supplied to a phase-locked loop circuit (PLL) 17.
  • PLL 17 the clock signals that are synchronized with the reproduction signal are extracted.
  • the reproduced signal is then subjected to processing for error correction, interpolation, and the like in a reproduction signal processor 18.
  • the reproduced digital audio signal is supplied to a D/A converter 19, and the analog audio signal from D/A converter 19 is fed out at an output terminal 21 after having passed through a low-pass filter 20.
  • the subcodes and subcode ID are separated in the reproduction signal processor 18 and are fed out at an output terminal 22.
  • a subcode decoder (not shown) is connected to output terminal 22, and the control data and the like are formed from the subcodes.
  • Timing control unit 23 also generates a clock and timing signal employed by both recording signal processor 13 and reproduction signal processor 18.
  • Fig. 3A shows an arrangement of the data of one segment which is recorded by one rotary head. It is assumed that a unit amount of the recording data is one block and 196 blocks (7500 ⁇ s) of data are included in one segment. A margin of eleven blocks is provided at both end portions of one segment corresponding to the respective ends of the track. Subcode 1 and subcode 2 are recorded adjacent the end margins, and these two subcodes consist of the same data recorded twice. The subcode includes the program number and the time code. A run-in interval of two blocks for the PLL and postamble interval of one block are arranged on both sides of a recording area of eight blocks for each subcode 1 and 2.
  • An interlock gap in which no data is recorded is next provided and a five-block pilot signal for Automatic Track Finding (ATF) is recorded between the two interlock gaps of three blocks each.
  • a PCM signal that has been subjected to the recording processing is recorded in an area having a length of 128 blocks that is preceded by a run-in interval for the PLL of two blocks at the center of one segment.
  • the PCM signal is the data corresponding to the audio signal for the period of time when magnetic heads 2A and 2B rotate one-half rotation.
  • the PCM signal typically comprises stereophonic PCM signals for two channels consisting of the left (L) and right (R) channels and the parity data for the error detection/correction codes.
  • L left
  • R right
  • the data Lo consists of the even-number designated data of the L channel and the parity data concerned with that data.
  • the data Ro consists of the odd-number designated data of the R channel and the parity data concerned with that data.
  • the odd numbers and even numbers denote the order in which they are counted from the beginning of the interleave blocks.
  • Data constituting one segment having the same arrangement as that of the foregoing track is also recorded in the successive track formed by the other magnetic head 2B.
  • data Re is recorded in the left-half portion of the data area of the track
  • data Lo is recorded in the right-half portion of the central data area.
  • the data Re consists of the even-number designated data of the R channel and the parity data concerned with that data.
  • the data Lo consists of the odd-number designated data of the L channel and the parity data concerned with that data.
  • Fig. 3B shows a data arrangement of one block of the PCM signal.
  • a block sync signal of eight bits, constituting one symbol is added at the beginning of a block, the PCM-ID of eight bits is then added, and a block address of eight bits is added after the PCM-ID.
  • An error correction coding process involving simple parity is performed with respect to two symbols (W1 and W2) of the PCM-ID and block address.
  • the eight-bit parity code is added after the block address.
  • a data format of the PCM-ID and symbols (W1 and W2) of the block address in the above-mentioned PCM signal block is shown in Fig. 4.
  • the PCM-ID is allotted for every other block of the PCM signal recorded in the 128 data block area of the track, that is, it is allotted for 64 blocks.
  • the data format of the above-stated symbols (W1 and W2) is constructed of eight blocks.
  • the PCM-ID area contains ID signals, ID-1 to ID-8, each of which has two bits, and a four-bit frame address. An optional code may be recorded in the blocks in which the ID signals and frame address are not recorded.
  • the contents such as the presence or absence of emphasis, the sampling frequency, the number of channels, the number of digitization, the track width, the permission or inhibition to copy, and the like are recorded on ID-2 to ID-7 after they are encoded.
  • ID-1 to ID-7 and the frame address have the same data in the respective segments of the interleave pair.
  • the block address is made up of seven bits, excluding the most significant bit (MSB). By setting the most significant bit of the block address to "0", it is indicated that the block includes the digital data, that is, the PCM data.
  • the block address of seven bits sequentially changes, such as from (00) to (7F), using hexadecimal notation.
  • the PCM-ID that is recorded in each block having the block address whose lower three bits are (000) (010) (100) (110) is determined as described above.
  • the optional PCM-ID code can be recorded in each block having a block address whose lower three bits are (001) (011) (101) (111).
  • Fig. 3C shows a data arrangement of one block of the subcodes, and the data constitution is similar to that of the foregoing digital signal block.
  • the most significant bit of the symbol W2 of the subcode block is set to "1", thereby indicating that the block is the subcode block.
  • the lower four bits of the symbol W2 are used as the block address.
  • Eight bits of the symbol W1 and three bits in the symbol W2, except the MSB and the block address, are used as the subcode ID.
  • the error correction coding process of simple parity is executed with regard to the two symbols (W1 and W2) of the subcode block and an eight-bit parity code is added.
  • the subcode ID data that is recorded in the even number designated block address, in which the least bit (LSB) of the block address is "0" differs from the subcode ID data that is recorded in the odd-number designated block address, because the LSB of that block address is "1".
  • the subcode ID includes the control ID to designate the reproducing method, the time code, and the like.
  • the subcode data is subjected to error correction coding processing using the Reed-Solomon code similar to the digital signal data.
  • Fig. 5A shows a code constitution of the data that is recorded by one magnetic head, head 2A for example
  • Fig. 5B shows a code constitution of the data that is recorded by the other magnetic head 2B.
  • the PCM signal having 16 digitization bits is divided into upper eight bits and lower eight bits and subjected to the coding processing of the error detection/correction codes, in which eight bits are used as one symbol.
  • the coding processes of an error detection code C1 and an error correction code C2 are executed with respect to each of the column and row directions of the two dimensional arrangement of the data comprising the even-number designated data Le of the L channel consisting of the symbols of (L0, L2, ..., L1438) and the odd-number designated data Ro of the R channel of (R1, R3, ..., R1439).
  • the twenty-eight symbols in the column direction are subjected to a C1 coding process using a (32, 28, 5) Reed-Solomon code.
  • a parity data P of four symbols of the C1 code is arranged at the last position of the two-dimensional arrangement.
  • the fifty-two symbols in the row direction are subjected to a C2 coding processing using a (32, 26, 7) Reed-Solomon code.
  • the C2 code is executed with respect to the twenty-six symbols of every two symbols among the fifty-two symbols.
  • a parity data Q consisting of six symbols is generated with respect to new code series, and parity data Q consisting of a total of twelve symbols of the C2 code is arranged in the central portion of the two-dimensional arrangement.
  • a similar coding processing of the C2 code is performed with regard to the other fifty-two symbols of the digital signal data arranged in the row direction.
  • the parity data Q is arranged in the central portion of the two-dimensional arrangement.
  • the code construction of Fig. 5B is that which is obtained by replacing the even-number designated PCM signals of the L channel in the code constitution of Fig. 5A by even-number designated PCM signals (R0, R2, ..., R1438) of the R channel and by replacing the odd-number designated PCM signals of the R channel by the odd-number designated PCM signals (L1, L3, ...., L1439) of the L channel.
  • One digital signal block is made up by adding the sync signal, PCM-ID, block address, and parity to the thirty two symbols arranged in the column direction in the code arrangement shown in Fig. 3B.
  • Fig. 6 shows one construction of reproduction signal processor 18.
  • the reproduced signal is supplied to a demodulation unit 32 through an input terminal 31.
  • One symbol of ten bits is demodulated into one symbol of eight bits.
  • the reproduced data from demodulation unit 32 is supplied to a data bus 35 through a data register 33 and a buffer 34.
  • a buffer 36 which can comprise a random access memory (RAM), and an error correction circuit (ECC) 37 are also connected to data bus 35.
  • RAM random access memory
  • ECC error correction circuit
  • the data stored in the buffer RAM 36 is subjected to the error correcting processes (C1 and C2 decoding) using the Reed-Solomon code by error correction circuit 37.
  • the error corrected PCM data is supplied to an interpolation unit 38 and the uncorrectable errors are interpolated.
  • the reproduced and error-corrected PCM data is fed out at an output terminal 39 and supplied to a D/A converter, such as shown at 19 in Fig. 1.
  • the subcodes are subjected to further processing, such as error correction and the like, by a subcode decoder (not shown) and fed to an output terminal for the subcodes.
  • a block address detection unit 40 is provided with the output of demodulation unit 32 and the reproduction block address is detected.
  • the reproduction block address as detected by block address detection unit is supplied to a frame address detection unit 42 and an address generation unit 41.
  • the reproduction address generated by address generation unit 41 is used as an address signal for buffer RAM 36.
  • the reproduction block address is used to write the reproduction data (23 symbols x 128 blocks), as shown in Fig. 5, of one segment every block in accordance with the order from the first block to the 128th block.
  • An address for error correction circuit (ECC) 37 is also generated by address generation unit 41 and the address for ECC 37 is supplied to buffer RAM 36.
  • the ECC address is used to read out the data from buffer RAM 36 for the respective C1 and C2 decoding and to write the error corrected data and a pointer back into buffer RAM 36.
  • the data that is the PCM data and the parity data of the C1 series that had previously been written by the reproduction address is read out of buffer RAM 36 and every block is error corrected by error correction circuit 37.
  • the corrected PCM data and the C1 pointer are written into the same block address in buffer RAM 36.
  • the C1 pointer is written into the memory area in which the parity P has already been written.
  • the error correcting process is performed with respect to all of the C1 series.
  • the C1 decoded digital signal data, C1 pointer, and parity data Q are read every C2 series and subjected to the C2 decoding in error correction circuit 37.
  • the C2 decoding comprises one symbol or two-symbol correction using the error correction code C2 and erasure correction using the C1 pointer.
  • the PCM signal that was error corrected by the C2 decoding and the C2 pointer is written into buffer RAM 36.
  • the necessary read address and write address are formed by the address generation unit 41.
  • the PCM data which have been subjected to the C1 and C2 decoding are read out of buffer RAM 36 in accordance with the original order.
  • stereophonic signals of two channels are formed by the PCM data that have been reproduced from tracks TA and TB of the interleave pair and that have been error-corrected.
  • an address formed at address generation unit 41 is provided to buffer RAM 36, and digital signal data read out of buffer RAM 36 is supplied to interpolation unit 38.
  • a frame address FAD is detected from the PCM-ID of the reproduction data provided by demodulation unit 32 based on a block address detected by the above-mentioned block address detection unit 40. More specifically, the block address (W2) varies sequentially from (06) to (7F), however, because the distinction between the ID signal and frame address FAD and an optional code can be done by the least significant bit B0 of the block address, the detection of the frame address FAD is performed consequently. Thus, the detected frame address FAD is supplied to a frame address decision unit 43.
  • the PCM-ID or subcode ID (W1), the block address (W2), and a parity, which are provided by demodulation unit 32, are supplied to an error detection unit 44.
  • error detection unit 44 the error detection is carried out using a simple parity.
  • An error pulse Per indicative of the presence or absence of an error is produced by error detection unit 44 and fed to frame address decision unit 43.
  • Frame address decision unit 43 is constructed to supply a decision signal Sid based on the above-mentioned frame address FAD and the error pulse Per to a RAM write-request generation unit 45.
  • RAM write-request generation unit 45 is constructed so that a write request signal is provided to buffer RAM 36 when the above-described decision signal Sid takes a high level, for example. Thus, when a write request signal having a high level is supplied to buffer RAM 36, reproduced data from demodulation unit 32 is written into buffer RAM 36.
  • Fig. 7 shows one embodiment of frame address decision circuit 43.
  • the result of the parity check is supplied as the error pulse Per through input terminal 51 to an A-channel frame address multiple coincidence circuit 52 and a B-channel frame address multiple coincidence circuit 53.
  • the A-channel multiple coincidence circuit 52 detects multiple coincidence of frame addresses of reproduction data reproduced by magnetic head 2A
  • the B-channel multiple coincidence circuit 53 detects multiple coincidence of frame addresses of reproduction data reproduced by magnetic head 2B.
  • the error pulse Per fed in at input terminal 51 takes a high level in the presence of an error, whereas it has a low level in the absence of an error.
  • A-channel multiple coincidence circuit 52 and B-channel multiple coincidence circuit 53 the detection operation of multiple coincidence of the frame address FAD is performed only when the error pulse Per assumes a low level.
  • the frame address FAD is supplied through an input terminal 54 to A channel multiple coincidence circuit 52, B-channel multiple coincidence circuit 53, and a comparison circuit 55.
  • a multiple coincidence signal ADa indicative of a result of multiple coincidence of a frame address FADa in the A channel is output from A-channel multiple coincidence circuit 52, while a multiple coincidence signal ADb indicative of a result of multiple coincidence of a frame address FADb in the B channel is produced from B-channel multiple coincidence circuit 53.
  • the multiple coincidence signals ADa and ADb are supplied to a selector control unit 56, a logic circuit 57, and the respective frame addresses FADa and FADb of the A channel and the B channel are fed to an AB coincidence detection unit 58 and to a selector 59.
  • AB coincidence detection unit 58 detects whether the frame addresses FADa and FADb detected by multiple coincidence in each of the A channel and the B channel coincide with each other, and an AB coincidence detection signal AD2 indicative of a coincidence detection result is produced and fed to selector control unit 56.
  • selector control unit 56 a control signal SC1 for selecting any one of the frame addresses FADa, FADb and a reference frame address FADs is developed on the basis of the multiple coincidence signals ADa, ADb and the AB coincidence detection signals AD2 and a decision rule of the reference frame address, which will be described later.
  • the above-described frame addresses FADa, FADb and the reference frame address FADs of the previous frame as selected by a second selector 60 are supplied to the first selector 59.
  • selector 59 a frame address is selected on the basis of the control signal SC1 from selector control unit 56 and SC1 from selector control unit 56 and supplied to a (+1) circuit 61 and to selector 60.
  • (+1) circuit 61 the frame address FAD as a code signal, which is supplied from selector 59 and sequentially changes from (0000) to (1111), is incremented by one and fed to a D flip-flop 62.
  • D flip-flop 62 the frame address FAD supplied from (+1) circuit 61 is accepted in response to a pulse PINT with an interleave period and acting as a clock pulse fed in at an input terminal 63, and the address FAD is fed out from D flip-flop 62 to selector 60.
  • selector 60 one or the other of the frame address FAD from selector 59 or the frame address FAD from D flip-flop 62 is selected based on a mechanical mode signal MM supplied at an input terminal 64 and the selected frame address is supplied to a comparison circuit 55 and to selector 59, respectively, as the reference frame address FADs.
  • comparison circuit 55 the reference frame address FADs is compared with the reproduced frame address FAD fed in at terminal 54.
  • a signal SCM having a high level, for example is fed to logic circuit 57, whereas when the address values are not equal a low level signal SCM is fed to logic circuit 57.
  • Logic circuit 57 can determine the timing of the reference frame address FADs on the basis of the above-mentioned multiple coincidence signals ADa and ADb.
  • signal SCM assumes a high level
  • a high-level decision signal Sid is supplied through an output terminal 65 to RAM write-request generation unit 45 based on the timing to write the reproduction data into buffer RAM 36.
  • Fig. 8 is a block diagram of an embodiment of a circuit suitable for A-channel multiple coincidence circuit 52, B-channel multiple coincidence circuit 53, and AB coincidence detection unit 58.
  • A-channel multiple coincidence circuit 52 detects whether the reproduced frame address FADa of the A channel is in the state of multiple coincidence. Because the structure and operation of the B-channel multiple coincidence circuit 53 are made to be the same as those of the A-channel multiple coincidence circuit 52, only the A-channel multiple coincidence circuit 52 will be described.
  • the reproduced frame address FADa from the A channel is fed in at an input terminal 82 in Fig. 8 and supplied to a register 84. Meanwhile, when the error pulse Per produced from the error detector 44 has a low level, that is, when no error is detected, a high-level input control signal SC2 is fed to register 84 through a terminal 86 from a control circuit (not shown) for controlling register 84.
  • register 84 only when the high-level input control signal SC2 is present is the frame address FADa1 produced.
  • the first frame address FADa1 is fed into a second register 86, and the next frame address FADa2 is fed into register 84.
  • the frame address FADa1 is fed from register 87 to an input terminal of a switch 89, and the frame addresses FADa1 and FADa2 held in registers 84 and 87 are both supplied to a coincidence detection unit 91.
  • Coincidence detection unit 91 compares the consecutive frame addresses FADa1 and FADa2 and only when it is determined that both values are equal is a high-level multiple coincidence signal ADa supplied to control the operation switch circuit 89. This coincidence signal ADa is made available at output terminal 71.
  • switch circuit 89 In response to the high-level multiple coincidence signal ADa, switch circuit 89 is set to an ON or closed state, so that the frame address FADa1 from register 87 is supplied to the AB coincidence detection unit 58 via switch 89 and a latch 93. Further, when the multiple coincidence signal ADa is at a low level because the values of the frame addresses FADa1 and FADa2 are not equal, switch 89 is set in an OFF or open state. As a result, the frame address FADa1 from the register 87 is not output so that only the multiple coincidence signal ADa having a low level is fed out at terminal 71.
  • the structure of the B-channel multiple coincidence circuit 53 is the same as the A-channel multiple coincidence circuit 52 and is composed of registers 85, 88, a coincidence detector 92, a switch 90, a latch 94, input terminal 83, and output terminal 95, and its operation is the same as the A-channel multiple coincidence circuit 52.
  • the frame addresses FADa and FADb are output from the latches 93 and 94 and fed to AB coincidence detection unit 58.
  • AB coincidence detection unit 58 detects whether the frame addresses FADa and FADb reproduced respectively from the A channel and B channel coincide with each other, and an AB coincidence detection signal AD2 indicative of the results of the coincidence detection operation is output at terminal 81.
  • a high-level AB coincidence detection signal AD2 is supplied to the selector control unit 56 of Fig. 7 through output terminal 81.
  • the R-DAT apparatus has the feature that the drum diameter, wrap angle, number of revolutions of the drum, and the like can be varied if the track format is observed, the waveforms of the reproduced RF signals are different from one another by the conditions as shown in Fig. 10.
  • Fig. 10A the reproduced RF signal waveform in a Standard Playback (SP) mode at 2000 rpm with a drum diameter of 30 mm is shown;
  • Fig. 10B the reproduced RF signal waveform in an A-A-A-Type SP mode is shown;
  • Fig. 10C the reproduced RF signal waveform in 1.5-fold speed (increased by 1 1/2 times) of the A-type is shown; in Fig.
  • FIG. 10D the reproduced RF signal waveform in an A-type Long Playback (LP) mode is shown; in Fig. 10E, the reproduced RF signal in a B-type SP mode is shown; in Fig. 10F, the reproduced RF signal waveform in 1.5-fold speed of the B-type is shown; in Fig. 10G, the reproduced RF signal waveform in a B-type LP mode is shown; and in Fig. 10H, the reproduced RF signal waveform is shown when tape speed is doubled in the SP mode.
  • LP Long Playback
  • a type means that magnetic heads 2A and 2B are provided in a stepped relationship corresponding to one half of the track pitch and B type means that there is no step between the magnetic heads 2A and 2B.
  • B type means that there is no step between the magnetic heads 2A and 2B.
  • the drum diameter is mm
  • the number of revolutions of the drum is 4000 rpm
  • the wrap angle is 180°, in both the A type and the B type.
  • the SP mode means a standard recording time mode
  • the LP mode means a long time recording mode.
  • A indicates a waveform of the reproduced signal of the A channel reproduced by the magnetic head 2A
  • B indicates a waveform of the reproduced signal of the B channel reproduced by the magnetic head 2B.
  • the suffixes "05", "06" affixed to the above-mentioned A and B are the numbers of adjacent tracks or frames.
  • the present invention sets the reference frame address FADs when reproduced data is taken into buffer RAM 36, and takes data into buffer RAM 36 based on whether the reproduced frame address FAD coincides with the reference frame address FADs. Thus, only reproduced data with the same frame address FAD can be taken into the same block of buffer RAM 36.
  • the reproduced data with the same frame address FAD can be taken into the same block of buffer RAM 36 with high reliability, without lowering ECC correction capability, without forcing interpolation, and without increasing the hardware size. Further, since the reproduced data is written into buffer RAM 36 only when the reference frame address FADs is equal to the reproduced frame address FAD, the invention is applicable to all mechanical specifications and reproducing conditions. Also, it is possible to perform stable reproduction even in the face of tracking disturbances.
  • the reference frame address FADs is determined with multiple coincidence of the frame address FAD, and it has the following three modes.
  • Figs. 9A-9C DA and DB represent the timing of the playback signals reproduced by magnetic heads 2A and 2B, respectively.
  • the frame address FAD that first provides multiple coincidence within one interleave block is selected to be the reference frame address AD common with the A channel and the B channel, and subsequent frame addresses FAD are disregarded.
  • the reference frame address FADs is determined by the following decision rule, in which OK of the multiple coincidence signal AD represents a high level at which the multiple coincidence signal AD represents a low level at which no multiple coincidence is provided.
  • selector 60 of frame address decision circuit 43 shown in Fig. 7 the frame address FAD selected by selector 59 is compared with the frame address FAD of the reproduced data in comparison circuit 55.
  • the value n of the frame address FADa is selected to be the reference frame address FADs that is common with the A and B channels within one interleave block.
  • this decision rule is applied to the cases of the reproduction of the A type SP mode of Fig. 10B, the A type LP mode of Fig. 10D and the B type SP mode of Fig. 10E, for example.
  • the reference frame address FADs in the present interleave block is decided to be the reference frame address in the next interleave block by the following decision rule:
  • the frame address FAD is incremented by one at the (+1) circuit 61 and fed through D flip-flop 62 and is selected by selector 60 by the mechanical mode MM for two-fold speed and compared with the frame address FAD of the reproduced data in comparator 55.
  • the frame address FAD that first coincides within one interleave block is selected as the reference frame address FADs for every channel in its interleave block, and subsequent frame addresses are disregarded.
  • the frame addresses FADa and FADb that provide multiple coincidence in each of the A and B channels are made to be the respective reference frame addresses of the A channel and the B channel within the present interleave block.
  • the frame address FAD selected by selector 59 of Fig. 7 is selected in selector 60 of the frame address decision circuit 43 and is compared with the frame address FAD of the reproduced data in comparison circuit 55.
  • an interleave pair with the identical frame address is constituted by two tracks formed by the two magnetic heads of the A channel and B channel, there is no two track limitation, and the identical frame address may be given for three or more tracks.
  • reproduced address data and a reference address are compared at the time of reproduction and the reproduced digital signal is selectively written into a memory based on this comparison output.
  • the reproduced digital signal with the identical frame address can be taken into the same block of a memory with high reliability, without lowering ECC correction capability, without enforceably performing interpolation, and without enlarging the hardware size.

Claims (5)

  1. Digitalsignalwiedergabegerät zur Wiedergabe eines Adressendaten zum Identifizieren eines Datenblocks aufweisenden Digitalsignals von einem Aufzeichnungsmedium (3), wobei das Digitalsignal in Form von Gruppen aus wenigstens einem Paar Spuren (7A, 7B) auf dem Aufzeichnungsmedium aufgezeichnet ist, jede Gruppe Spuren einen Datenrahmen mit einer durch wenigstens eine erste und zweite Spurrahmenadresse (FADa; FADb) in den jeweils betreffenden der Gruppe Spuren verkörperten Rahmenadresse (FAD) bildet und jede Spur mehrere mit den Spurrahmenadressen versehene Datenblöcke bildet, bestehend aus:
    einer Wiedergabeeinrichtung (2A, 2B) zum Wiedergeben des auf dem Aufzeichnungsmedium (3) mit den Adressdaten aufgezeichneten Digitalsignals,
    einer Speichereinrichtung (36) des durch die Wiedergabeeinrichtung wiedergegebenen Digitalsignals,
    einer Einrichtung (42) zum Extrahieren der Rahmenadressendaten (FAD) aus den Datenblöcken des wiedergegebenen Digitalsignals,
    einer Einrichtung (52, 53, 59, 60) zur Bildung von Referenzrahmenadressendaten (FADs) aus den extrahierten Adressendaten,
    einer Vergleichseinrichtung (55) zum Vergleichen der extrahierten Adressendaten (FAD) und der Referenzadressendaten (FADs) und
    einer Einrichtung zum selektiven Schreiben des wiedergegebenen Digitalsignals in die Speichereinrichtung in Abhängigkeit von einem Vergleichsausgangssignal (SCM) aus der Vergleichseinrichtung derart, daß die Einrichtung zum selektiven Schreiben die wiedergegebenen Daten in die Speichereinrichtung nur schreibt, wenn das Vergleichsausgangssignal aus der Vergleichseinrichtung anzeigt, daß die extrahierten Adressendaten (FAD) eines Blocks mit den Referenzadressendaten (FADs) koinzidieren,
    wobei die Einrichtung zur Bildung der Referenzrahmenadressendaten
    - eine Mehrfachkoinzidenz-Detektoreinrichtung zum Detektieren mehrfacher Koinzidenzen sukzessiverextrahierter Adressendaten aus den Datenblöcken mit einer ersten und zweiten Rahmenadressen-Mehrfachkoinzidenz-Detektoreinrichtung (52, 53) zum Detektieren der durch die Wiedergabeeinrichtung wiedergegebenen ersten und zweiten Spurrahmenadresse (FADa, FADb) und
    - eine Auswahleinrichtung (59, 60) zum Auswählen eines Ausgangssignals der ersten und zweiten Rahmenadressen-Mehrfachkoinzidenz-Detektoreinrichtung und zur Bildung der Referenzrahmenadresse (FADs) aus dem ausgewählten Ausgangssignal aufweist.
  2. Digitalsignalwiedergabegerät nach Anspruch 1, wobei das Aufzeichnungsmedium ein Magnetband und die Wiedergabeeinrichtung wenigstens einen ersten und zweiten Drehkopf (2A, 2B) zur Wiedergabe eines auf dem Band aufgezeichneten Digitalsignals aufweist.
  3. Digitalsignalwiedergabegerät nach Anspruch 2, wobei die Auswahleinrichtung (60) in Abhängigkeit von einem ausgewählten Wiedergabemodus (MM) des Digitalsignalwiedergabegeräts arbeitet.
  4. Digitalsignalwiedergabegerät nach Anspruch 3, wobei eine Fehlerdetektoreinrichtung (44) zum Detektieren eines Fehlers des wiedergegebenen, die Rahmenadressendaten enthaltenden Digitalsignals vorgesehen ist, und wobei die erste und zweite Rahmenadressen-Mehrfachkoinzidenz-Detektoreinrichtung (52, 53) in Abhängigkeit von einem Ausgangssignal (Per) der Fehlerdetektoreinrichtung gesteuert sind.
  5. Digitalsignalwiedergabegerät nach Anspruch 2, wobei der Wiedergabemodus durch einen Anwender des Geräts ausgewählt wird.
EP19900402177 1989-07-28 1990-07-27 Gerät zur Wiedergabe von digitalen Signalen Expired - Lifetime EP0410897B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1196411A JP2840680B2 (ja) 1989-07-28 1989-07-28 再生装置
JP196411/89 1989-07-28

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EP0410897A2 EP0410897A2 (de) 1991-01-30
EP0410897A3 EP0410897A3 (en) 1991-10-23
EP0410897B1 true EP0410897B1 (de) 1995-09-13

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU676504B2 (en) * 1992-12-04 1997-03-13 Sony Corporation Apparatus for recording and reproducing a digital video and audio signal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696008A (en) * 1983-12-02 1987-09-22 Canon Kabushiki Kaisha Data storing device having position determining means
EP0235782B1 (de) * 1986-03-04 1992-01-22 Sony Corporation Digitalwiedergabegerät
AU606125B2 (en) * 1987-02-06 1991-01-31 Sony Corporation Apparatus for reproducing a digital signal
US5021897A (en) * 1987-06-12 1991-06-04 Matsushita Electric Industrial Co., Ltd. Memory system for recording and reproducing block unit data

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EP0410897A3 (en) 1991-10-23
JPH0362364A (ja) 1991-03-18
DE69022328T2 (de) 1996-03-14
DE69022328D1 (de) 1995-10-19
JP2840680B2 (ja) 1998-12-24
EP0410897A2 (de) 1991-01-30

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