EP0410783B1 - Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques - Google Patents

Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques Download PDF

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Publication number
EP0410783B1
EP0410783B1 EP19900308257 EP90308257A EP0410783B1 EP 0410783 B1 EP0410783 B1 EP 0410783B1 EP 19900308257 EP19900308257 EP 19900308257 EP 90308257 A EP90308257 A EP 90308257A EP 0410783 B1 EP0410783 B1 EP 0410783B1
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EP
European Patent Office
Prior art keywords
pipeline
graphics
marker
window
frame buffer
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EP19900308257
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German (de)
English (en)
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EP0410783A2 (fr
EP0410783A3 (en
Inventor
David Pinedo
Ronald D. Larson
Darel N. Emmot
Byron A. Alcorn
Desi Rhoden
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HP Inc
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Hewlett Packard Co
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Priority to EP94201810A priority Critical patent/EP0617402B1/fr
Priority to EP94201808A priority patent/EP0617400B1/fr
Priority to EP94201809A priority patent/EP0617401A3/fr
Publication of EP0410783A2 publication Critical patent/EP0410783A2/fr
Publication of EP0410783A3 publication Critical patent/EP0410783A3/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Definitions

  • This invention relates to computer workstation window systems. More specifically, this invention relates to method and apparatus for accelerating graphics primitive rendering on multitasking workstations that utilize graphics pipelines.
  • Computer workstations provide system users with powerful tools to support a number of functions.
  • An example of one of the more useful functions which workstations provide is the ability to perform highly detailed graphics simulations for a variety of applications. Graphics simulations are particularly useful for engineers and designers performing computer aided design (CAD) and computer aided management (CAM) tasks.
  • CAD computer aided design
  • CAM computer aided management
  • Modern workstations having graphics capabilities utilize "window” systems to accomplish graphics manipulations.
  • An emerging standard for graphic window systems is the "X” window system developed at the Massachusetts Institute of Technology.
  • the X window system is described in K. Akeley and T. Jermoluk, "High-Performance Polygon Rendering", Computer Graphics , 239-246, (August 1988).
  • Modern Window systems in graphics workstations must provide high-performance, multiple windows yet maintain a high degree of user interactivity with the workstation.
  • software solutions for providing increased user interactivity with the window system have been implemented in graphics workstations.
  • software solutions which increase user interactivity with the system tend to increase processor work time, thereby increasing the time in which graphics renderings to the screen in the workstation may be accomplished.
  • a primary function of window systems in graphics workstations is to provide the user with simultaneous access to multiple processes on the workstation.
  • each of these processes provides an interface to the user through its own area onto the workstation display.
  • the overall result is an increase in user productivity since the user can manage more than one task at a time with multiple windows.
  • each process associated with a window views the workstation resources as if it were the sole owner.
  • resources such as the processing unit, memory, peripherals and graphics hardware must be shared between these processes in a manner which prevents interprocess conflicts on the workstation.
  • Graphics workstations generally utilize graphics "pipelines" which interconnect the various components of the system.
  • a graphics pipeline is a series of data processing elements which communicate graphics commands through the graphics system.
  • Today, graphics pipelines and window systems are evolving to support multitasking workstations.
  • the typical graphics pipeline interconnects a "host” processor to the graphics system which provides the various graphics commands available to the system and which also interface with the user.
  • the host processor is interfaced through the graphics pipeline to a "transform engine” which generally comprises a number of parallel floating point processors.
  • the transform engine performs a multitude of system tasks including context management, matrix transformation calculations, light modeling and radiosity computations, and control of vector and polygon rendering hardware.
  • a "graphics primitive” is a basic component of a graphics picture such as, for example, a polygon or vector. All graphics pictures are formed from combinations of these graphics primitives.
  • Many schemes may be utilized to perform graphics primitives rendering.
  • One such scheme is the "spline tessellation" scheme utilized in the TURBO SRX graphics systems provided by the Hewlett-Packard Company Graphics Technology Division, Fort Collins, Colorado. Regardless of the type of graphics rendering scheme utilized by the graphics workstation, the transform engine is essential in managing graphics rendering.
  • a graphics “frame buffer” is interfaced further down the pipeline from the host processor and transform engine in the graphics window system.
  • a “frame buffer” generally comprises a plurality of video random access memory (VRAM) computer chips which store information concerning pixel activation on the display corresponding to the particular graphics primitives which will be rendered to the screen.
  • VRAM video random access memory
  • the frame buffer contains all of the data graphics information which will be written onto the windows, and stores this information until the graphics system is prepared to render this information to the workstation's screen.
  • the frame buffer is generally dynamic and is periodically refreshed until the information stored on it is rendered to the screen.
  • the host and frame buffer have associated bandwidths. The bandwidth is a measure of the rate of data flow over a data path.
  • a graphics context consists of the current set of attributes, matrix stack, light sources, shading control, spline basis matrices, and other hardware state information.
  • Previous graphics systems were generally only able to support a single graphics context at a time and required the host's software to perform all of the context switching.
  • software context switching requires the host to store the context for each active process in virtual memory, write the context to the device when the process is active, and read the context back in the system. This process is extremely time consuming and inefficient, and does not adequately support high level graphics operations in the graphics system.
  • a latch in front of each pipe stage acts as a one-deep FIFO to store the data being sent from the previous stage when the current stage is not ready to receive it.
  • a register is added to each stage to latch the current hold signal, sent from a following stage, before it is sent to the previous stage.
  • the hold signal of one stage causes a hold signal to be generated by the next previous stage as the process of latching the data and transmitting the hold signals continues up the pipeline.
  • window operations which theoretically should be interactive with the user oftentimes force the user to wait while graphics primitives are being rendered.
  • graphics pipelines and graphics workstations are evolving to support more complex primitives and longer pipelines, pipeline latency and pipeline flushing now present prohibitive problems in the ongoing effort to increasing pipeline throughput and efficiency.
  • the invention consists in a computer system as claimed in Claim 1 and a method as claimed in Claim 5.
  • Figure 1 is a block diagram of a window graphics system utilizing a graphics pipeline and a graphics pipeline bypass.
  • Figure 2 is a block diagram of a window graphics system utilizing a graphics pipeline, a graphics pipeline bypass, a marker register and a stopmarker register.
  • Figure 3 is a flow chart of a method provided in accordance with this invention utilizing marker registers and stopmarker registers.
  • Figure 4 is a block diagram of a window graphics system wherein window relative addressing is performed.
  • Figure 5 is a flow chart of a method provided in accordance with this invention for window relative addressing and implementing virtual windows.
  • Figure 6 is a block diagram of a window graphics system utilizing a graphics pipeline and a graphics pipeline bypass for moving block data through the graphics pipeline bypass to a frame buffer.
  • Figure 7 is a flow chart of a method provided in accordance with this invention for moving block data and rendering the block data on a frame buffer according to frame buffer relative addresses.
  • Figure 8 is a block diagram of a graphics window system for transferring large data blocks from a host processor to a frame buffer through a burst block utilizing FIFO registers.
  • Figure 9A is a flow chart of a method provided in accordance with this invention for transferring large blocks of data along a pipeline bypass from a host processor to a burst block.
  • Figure 9B is a flow chart of a method provided in accordance with this invention for transferring data from a burst block to a pixel cache.
  • the inventors of the subject matter herein claimed and disclosed have solved the above mentioned long-felt needs in the art by implementing a graphics window system using a graphics pipeline having a separate path for commands and data which do not require traverse through the graphics pipeline.
  • This separate path is herein defined as a "pipeline bypass bus" and provides data commands and blocks direct access to the frame buffer without passing through the pipeline bus.
  • the pipeline bypass bus supports block moves, block reads and write operations, as well as other data transfer functions in hardware rather than software.
  • the pipeline bypass bus also provides fast access to the frame buffer for comparatively simple commands originating from the host processor. Furthermore, the pipeline bypass bus reduces graphics pipeline overhead and provides services required by the window system which would otherwise have to be processed through the pipeline bus. While the pipeline bus offers high performance rendering, the pipeline bypass bus offers fast block operations and direct frame buffer access to data output by the host processor.
  • a graphics system is comprised of a host processor 20 which is interfaced 30 to a transform engine 40.
  • the pipeline 50 interfaces the host processor 20 and transform engine 40 with rendering circuit 60.
  • the pipeline 50 is a graphics processor which performs a variety of tasks in the graphics window system. These tasks include bussing data through the graphics system and processing the graphics commands through various hardware blocks and software functions.
  • the terms pipeline, pipeline bus, and pipeline processor are used interchangeably throughout to denote the graphics pipeline processor.
  • Window circuitry 65 in preferred embodiments comprises graphics hardware provided in accordance with this invention for rendering graphics primitives on windows to frame buffer 70. Window circuitry in interfaced with frame buffer 70 and rendering circuitry 60.
  • graphics primitives are output from host processor 20 and manipulated by transform engine 40 through graphics pipeline 50 for rendering to frame buffer 70.
  • rendering circuit 60 After rendering circuit 60 renders a window with a particular context through window circuitry 65 on frame buffer 70, the window is output on raster display 80.
  • a pipeline bypass bus 90 is interfaced 30 to host processor 20 and frame buffer 70.
  • Pipeline bypass bus 90 provides a separate path for data from host processor 20 to frame buffer 70. Thus, when data passes through pipeline bypass bus 90 to frame buffer 70, no overhead time through the graphics pipeline is incurred.
  • Pipeline bypass bus 90 offers fast block transfer operations and direct frame buffer access for data output from host processor 20.
  • hardware solutions which eliminate the need for pipeline flushing and which reduce pipeline latency, thereby increasing window acceleration through the system are provided in accordance with this invention.
  • hardware implementations allow storage of multiple graphics contexts on the graphics system.
  • windows in the graphics system may be viewed as "virtual" devices.
  • a virtual device operates according to window relative addresses through the graphics pipeline independent of addresses corresponding to the frame buffer or raster display. Since windows and window context switching may thus be rendered according to window relative addresses, the need for pipeline flushing is eliminated and pipeline latency is significantly reduced.
  • each window in the window system can view the graphics pipeline as an exclusive resource since time consuming manipulations of windows which increase pipeline latency are eliminated. Therefore, methods and apparatus provided in accordance with this invention solve a long-felt need in the art for graphics systems which support multiple window contexts and eliminate the need for pipeline flushing.
  • host processor 20 is interfaced along pipeline 50 with rendering circuit 60.
  • rendering circuit 60 Interposed between rendering circuit 60 and frame buffer 70 is a marker register 100.
  • the pipeline marker register 100 is accessed by the host processor 20 through the pipeline bus 50 without affecting data flowing through the pipeline. Marker register 100 prevents unnecessary pipeline flushing when it is desired to change a window context.
  • a window context change often requires swapping of system resources such as, for example, window clipping planes or window display mode planes. Furthermore, these system resources oftentimes must be swapped during the context switch because they are a limited resource and are shared between multiple processes. Marker register 100 provides a preferred resource for switching contexts when compared with previous software solutions which might tend to reduce the need for pipeline flushing, but do not --and cannot-- eliminate it.
  • marker register 100 keeps track of currently active contexts which traverse the graphics pipeline 50 from host processor 20.
  • a "marker" is sent down the pipeline 50 from host processor 20 between each context switch.
  • the marker register is incremented each time a context traverses the pipeline such that a table of contexts currently in the pipeline is maintained by the system in marker register 100.
  • the table shows the context number, the window clipping planes, window identification, and marker numbers for each active context in the pipeline.
  • pipeline marker register 100 is automatically updated each time a marker reaches the end of pipeline bus 50.
  • stopmarker register 110 is interfaced on the pipeline bypass bus 90 between host processor 20 and frame buffer 70.
  • stopmarker register 110 is set with a particular value according to the particular application specified by host processor 20 and the user.
  • the window system can read the value of marker register 100 and compare this value with the predetermined value in stopmarker register 110 to determine which contexts are still in the pipeline. If the marker register value equals the stopmarker register value, the window system will wait until the current context has been processed by the system and rendered to frame buffer 70. If the stopmarker register value is not equal to the marker register value, the context being swapped is not in the pipeline and the context switch and clipping plane changes can occur immediately. Therefore, under no circumstances will it be necessary to halt data flow in the pipeline or prevent the host processor from continuing to place commands and data onto the pipeline. Thus, the need for pipeline flushing is eliminated.
  • FIG. 3 a flow chart of a preferred embodiment of a method implementing the marker/stopmarker system of Figure 2 is illustrated.
  • the system initiates a stopmarker register through the pipeline bypass at step 120. It is then desired to "unplug" the pipeline at step 125.
  • the system initiates a marker register through the pipeline at step 130 and sends data command segments through the pipeline at step 135.
  • the host processor interrogates the system at step 140 to determine if the pipeline is "plugged.”
  • the term "plugged” used herein means that data and graphics commands do not flow through the pipeline. If the pipeline is plugged, then the system performs the task for which the stop or plug was desired at step 150. The system then initiates the next stopmarker through the pipeline bypass at step 155 and unplugs the pipeline at step 160.
  • step 145 the system asks if the pipeline is filled at step 145. If the pipeline is filled, then the system returns to step 140. However, if the pipeline is not filled, then the system returns to step 125 where it unplugs the pipeline.
  • the host processor interrogates the system to determine at step 165 if the marker register value is equal to the stopmarker register value. If the stopmarker register value is equal to the marker register value, then the system stops pixel data flow to the frame buffer or "plugs" the pipeline at step 170. The host processor then interrogates the system to determine whether the pipeline has been unplugged at step 175. If the pipeline has not been unplugged, then the system waits.
  • the host processor interrogates the system at step 165 again to determine if the marker value is equal to the stopmarker value. If the stopmarker value is not equal to the marker value, then the host processor outputs a command at step 180 which allows the pixel cache to write data to the frame buffer.
  • the host processor plugs the pipeline at step 170 at which time the host processor interrogates the system to determine whether the pipeline is plugged at step 140.
  • the need to flush the pipeline has been eliminated since plugging of the pipeline need only occur between the pixel cache and the frame buffer for relatively short periods of time while complex processing and matrix transformation occurs earlier in the pipeline.
  • This advantageous result is achieved since the marker and stopmarker registers tell the graphics system when the pixel data flow to the frame buffer must wait since a particular context has not yet been rendered to the frame buffer.
  • Context switching utilizing the marker and stopmarker hardware provided in accordance with this invention thus eliminates the need for pipeline flushing since the graphics pipeline need never be emptied of data in order to determine whether a current context has been rendered to the frame buffer. In this fashion, extremely fast and efficient context switching can be accomplished, thereby significantly improving overall graphics system performance.
  • the marker register and stopmarker register hardware provided in accordance with this invention satisfies a long-felt need in the art for context switching in graphics systems utilizing a pipeline bus and pipeline bypass bus.
  • any graphics application will run faster when it views itself as the sole owner of the graphics system. This is a consequence of the fact that when a graphics application requests a window, the corresponding frame buffer memory is allocated to that application for graphics output.
  • an ideal environment for graphics rendering would allow each graphics process to treat the window as a "stand alone" or virtual graphics device.
  • the window origin is a reference for the graphics primitives which are rendered to the window.
  • Translation to screen relative or "frame buffer relative addresses” occurs after scan conversion according to window relative addresses and before frame buffer access.
  • the application treats the window as a full screen "virtual" device since the graphics system renders primitives as if the window comprises the entire frame buffer.
  • Operations of this nature may be performed by a transformation matrix.
  • the pipeline must be flushed every time the window is moved or changed. After flushing the pipeline, the new window offset may then be added to the transformation matrix and the pipeline must be filled up again.
  • a more preferred solution is to allow the application to access the window as if it owned the entire screen or frame buffer, then provide hardware to receive window offset data corresponding to frame buffer relative addresses so that the window containing the graphics primitives can be rendered to the frame buffer according to frame buffer relative addresses.
  • rendering circuit 60 comprises a transform engine 210 and a scan converter 220.
  • the scan converter is a raster scan converter.
  • Pixel cache 230 is further interfaced with frame buffer 70.
  • video random access memory VRAM 240 comprises the addressable frame buffer for the system.
  • An address manipulator 250 is interfaced on pipeline bypass bus 90. Address manipulator 250 is interposed along pipeline bypass bus 90 between host processor 20 and frame buffer 70.
  • address manipulator 250 comprises data registers for receiving offset addresses for each window from host processor 20 window relative conversion circuitry, and data register for storing window identification.
  • the window offsets are applied to each window by address manipulator 250 before the windows containing graphics primitives are rendered to frame buffer 70. Since the window offsets are written to address manipulator 250 through pipeline bypass bus 90, they may be updated asynchronously. The windows can thus be moved or shuffled on the frame buffer through pipeline bypass 90 simultaneously as window relative rendering of graphics primitives occurs at scan converter 220 through pipeline bus 50. Graphics applications and processes may therefore run on graphics pipeline bus 50 without explicit knowledge of their eventual window location on the frame buffer. Thus, windows in graphic systems provided in accordance with this invention truly function as virtual devices since they are able to view the graphics pipeline as an exclusive resource during window relative rendering operations.
  • pixel cache 230 is interfaced with address manipulator through a central bus 240.
  • the pixel cache 230 contains window relative addresses 245 of graphics primitives which have been rendered on the window with respect to the window origin. Since window offset data is written to address manipulator 250 through pipeline bypass bus 90, the pixel cache 230 interfaces 245 with address manipulator 250 to provide the window relative data which will be combined with the window offset addresses in the address manipulator.
  • Address manipulator 250 is also interfaced with frame buffer 70 so that the graphics windows can be rendered to the frame buffer according to frame buffer relative addresses 255.
  • a flow chart to accomplish window relative rendering in window graphics systems provided in accordance with this invention is shown in Figure 5.
  • a window manager the pipeline processes an application through the pipeline.
  • the application requests a window ID at step 260.
  • the window manager determines whether a new window ID has been requested at step 265. If a new window ID has not been requested, then the window manager determines whether a window move has been requested at step 270. If a window move has not been requested, then the process returns to step 265. However, if a window move is requested, then the window manager plugs the pipeline at step 275.
  • the window manager then calculates a new window location and moves the window at step 280. Furthermore, the window manager writes the window offset to the address manipulator at step 285 and unplugs the pipeline at step 290. The process then returns to step 265 to determine whether a new window ID has been requested. Since a new window ID has not been requested at this point, the window manager assigns a window ID at step 295 and plugs the pipeline at step 300.
  • the host processor then interrogates the system at step 305 to determine whether the new window ID has been received. If the new window ID has not been received, then the system waits until the window manager sends a new window ID However, if a new window ID has been received, the host processor sends the application which comprises data or command segments to the assigned window ID through the pipeline at step 310. The host processor then determines whether the application is finished at step 315. If the application is not finished, then the host processor sends additional data or command segments through the pipeline at step 310. However, if the application is finished, then the window can be said to have been rendered and the window manager will have moved the window to its new location at step 280. The process then stops at 320 until another window traverses the pipeline.
  • Window relative rendering accomplished methods illustrated in Figure 5 eliminates the need for pipeline flushing.
  • the window manager independently applies window offset addresses to window relative data while the pipeline can simultaneously process windows according to window relative addresses. This has not been heretofore achieved in the art and significantly increases the speed and timeliness of rendering of graphics primitives to the frame buffer.
  • Graphics window systems must support block move operations in order to maximize the system's performance.
  • block move operations generally support basic window primitives including raster texts and icons.
  • Other types of graphics block moves such as shuffles and block "resizes" must also take advantage of the system's block moving capabilities.
  • a "block” may be considered an entire window or merely part of a window comprising a set graphics primitives on the graphics system.
  • Block moves are particularly difficult to handle in a window environment because window offset addresses need to be included in these operations which are typically implemented as screen address relative.
  • block move operations inside a window must be window relative so that forcing all block moves in the graphics system to be window relative is neither an adequate nor versatile solution.
  • the reason that block move operations inside a window must be window relative is that many objects, for example fonts, are stored in off screen memory on the frame buffer and thus these objects are identified exclusively according to frame buffer relative addresses.
  • implementation of a graphics block mover in hardware allows the graphics system to handle several different kinds of block moving operations.
  • implementation of the block mover in hardware includes a register having the ability to store a bit for each operand output from the host processor that specifies whether the operand is window address relative or screen address relative.
  • Block moves accomplished by methods and systems provided in accordance with this invention can thus be window relative, screen relative, or any combination thereof.
  • Window systems provided in accordance with this invention may include block moving hardware which supplies window offsets through a pipeline bypass bus for windows having graphics primitives rendered thereon according to window relative addresses.
  • block moves initiated in accordance with this invention write the block's source and destination addresses, the block's width and height, and a particular replacement rule to the address manipulator through the pipeline bypass bus prior to initiation of the block move.
  • block moving hardware does not require the window to make decisions about its particular coordinate system as it traverses the graphics pipeline. This eliminates the need for the window system to incur additional processor overhead while manipulating graphics primitives according to frame relative addresses which would necessarily occur in parallel with processing the application or context.
  • a block if a block is off screen in the work area of the frame buffer it may automatically be assumed to be screen relative. However, if the block is displayed in the active screen area of the frame buffer, it may be assumed to be addressed window relative.
  • window relative rendering circuit 330 generally comprises raster scanning means and pixel cache buffer means as exemplified in the earlier figures. Window relative rendering circuit 330 renders graphics primitives to the window according to window relative addresses.
  • Window relative rendering circuit 330 is further interfaced with frame buffer 70.
  • frame buffer 70 is a VRAM.
  • Frame buffer 70 may be conceptually broken into two parts.
  • the first part 340 corresponds to screen addresses, i.e., places on the video screen where graphics primitives will actually be displayed.
  • the second portion of the frame buffer 350 corresponds to an "off screen" work area.
  • the off screen work area 350 is an area where windows or blocks which have not been rendered on the video screen of the graphics system exist exclusively according to frame buffer relative addresses. Blocks which appear on the first portion of the frame buffer 340 may be addressed relative to the screen in frame buffer relative addresses or window relative addresses as they are processed through the pipeline.
  • a source block 360 may be moved from the work area 350 to destination window or block 370 in the first portion 340 of frame buffer 70. It will be recognized by those with skill in the art that the source and destination addresses could be interchanged such that blocks can be moved window relative, screen relative or any combination thereof.
  • host processor 20 In order to move blocks between a destination and a source, host processor 20 outputs window offset information over pipeline bypass bus 90 to a variety of data registers which comprise address manipulator 250.
  • Destination register 380 is adapted to store the destination address of the block output by host processor 20.
  • Source address register 390 is adapted to receive the block's source address over the pipeline bypass 90 output by host processor 20.
  • the block size comprises the block's width and height so that the block may be correctly written to the appropriate destination in the frame buffer.
  • the specifier register 410 is adapted to receive data from host processor 20 through pipeline bypass bus 90 which specifics whether the block to be moved is currently window address relative or frame buffer address relative. In still further preferred embodiments, a single bit of the operand received from host processor 20 and stored in specifier register 410 specifies whether the block is window or screen relative. Thus, with methods and apparatus provided in accordance with this invention, blocks may be moved which are window address relative or screen address relative, and between sources and destinations which are window relative addressed or frame buffer relative addressed.
  • the source addresses and destination addresses may be specified either according to window relative addresses or frame buffer relative addresses and blocks may be concomitantly moved between sources and destinations addresses either within windows, or in and around the frame buffer.
  • a block is rendered through a graphics pipeline according to window relative addresses at step 420.
  • the block's source addresses are written through the pipeline bypass to the source address register at step 430.
  • the block's destination addresses are written to the destination address register through the pipeline bypass bus at step 440. It is desired to write the block's size to the block size register through the pipeline bypass bus at step 450.
  • the host processor interrogates a specifier register at step 460 to determine whether a destination block has been addressed according to window relative addresses or frame buffer relative addresses. Similarly, the host processor interrogates a specifier register at step 465 to determine whether a source block has been addressed according to window relative or frame buffer relative addresses. If the blocks have been addressed according to frame buffer relative addresses a "zero" window offset is applied at step 470 which effectively does not change the block addresses since the block is considered to be frame buffer relative addressed.
  • the window offset addresses are applied to the block at step 480 so that the blocks are correctly addressed according to frame buffer relative addresses before the blocks are rendered to the destination on the system frame buffer or screen.
  • the blocks may be rendered to their destinations on the frame buffer at step 490.
  • the block window offset addresses are written to the address manipulator through the pipeline bypass bus rather than through the graphics pipeline bus. Therefore, the graphics pipeline is not used to address the block relative to the frame buffer and thus is free to perform graphics primitive renderings to blocks and windows entirely according to window relative addresses.
  • Methods and systems provided in accordance with this invention reduce pipeline latency since each window is in effect treated as a virtual device in the system. Furthermore, methods and apparatus provided in accordance with this invention solve a long-felt need in the art for graphics pipelines that eliminate the need for pipeline flushing since the time consuming task of adding window offsets to window relative addressed blocks and obtaining frame buffer relative addressed blocks is eliminated. This goal is accomplished by implementing a graphics pipeline bus having hardware adapted to perform these tasks.
  • "burst" data hardware block 500 is provided in accordance with this invention interfaced in pipeline bypass bus 90 and interposed between host processor 20 and pixel cache 230.
  • the data block 500 is denoted a "burst” data block since host processor 20 can load data block 500 with extremely large blocks of data through pipeline bypass bus 90.
  • these large blocks of data may comprise graphics animation data which will be written to the frame buffer.
  • These large blocks of data are organized as multiple rows of pixels, called "scanlines.”
  • the data is organized in host processor memory as an array of data with the first datum being the leftmost pixel of the first scanline, then proceeding along the scanline to the rightmost pixel of the first scanline, and then back to the leftmost pixel of the second scanline, etc. This forms a two dimensional array of pixel data to be sent to the frame buffer.
  • the burst is comprised of a number of first-in, first-out (FIFO) registers shown at 510.
  • the FIFO's are organized in banks. There are from one to "n" banks of FIFO's. Each FIFO bank buffers pixels along the scanline. The number of pixels buffered along a scanline is dependent on the depth of the FIFO's. Multiple scanlines, equal to the number of FIFO banks, can be buffered.
  • the input port and output port of the FIFO's operate independently. Data is transferred from the host processor 20 to the FIFO input ports independently and in parallel with data transferred from the FIFO output ports to the pixel cache 230.
  • the banks are connected in parallel as seen from the pipeline bypass bus 90.
  • the host processor 20 writes data to the input port of one of the FIFO banks from one scanline of data until that FIFO bank is full.
  • the host processor then writes data to the input port of the next FIFO bank from the next scanline of data.
  • the graphics pipeline 50 is then plugged, and pixel data transfer from the graphics pipeline 50 into the frame buffer 70 is suspended while the data transfer from burst 500 is active. Since burst 500 is interfaced with the pixel cache 230 through the pipeline bypass bus 90, the need to flush the graphics pipeline is eliminated.
  • a way to clip data from the left and right edges is provided.
  • Two additional offset operands from the host processor are written to the address manipulator 230.
  • the offsets specify the number of pixels along a scanline from the beginning of the scanline to the right edge and the left edge of the desired sub-block of data. These offsets instruct the address manipulator to clip the data transferred from the FIFO's 510 to the pixel cache 230; that is to the right, or to the left of the desired sub-block of data.
  • burst 500 is comprised of a number of first-in, first-out (FIFO) registers, shown generally at 510.
  • the FIFO's 510 are connected in parallel with each other in the burst block 500.
  • FIFO's 510 are interfaced with the pipeline bypass bus 90 so that host processor 20 can move large data blocks in parallel to each of the FIFO's 510.
  • the amount of data bussed from host processor 20 to burst 500 is only limited by the number of FIFO's which are connected in parallel in the burst block.
  • Burst 500 is interfaced with pixel cache 230 so that it may transfer the data in FIFO's 510 to pixel cache 230 after host processor 20 has written the desired data to FIFO's 510.
  • Pixel cache 230 is interfaced with VRAM 70 to allow data in burst 500 to be rendered to the frame buffer. Since burst 500 is interfaced with the pixel cache through pipeline bypass bus 90, the graphics pipeline 50 is free to perform window relative rendering of other graphics primitives output from host processor 20. Therefore, use of burst 500 interfaced with graphics pipeline bypass bus 90 reduces graphics pipeline latency and eliminates the need to flush the pipeline 50 when a context switch for the data in burst 500 is desired.
  • address manipulator 250 is provided interfaced on the pipeline bypass bus 90 interposed between host processor 20 and VRAM 70.
  • the address manipulator functions as described above and renders the data in burst 500 according to frame buffer relative addresses on the VRAM 70. It is necessary to utilize address manipulator 250 since the data written to FIFO's 510 in burst 500 from host processor 20 may appear in window relative addresses.
  • host processor 20 writes window offset addresses for the data in FIFO's 510 to a data register in the address manipulator so that address manipulator 250 may render the data in FIFO's 510 according to frame buffer relative addresses on VRAM 70.
  • Address manipulator 250 also aligns data written in the FIFO's 510 on the frame buffer. Alignment is accomplished by an additional offset operand from the host processor 20 written to the address manipulator 250 which instructs the address manipulator to clip data in FIFO's 510 which will be input to pixel cache 230 and which falls outside of the specified block on frame buffer 240 when the data is rendered. In preferred embodiments, clipping is necessary since block data output from burst 500 is potentially large enough to fall outside the particular destination addresses on the frame buffer.
  • FIG. 9A a flow chart of a preferred embodiment of transfer of large data blocks from a host processor to a burst block is shown.
  • the block destination addresses are written through the pipeline bypass to the address manipulator at step 520.
  • the block size is written through the pipeline bypass bus from the host processor to the address manipulator at step 530. It is then desired to write left edge and right edge offsets through the pipeline bypass to the address manipulator at step 540.
  • Left edge and right edge offsets are then written through the pipeline bypass bus to the address manipulator at step 540.
  • the host processor interrogates the FIFO's to determine whether there is room in the FIFO's. If there is not room in the FIFO's, then the process must wait. However, if there is room in the FIFO's, the host processor asks if there is data to be transferred at step 560. If there is not data to be transferred, the process stops. However, if there is data to be transferred, then individual datum are transferred at step 570. In this fashion data from the host processor may be transferred to the burst block.
  • FIG. 9B a preferred embodiment of a flow chart for transferring data from a burst block to a pixel cache is shown.
  • the host processor interrogates the burst block at step 580 to determine if there is data available in all of the FIFO's. If data is not available from all of the FIFO's, then the process must wait. However, if data is available from all of the FIFO's, then individual transfers of datum from the burst block to the pixel cache at step 590 is accomplished.
  • the host processor then interrogates the system at step 600 to determine if all the data has been transferred. If all data transfer has occurred, then the process stops.
  • burst transfer operations provided in accordance with this invention satisfy a long-felt need in the art for window systems having the ability to move a large amount of pixel data to around the system in an efficient manner.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)

Claims (10)

  1. Système d'ordinateur pour supprimer le besoin d'une purge de pipeline en interrompant le flux de données entre un circuit de rendu (60) et un tampon de trame (70), ledit système d'ordinateur comprenant un sous-système graphique ayant un tampon de trame et un pipeline (50), dans lequel ledit tampon de trame et ledit circuit de rendu sont connectés audit pipeline, ledit dispositif comprenant:
    un registre de marqueur (100), connecté dans ledit pipeline entre ledit circuit de rendu et ledit tampon de trame, pour suivre l'avancement des contextes graphiques multiples qui traversent le pipeline, en suivant l'avancement de marqueurs traversant ledit pipeline;
    un hôte (20) connecté audit pipeline, pour générer (i) des primitives graphiques, (ii) générer des contextes graphiques et (iii) générer des marqueurs, lesdits primitives graphiques, contextes et marqueurs étant fournis audit pipeline, dans lequel un marqueur est fourni entre chaque contexte graphique; pour interroger ledit registre de marqueur; et pour interrompre le flux de données à travers ledit pipeline vers ledit tampon de trame, en réponse au suivi des contextes multiples par l'interrogation dudit registre de marqueur par ledit hôte; et
    un contournement de pipeline (90), connectant ledit hôte audit tampon de trame, et un registre de marqueur d'arrêt (110) interfacé avec le contournement de pipeline, pour stocker une valeur prédéterminée, la valeur étant utilisée pour déterminer lesquels des contextes multiples se trouvent dans le pipeline.
  2. Système selon la revendication 1, dans lequel le registre de marqueur contient une valeur de marqueur entre chaque commutation de contexte, et l'hôte interrompt le flux de données lorsque la valeur du marqueur d'arrêt est égale à la valeur du marqueur.
  3. Système selon la revendication 1, dans lequel le registre de marqueur d'arrêt est initialisé à travers le contournement de pipeline, entre l'hôte et le tampon de trame.
  4. Système selon la revendication 1, dans lequel le registre de marqueur est automatiquement mis à jour par un marqueur envoyé sur le pipeline, entre l'hôte et le tampon de trame.
  5. Procédé pour suivre l'avancement de données ou commandes dans un système graphique d'ordinateur ayant un pipeline et un tampon de trame, afin de supprimer la purge du pipeline, ledit procédé comprenant les étapes de:
    génération de données ou commandes et fourniture desdites données ou commandes audit pipeline;
    génération de marqueurs, dans lequel chacun desdits marqueurs a une valeur de marqueur, et fourniture desdits marqueurs audit pipeline, de façon qu'un marqueur soit fourni entre chacune desdites données ou commandes, dans lequel lesdits marqueurs traversent ledit pipeline;
    détermination d'une valeur de marqueur d'arrêt;
    surveillance dudit pipeline en un point prédéterminé dans ledit pipeline, en notant lesdites valeurs de marqueur pendant que lesdits marqueurs traversent ledit pipeline;
    en déterminant si un marqueur ayant une valeur égale à ladite valeur de marqueur d'arrêt est passé par ledit point prédéterminé, en interrogeant lesdites valeurs de marqueur notées; et
    en interrompant le flux de données à travers ledit pipeline vers ledit tampon de trame, en réponse à l'interrogation desdites valeurs de marqueur notées.
  6. Procédé selon la revendication 5, et pour surveiller les données ou commandes, comprenant en outre les étapes de:
    positionnement d'un registre de marqueur dans ledit pipeline audit point prédéterminé;
    enregistrement dans ledit registre de marqueur de la valeur des marqueurs passant par ledit registre de marqueur;
    vérification du registre de marqueur audit point prédéterminé; et
    interruption des données ou commandes dans le tampon de trame, lorsque la valeur stockée dans ledit registre de marqueur est égale à ladite valeur de marqueur d'arrêt.
  7. Procédé selon la revendication 6, dans lequel l'étape de génération de marqueurs comprend l'étape:
       d'incrémentation de la valeur de marqueur d'une valeur prédéterminée, au moment où chaque marqueur est généré.
  8. Procédé selon la revendication 7, dans lequel le système de pipeline est utilisé dans un système graphique à fenêtres.
  9. Procédé selon la revendication 5, dans lequel ladite valeur de marqueur d'arrêt est stockée dans un registre de marqueur d'arrêt.
  10. Procédé selon la revendication 9, dans lequel les données ou les commandes sont des contextes graphiques.
EP19900308257 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques Expired - Lifetime EP0410783B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP94201810A EP0617402B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques
EP94201808A EP0617400B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans de systèmes graphiques
EP94201809A EP0617401A3 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques.

Applications Claiming Priority (2)

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US38751089A 1989-07-28 1989-07-28
US387510 1995-02-13

Related Child Applications (5)

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EP94201809.4 Division-Into 1990-07-27
EP94201808A Division EP0617400B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans de systèmes graphiques
EP94201808.6 Division-Into 1990-07-27
EP94201810.2 Division-Into 1990-07-27
EP94201810A Division EP0617402B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques

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EP0410783A2 EP0410783A2 (fr) 1991-01-30
EP0410783A3 EP0410783A3 (en) 1991-07-10
EP0410783B1 true EP0410783B1 (fr) 1996-08-28

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EP19900308257 Expired - Lifetime EP0410783B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques
EP94201810A Expired - Lifetime EP0617402B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques
EP94201809A Withdrawn EP0617401A3 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques.
EP94201808A Expired - Lifetime EP0617400B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans de systèmes graphiques

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EP94201810A Expired - Lifetime EP0617402B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques
EP94201809A Withdrawn EP0617401A3 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans des systèmes graphiques.
EP94201808A Expired - Lifetime EP0617400B1 (fr) 1989-07-28 1990-07-27 Méthode et dispositif pour l'accélération de fenêtres dans de systèmes graphiques

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DE4405330A1 (de) * 1994-02-21 1995-08-24 Vobis Microcomputer Ag Verfahren zum Scrollen von mehreren Rasterzeilen in einem Fenster eines Grafikmodus betriebenen Bildschirms eines Personalcomputers
KR20080031595A (ko) * 2006-10-04 2008-04-10 삼성전자주식회사 오프스크린 버퍼링 관리 장치 및 방법
US20160104263A1 (en) * 2014-10-09 2016-04-14 Media Tek Inc. Method And Apparatus Of Latency Profiling Mechanism

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FR2582132B1 (fr) * 1985-05-15 1987-07-17 O Donnell Ciaran Circuit de memoire d'image virtuelle permettant le multifenetrage
US4811245A (en) * 1985-12-19 1989-03-07 General Electric Company Method of edge smoothing for a computer image generation system
US4829294A (en) * 1986-06-25 1989-05-09 Hitachi, Ltd. Document processing method and system using multiwindow
US4823286A (en) * 1987-02-12 1989-04-18 International Business Machines Corporation Pixel data path for high performance raster displays with all-point-addressable frame buffers
GB2203317B (en) * 1987-04-02 1991-04-03 Ibm Display system
US4903218A (en) * 1987-08-13 1990-02-20 Digital Equipment Corporation Console emulation for a graphics workstation
US4814884A (en) * 1987-10-21 1989-03-21 The United States Of America As Represented By The Secretary Of The Air Force Window generator
JPH0727571B2 (ja) * 1987-10-26 1995-03-29 テクトロニックス・インコーポレイテッド ラスタ走査表示装置及び図形データ転送方法

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Publication number Publication date
DE69033158D1 (de) 1999-07-15
EP0617400A3 (fr) 1995-04-26
EP0617400B1 (fr) 1999-09-08
EP0617402B1 (fr) 1999-06-09
EP0617402A3 (fr) 1995-04-26
EP0617402A2 (fr) 1994-09-28
DE69033158T2 (de) 1999-10-14
DE69033283D1 (de) 1999-10-14
EP0617401A2 (fr) 1994-09-28
DE69033283T2 (de) 1999-12-30
EP0617400A2 (fr) 1994-09-28
EP0617401A3 (fr) 1995-04-26
DE69028259T2 (de) 1997-01-23
DE69028259D1 (de) 1996-10-02
EP0410783A2 (fr) 1991-01-30
EP0410783A3 (en) 1991-07-10

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