EP0407423B1

EP0407423B1 - System for transferring binary information

Info

Publication number: EP0407423B1
Application number: EP89903830A
Authority: EP
Inventors: Sten Lundgren
Original assignee: Lundgren & Nordstrand AB
Current assignee: Lundgren & Nordstrand AB
Priority date: 1988-03-14
Filing date: 1989-03-13
Publication date: 1994-06-01
Anticipated expiration: 2009-03-13
Also published as: ATE106644T1; EP0407423A1; SE8800896D0; DE68915759D1; WO1989008958A1; SE460751B; AU3298689A; SE8800896L; DE68915759T2; JP2766013B2; JPH03503469A

Abstract

In a system for transferring binary information between a plurality of transmitters (6) and receivers (5) connected to a common communication line (9, 9'; 17), each transmitter (6) and each receiver (5) are connected to the communication line via a coupling unit (11; 11') of their own. The coupling unit comprises a counting device (12, 13; 12', 13'), and the counting devices of the coupling units pertaining to a group of a transmitter and at least one receiver are adapted, after reception of a constantly unique number of pulses predetermined for that group, to couple the transmitter and the receiver(s) of that group to the communication line for transferring a binary information bit from the transmitter to the receiver(s) of the group. Furthermore, a clock device (10; 11, 11') is coupled to supply pulses to all counting devices for sequentially coupling the different transmitter and receiver groups to said communication line.

Description

The present invention relates to a system for transferring binary information between a plurality of transmitters and receivers connected to a common communication line.
The system is primarily intended to serve as a communication system for transferring on and off commands to different electrical components in a machine or different electrical units of an installation, but can also be used for a great many other applications where there is need of binary information transfer, and it should be emphasised that the system is not restricted to electrical transmitters of receivers, nor to an electrical communication line.
Prior art systems for transferring on and off commands in a machine usually operate with a central unit in the form of a computer which, via an address line and a data line, are connected to all of the transmitters and receivers of the machine. The transmitters may, for example, be switches, photoelectric cells and relays supplying information, on the basis of which the central unit shall supply commands to different receivers, for example relays, motors and solenoid valves.
For its proper functioning, such a machine requires on the one hand a control program for the central unit and, on the other hand, addressable units for connecting the transmitters and receivers to the address and the data lines, and this makes the prior art systems relatively slow and difficult to change.
DE-A-2 259 223 discloses a system for transferring binary information in the form of binary data pulses between a plurality of transmitters and receivers, which system comprises a single communication line, a plurality of separate communication groups each group consisting of one of said transmitters and one of said receivers, a coupling unit in each transmitter and in each receiver for connecting said transmitter and said receiver to said single communication line, a counting device in each coupling unit connected to said single communication line for receiving clock pulses therefrom, the coupling units pertaining to each one of said separate communication groups being adapted, after reception by the counting devices of a unique number of said clock pulses predetermined for that communication group, to connect said transmitter and said receiver of that communication group to said single communication line for transferring information from said one transmitter to said one receiver of that communication group.
This prior art system uses a central clock generator for generating time channel pulses and cycle pulses. When a time channel is opened by the clock generator, a transmitter and a receiver are connected to the communication line and information in the form of a plurality of pulses is transferred from the transmitter to the receiver. Therefore, this system is not well adapted for transferring on and off commands to different electrical components in a machine or different electrical units of an installation. Using the prior art system in such an application would result in an inefficient system, since only one data pulse would be transferred from the transmitter to the receiver in each time channel. The system of DE-A-2 259 223 further uses four different types of signals for transferring information, starting a new time channel and starting a new operating cycle. Therefore, said system is sensitive to noise. Also, the operation of the known system is not possible to be changed during an operation cycle, since there is no co-operation between the transmitters and the clock generator.
Therefore, it is the object of this invention to provide a system of the above-mentioned type, by which it is possible, without using a central unit, to establish systems that can operate at high speed and are easily changed even during operation, if required.
This object is achieved, in accordance with the invention, in that the information transferring system has the features stated in the characterising part of claim 1.
This system makes it possible to install the different components of a machine together with a single communication line and a current supply line before the machine function is finally specified. Also the coupling units can be installed and the final machine function established by programming of the coupling units. Further components can be added by supplementary wiring and suitable programming of additional coupling units and any existing coupling units.
The communication line can be branched in optional manner, such that e.g. looping will not be necessary.
Accordingly, the coupling units are thus generally designed and given their final function by programming. The clock device therefore is integrated into the coupling units, at least one coupling unit of each group being adapted, during transfer of a binary information bit, also to provide a clock pulse supplied to all counting devices.
To prevent the system according to the invention from stopping in the event of a fault in one coupling unit, at least one of the coupling units comprises a monitoring device which, in the absence of a clock pulse during a predetermined time interval greater than the normal time interval between clock pulses, supplies a clock pulse to the communication line, such that the defective coupling unit is skipped in the operating sequence of the system.
For easy and automatic starting of the system, at least one of the coupling units may comprise a resetting device supplying a resetting signal to all counting devices as soon as the main switch of the machine is switched on, i.e. when voltage occurs in the current supply line. Consequently, the system also will always begin operating in one and the same step of its operating sequence.
Since the system according to the invention is sequential, the operating sequence must be traversed over and over again. To this end, the coupling unit of the transmitter in the last group coupled in the sequence to the communication line comprises a resetting device which supplies a resetting signal to all counting devices via the communication line when that coupling unit couples the associated transmitter to the communication line.
When one of the transmitters of the system changes its state, the associated receiver will be supplied with a change command which can be delayed maximally by the time it takes to traverse the operating sequence. According to the invention, however, the reaction time for effecting a transmitter change can be reduced considerably if the coupling unit to a transmitter in a group requiring a very short reaction time, is provided with an interrupt device which, substantially immediately when the transmitter changes its state and independently of the position of the system in the operating sequence, produces a resetting signal supplied to all counting devices via the communication line. Normally, this group should be connected as early in the operating sequence as possible so that, when the associated transmitter changes its state, the accompanying change command will always be carried out within a fraction of the time it takes to traverse the entire operating sequence.
For handling composite conditions, i.e. generating a command in response to the state of several transmitters, use may be made, according to the invention, of a logical network, for example a combinatory network, which has a plurality of inputs, optionally has time delays, and has at least one output, and in which each output can be regarded as a transmitter and each input as a receiver which then must first receive its command before the composite condition can be formed.
In view hereof, the coupling units pertaining to the inputs of the combinatory network must be placed at an earlier stage in the operating sequence than the coupling units pertaining to the outputs of the combinatory network.
In a preferred embodiment of the system according to the invention, one coupling unit may be common to several transmitters and/or receivers which form several groups of transmitters and receivers. This is made possible by connecting a counting device which is common to the groups, to a decoder having a plurality of outputs. The different groups are distinguished by that decoder output which is activated.
If use is made of decoders having several ouputs, the system according to the invention is also capable of suplying, in a simple manner, a receiver with information representing a digital value consisting of several binary bits, in that one and the same output from the decoder is consecutively and in several steps of the sequence coupled to the communication line for successively receiving the binary bits.
By making the decoders programmable, the group affilation of transmitters and receivers can be changed, even during traversing of the operating sequence, in that the programming is controlled by the state of one or more transmitters. With programmable decoders, the operating sequence can also be made to traverse any one of several parallel branches in response to the state of one or more transmitters.
Furthermore, a decoder of the above type also makes it possible to connect the inputs/outputs of a computer to the communication line without complicated input/output circuits.
The invention will be described in more detail below, reference being had to accompanying drawings. Fig. 1 illustrates schematically an information transfer system according to prior art technique. Fig. 2 illustrates schematically an information transfer system according to the invention. Fig. 3 illustrates a simple embodiment of a coupling unit comprised by the system of the invention. Fig. 4 illustrates the signal waveforms appearing in Fig. 3. Fig. 5 illustrates a more complete embodiment of a coupling unit comprised by the system of the invention. Fig. 6 is a block diagram of a coupling unit for several groups of transmitters and receivers. Fig. 7 is a block diagram showing the connection of a computer to the system. Fig. 8 illustrates an alternative clock device.
The prior art control system as shown in Fig. 1 comprises a central unit 1 in the form of a computer from which an address line 2 and a data line 3 extend. A receiver 5 and a transmitter 6 are connectible to the data line 4 via connecting units 4, 4'. The connecting units 4, 4' are connected both to the address line 2 and to the data line 3 and comprise, more particularly, an address decoder 7, 7' and a gate 8, 8'. The address decoder 7, 7' also controls the state of the gate 8, 8'.
The transmitter 6 may be, for example, a switch, and the receiver 5 a solenoid valve.
The central unit 1 controls the on-off switching of the receiver 5 connected to the output of the gate 8 by transmitting the unique address of the address decoder 7 on the address line 2 and by transmitting, at the same time as the address decoder 7 opens the gate 8, a data signal on the data line 3. The data signal indicates whether on-switching or off-switching is to occur, and is supplied, via the gate 8, to the receiver 5.
The central unit 1 can thus control on-off switching of an optional number of electrical components or units connected, each via one connecting unit responding to a unique address, to the data line 3 and the address line 2.
Via the connecting unit 4', the central unit 1 can also draw information from the transmitter 6. The connecting unit 4' is similar to the connecting unit 4, but the communication direction through the gate 8' is opposite to the direction through the gate 8. The addresses of all address decoders 7, 7' are mutually different, such that the central unit 1 communicates only via one connecting unit 4, 4' at a time.
In another known embodiment, the data line 3 is divided into two lines, one of which serves to feed data from the central unit 1, while the other serves to transfer data into the central unit 1.
Further variants of the above-mentioned system are known, but they all require the use of a central unit for controlling and monitoring the operation.
The information transfer system of the present invention, which is schematically illustrated in Fig. 2, is, like the prior art system, intended for a plurality of receivers, of which only the receiver 5 is shown, and a plurality of transmitters, of which only the transmitter 6 is shown. Furthermore, it comprises a data line 9 and a clock line 9' on which clock pulses are supplied by a clock 10. The receiver 5 and the transmitter 6 are connectible to the data line 9 by means of a coupling unit 11 and 11', respectively, also connected to the clock line 9'. The coupling units 11, 11' include a counting device comprising a counter 12, 12' and a decoder 13, 13'. The counting devices control the state of a gate 14 and 14', respectively, by which the receiver 5 and the transmitter 6 can be connected to the data line 9.
In the system according to the invention, the decoders 13, 13' are set to detect one and the same unique address. This means that the gate 14 in the coupling unit 11 is opened at the same time as the gate 14' of the pertaining coupling unit 11', and an input signal from the transmitter 6 is transferred via the data line 9 to the receiver 5. The receiver 5 thus is switched on or off in response to the value of the input signal from the transmitter 6. It will be realised that the system according to the invention makes it possible to arrange a very large number of pairs of coupling units 11, 11' in optional positions along the data and clock lines 9, 9'. The coupling units of several receivers can have the same address so that one transmitter can control several receivers at the same time. In a special case, there need be no receiver for a transmitter. Furthermore, coupling units belonging together need not be positioned adjacent one another, but may be placed at optional distances from one another along the lines 9, 9'.
To make all counters 12, 12' start counting the clock pulses from the clock 10 at the same time, all counters must be simultaneously reset, which can be done via a separate reset line connected to the resetting inputs of all counters 12, 12' and supplying these inputs with a resetting pulse after the clock 10 has supplied a pulse train in which the number of pulses equals the number of addresses or groups of coupling units. In one embodiment of the system according to the invention, the communication line therefore comprises a data line (line 9), a clock line (line 9') and a reset line (not shown). However, in a preferred embodiment of the present invention, use is made of a single line for transferring clock pulses, data pulses and resetting signals, and in this case the clock 10 is preferably integrated in all coupling units, each data pulse being utilised also as a clock pulse, while the resetting signal is a specially shaped signal.
Thus, the information transfer system according to the invention operates sequentially in a number of successive steps, and in each step a group of coupling units having the same address are connected to one another for a short time interval via the communication line, whereupon the next group of coupling units in the same way connects the associated transmitters and receivers to the communication line etc.
One embodiment of the coupling units 11, 11' included in the system of the invention is shown in Fig. 3, and some of the signal waveforms occurring therein are shown in Fig. 3.
The coupling unit shown in Fig. 3 is switchable so that it can operate either as the coupling unit 11 or as the coupling unit 11' in Fig. 2. This is achieved by setting the logical value in a point 15 of the unit. A transmitter or a receiver is connectible in a connecting point 16 forming the output to a receiver, if the logical value in point 15 is set to equal "1", and the input from a transmitter if the logical value in the point 15 is set to equal "0".
The coupling unit transfers signals to a communication line 17 which is a single-wire conductor, via a transistor unit 8 with an output connected to the communication line 17 and two inputs connected to a line 19 and a line 20, respectively. Furthermore, the coupling unit receives information from the communication line 17 via an optocoupler unit 21 having an input connected to the communication line 17 and two outputs each connected to one line 22 and 23, respectively. The signals occurring on the communication line 17 are either positive pulses or negative pulses. A positive pulse on the communication line 17 results in a positive pulse on the line 23, while a negative pulse on the line 17 results in a positive pulse on the line 22. Inversely, a positive pulse on the line 19 will generate a negative pulse on the line 17, while a positive pulse on the line 20 generates a positive pulse on the line 17.
The pulses supplied from the line 17 are fed via the lines 22 and 23 on the one hand to the reset input 24 and the clock input 25 of the counter 12 and, on the other hand, to an input to an AND gate 26. In addition, the pulses on the line 23 are supplied to a data input 27 to a latch circuit 28. All pulses on the lines 22 and 23 are supplied to the clock input 25 of the counter 12, while the reset input 24 receives a pulse only when a pulse on the line 22 and a pulse on the line 23 occur with a short time interval determined by a time circuit 29. The time circuit 29 is, like the other time circuits of the coupling unit, a monostable flip-flop which is triggered on the downward flank of incoming trigger pulses and on its output supplies a positive pulse of predetermined length, said pulse being supplied to an input to an AND gate 30, the other input of which is supplied with the pulses, combined via an OR gate 31, on the lines 22 and 23.
The output of the decoder 13 is connected to the other input to the gate 26, the output of which is connected to the trigger input to a second time circuit 32. The time circuit 32 can be actuated by the output signal from the gate 26 if it is activated because the point 15 has been set to logical "0". The output of the decoder 13 is also connected to the read input to the latch circuit 26, the output of which is connected to the input to a NAND circuit 33. The other input to the gate 33 is connected to the point 15. The input of the gate 33 is connected to the base of a transistor 34, the collector of which is connected to the output/input 16. One input of an OR gate 35 is connected to the output from the time circuit 32, and the other input to the output from an AND gate 36, one input of which is connected to a RC circuit 37, the other input of which is connected to a programming point 38, the logical value of which decides whether or not the coupling unit pertains to the last step of the operating sequence.
The output of the gate 35 is connected to the trigger input to a third time circuit 37, the output of which is connected to the trigger input to a fourth time circuit 40 and to one input of each of two AND gates 41 and 42. The time circuit 40 is active or inactive depending upon the logical value in point 38. Its output is connected to one input to an OR gate 43, the output of which is connected to the line 19. The input/output 16 is also connected to the input to an inverter 44 and to the other input to the gate 42. The output of the inverter 44 is connected to the other input to the gate 41.
The mode of operation of the coupling unit as shown in Fig. 3 will now be described with reference to Fig. 4 and, at first, on the assumption that the logical value is "0" in point 15 and "1" in point 38. When the voltage in the system comprising the coupling unit is switched on, the RC circuit 37 generates a pulse which is supplied to the trigger input of the time circuit 39 via the gates 36 and 35. Since the level selected for point 38 in this case also requires that the input 16 is set at a high level ("1"), the output pulse from the time circuit 39 will be supplied via the gate 42 to the line 20, whereby a positive pulse is obtained on the communication line 17. Since the output pulse from the time circuit 39 is supplied to the trigger input to the time circuit 40, the output pulse from the time circuit 40 will be supplied to the line 19 via the gate 43 and thus cause a negative pulse on the communication line 17 immediately after the positive pulse. This pulse combination is utilised as a resetting signal in the system and is shown in Fig. 4 in the signal waveform I. The resetting signal will reset, in the manner described above, the counter 12 in all coupling units of the system.
Reference is now made to the coupling unit whose decoder 13 is set at the count 0 in the counter 12, and the circuit point 15 of which is "0", i.e. where the circuit point 16 is the input from a transmitter not shown. The signal on the output of the decoder 13 will thus have a high level (logical 1) during the interval from the resetting of the counter 12 until the next clock pulse is supplied to the counter, as illustrated by the waveform II in Fig. 4. The resetting pulse which is also supplied to the clock input 25 of the counter 12, but which is suppressed, occurs also on one input of the gate 26 and now also on the output of this gate. This output pulse which is shown as waveform III in Fig. 4, triggers the time circuit 32. The output signal from the time circuit 32 has the appearance shown as waveform IV in Fig. 1 and triggers the time circuit 39, whereby - if the level on the input 16 for example is high - the output pulse from the time circuit 39 is supplied via the gate 42 to the line 20 where a pulse having the waveform V in Fig. 4 appears. In this manner, a positive pulse is generated on the communication line 17, as shown by waveform I in Fig. 4.
This pulse is supplied to all counters 12 as a clock pulse, and in the coupling unit whose decoder is set at count 0 and whose circuit point 15 has the logical level 1 (i.e. where the circuit point 16 is the output to a receiver not shown), the downward flank of waveform II will read in the value of the signal waveform VI in the latch circuit 28, in this case "1". This means that the signal waveform VII in Fig. 4 will appear on the output of the latch circuit 28, the output of the gate 33 will be logical "0", and a high level will be generated on the output 16.
If, instead, the data and clock pulse fed to the communication line 17 had been a negative pulse, the output from the latch circuit 28 would have been set at the logical value "0", and thus the level of the output 16 would have been low.
By the supplied data and clock pulse, all counters 12 were set at count 1, for which reason the above operation is repeated for the coupling units whose decoders 13 are set at this count. The sequence continues in this fashion up to the coupling unit in whose point 38 the logical value is "1". This coupling unit will thus generate a resetting signal on the communication line 17 for resetting all counters 12 and repeating the operating cycle just traversed.
The more generally formed variant, illustrated in Fig. 5, of the coupling unit 11, 11' contains essentially the same components as the coupling unit according to Fig. 3 and, in addition, two further component blocks A and B. Where applicable, the same reference numerals have been used in Figs. 3 and 5. The block A primarily replaces the circuit point 38 in Fig. 3, but has also a starting function and a monitoring function. The block B enables interruption and restarting of the operating sequence before this has reached its normal end.
The RC circuit 37 in Fig. 5 is connected to the reset input to a bistable flip-flop 45, the set input of which is connected to the output from the gate 30. The Q output of the flip-flop 45 is connected to the input to an AND gate 46, the other input of which is connected to the output from the gate 31, and the output of which is connected to the clock input 25 of the counter 12. The Q output of the flip-flop 45 is connected to an input to an OR gate 47, the other input of which is connnected to the output from the gate 30, and the output of which is connected to the reset input of the counter 12 and, furthermore, to the reset input to a counter 48 in the block A. The RC circuit 37 is further connected to an inverter 49, the output of which is connected to an input to an AND gate 50, the other input of which is connnected to the output of the gate 31, and the output of which is connected to an input 51 to the block A.
The block A has outputs 52-55 and contains, besides the counter 48 with a clock input 56, four time circuits 57-60, two OR gates 61, 62 and a selector circuit 63 with e.g. two settable final value circuit points 64, 65. These components are connected in the manner shown in Fig. 5.
The block B has inputs 66, 67 which are connnected to the lines 22 and 23, respectively, and an input 68 which is connected to the circuit point 16. The block B also has an output 69 connected to the input side of the OR gate 43, and an output 70 connected to the input side of an OR gate 71 connected between the gate 42 and the line 20. The block B comprises three time circuits 72-74, eight gates 75-82 and a settable interrupt circuit point 83 interconnected in the manner shown in Fig. 5.
The coupling unit in Fig. 5, finally, comprises three gates 84-86 on the input side of the time circuit 40 and a gate 87 on the output side thereof. Fig. 5 does not show the communication line 17, the transistor unit 18 and the optocoupler unit 21.
When the voltage in the system comprising the coupling unit according to Fig. 5 is switched on, each RC circuit generates a pulse which, via the flip-flop 45, directly resets the counters 12 and 48 and blocks the clock input 25 to the counter 12. The pulse from the RC circuit 37 furthermore prevents, via the gates 49, 50, triggering of the time circuits 58-60 in the block A.
In the coupling unit pertaining to the last step of the operating sequence, the input 16 has the logical value "0", and one of the circuit points 64, 65 has the logical value "1", for which reason the time circuit 39 is triggered on the downward flank of the pulse of the RC circuit 37, and then also the time circuit 40. Two pulses of opposite polarities are thus supplied successively via the gates 43 and 71 and the lines 19, 20 to the communication line 17 and from there to the lines 22, 23 of all coupling units, whereby the selected time circuit or circuits 58-60 are started on the downward flank of the first recurring pulse and open the gate 87 for feeding the second pulse to the communication line 17.
The said second pulse will reset the flip-flop 45 in every coupling unit so that its Q output will be "1", but without indexing the counter 12. The operating sequence is now traversed in the same manner as for the coupling unit according to Fig. 3.
The block A can also operate as a monitoring device in case one or more clock pulses fail to appear on the communication line. In such a case, the signal level on the output from any of the time circuits 58, 60 will, contrary to what is normal, change to "0", whereby the time circuit 57 is triggered and a clock pulse is fed to the communication line 17 via the gate 43 and the line 19. In this manner, the defective coupling unit is skipped, and the operating sequence continues. If the last coupling unit of the sequence should be passed, for example because of an interference, the counter 48 will be indexed and, together with the time circuit 57, generate a resetting signal so that the operating sequence is restarted from its first step.
Several coupling units can have the monitoring device connected for different delays, i.e. with each timing circuit 58-60 activated via the circuit points 64, 65 and the selector 63. Upon failure of a coupling unit with connected delay, monitoring is ensured by another coupling unit with a connected longer dealy.
The block B in Fig. 5 constitutes an interrupt device which substantially immediately when the signal level on the input 16 changes, and independently of the position of the system in the operating sequence, produces a resetting signal supplied to all counters 12 via the communication line 17. This is achieved by imparting to the circuit point 83 of a coupling unit the logical value "1". Such a change in the signal level on the input 16 causes a triggering of the time circuit 72 and then of the time circuit 73 or 74 in response to the level on the inputs 66 and 67, respectively. As a result, a pulse having a polarity opposite to that of the pulse that caused the triggering of the time circuit 73 or 74, is supplied via the outputs 69 and 70, respectively, to the communication line 17 so that a resetting signal is generated.
Fig. 6 illustrates a further embodiment of a coupling unit in the system of the invention. Here, all components between the lines 19, 20, 22, 23, a decoder 13'' and an output/input 16 with transistor 34 and optocoupler 88 are shown only in the form of a block 89. Furthermore, a counter 12 and indicators 90 are shown which indicate the signal level on the inputs/outputs 16. The decoder 13'' has a plurality of outputs connected to the block 89, and the block 89 has a corresponding number of outputs connected each to one transistor 34, and a corresponding number of inputs which, via the optocouplers 88, are connectible each to one of the inputs 16 and each to one indicator 90. In this manner, one coupling unit can be common to a plurality of transmitters and/or receivers which form several transmitter and receiver groups.
The coupling unit shown in Fig. 6 is also capable of transferring information representing a digital value formed by several binary bits, by connecting one and the same output from the decoder 13'' and thus from the block 89 to the communication line 17 in several consecutive steps in the operating sequence of the system, whereby the receiver at issue can be successively supplied with the binary information bits. The coupling unit shown in Fig. 6 can also be used for repeatedly connecting one or more transmitter and receiver groups during one and the same operating sequence, i.e. at intervals which are shorter than the sum of the clock pulse intervals during an operating sequence.
By making the decoder 13'' programmable via programming inputs 91, the group affiliation of transmitters and receivers can be changed dynamically, i.e. while the operating sequence is traversed and in response to the development thereof. For example, the programming inputs 91 can be controlled by the state of one or more transmitters.
Fig. 7 illustrates an embodiment of a coupling unit suitable for connection of an external computer 92 to the system according to the invention. Here, the decoder 13'' controls a data exchange 93 having its input side connected to a plurality of latch circuits 94 via which the computer 92 can carry out two-way communication with the system according to the invention.
Fig. 8 shows an alternative clock device which also is integrated into the coupling units, but consists of a preferably crystal-controlled oscillator 95 in each coupling unit. By simultaneously resetting, by means of the resetting signal, all of these oscillators which have a common oscillation frequency, the oscillators can be made to operate in synchronism.
More particularly, the oscillator 95 is connected to the clock input of the counter 12 via a divider 96 which is reset every time a resetting signal appears on the output of the gate 30.
It should be emphasised that the system according to the invention is applicable to several sub-systems which can operate independently of one another, but can also communicate with one another via the coupling units according to the invention.
It should also be emphasised that one or more of the transmitters and the associated receivers can be arranged, upon activation via their counting device and decoder, to transmit and receive binary information consisting of several binary information bits. Finally, the individual circuits of the system according to the invention can, of course, be replaced by equivalent circuits; for example, the time circuits may comprise counters.
It will be appreciated that a number of modifications and alternative uses of the above-described system for transferring binary information are possible, and the invention should therefore be regarded as variable within the scope of the appended claims.

Claims

An information transferring system for transferring binary information in the form of binary data pulses between a plurality of transmitters (6) and receivers (5), which system comprises
a single communication line (17),
a plurality of separate communication groups each group consisting of one of said transmitters (6) and at least one of said receivers (5),
a coupling unit (11; 11') in each transmitter and in each receiver for connecting said transmitter and said receiver to said single communication line,
a counting device (12, 13; 12', 13') in each coupling unit connected to said single communication line for receiving clock pulses therefrom,
the coupling units pertaining to each one of said separate communication groups being adapted, after reception by the counting devices of a unique number of said clock pulses predetermined for that communication group, to connect said transmitter and said at least one receiver of that communication group to said single communication line for transferring information from said one transmitter to said at least one receiver of that communication group,
characterised in
that each one of the transmitters (6) when connected to said single communication line (17), is adapted to consecutively generate a clock pulse as an information representing binary data pulse which is transferred to all the counting devices (12, 13; 12', 13') via said single communication line as a clock pulse and to said at least one receiver as an information representing pulse,
that several of said coupling units (11; 11') each comprise a monitoring device (A) which, in the absence of a clock pulse during a predetermined time interval, supplies a clock pulse to said single communication line (17), and
that a coupling unit (11; 11') in the communication group last connected in the sequence to said single communication line comprises a resetting device (38; A) for supplying a resetting signal to all counting devices (12, 13; 12', 13') via said single communication line (17) when that communication group is connected to said single communication line.
An information transferring system as claimed in claim 1, characterised in that at least one of said coupling units (11; 11') comprises a resetting device (37) for supplying a resetting signal to all counting devices (12; 12') via the single communication line (17) upon start of the information transferring system.
An information transferring system as claimed in claim 1 or 2, characterised in that in at least one group the coupling unit (11') of the transmitter (6) comprises an interrupt device (B) for generating a resetting signal supplied via the single communication line (17) to all counting devices (12, 13; 12', 13'), if information to be transferred from said transmitter changes.
An information transferring system as claimed in any one of claims 1-3, characterised by a logical network having a plurality of inputs and at least one output, said network forming a transmitter (6) for each output and a receiver (5) for each input.
An information transferring system as claimed in any one of claims 1-4, characterised by a further communication group comprising a coupling unit having a counter device (12) which is connected to a decoder (13'') having a plurality of outputs, whereby the coupling unit is common to a plurality of transmitters (6) and/or receivers (5).
An information transferring system as claimed in claim 5, characterised in that the decoder (13'') is set to couple the receiver (5) of one and the same output consecutively or at predetermined intervals which are shorter than the sum of the clock pulse intervals, to the communication line (17) for receiving, respectively, a value represented by several binary bits and the information bit of the transmitter a corresponding number of times during each operating sequence.
An information transferring system as claimed in claim 5, characterised in that the decoder (13'') is programmable.
An information transferring system as claimed in any one of claims 1-7, characterised in that the clock pulses representing binary data information have one or the other of two opposite polarities.