SE460751B - SYSTEM FOR TRANSFER OF BINARY INFORMATION BETWEEN A MULTIPLE SENSOR AND RECEIVER - Google Patents

Abstract

In a system for transferring binary information between a plurality of transmitters (6) and receivers (5) connected to a common communication line (9, 9'; 17), each transmitter (6) and each receiver (5) are connected to the communication line via a coupling unit (11; 11') of their own. The coupling unit comprises a counting device (12, 13; 12', 13'), and the counting devices of the coupling units pertaining to a group of a transmitter and at least one receiver are adapted, after reception of a constantly unique number of pulses predetermined for that group, to couple the transmitter and the receiver(s) of that group to the communication line for transferring a binary information bit from the transmitter to the receiver(s) of the group. Furthermore, a clock device (10; 11, 11') is coupled to supply pulses to all counting devices for sequentially coupling the different transmitter and receiver groups to said communication line.

Description

'. 460 751 10 15 20 25 30 35 2 that each sensor and each receiver are connected to the communication line via a separate switching unit, which comprises a counting device, the counting devices in the switching units belonging to a group of a sensor and at least one receiver being arranged to upon receipt of a unique number of pulses predetermined for that group, connect that group's transducer and receiver to the communication line for transmitting a binary information piece from the group's transducer to its receiver, and that a clock device is connected to simultaneously deliver pulses to the counting devices for sec. vental connection of the different groups of sensors and receivers to the communication line.

This system makes it possible to mount the various components of a machine together with a single communication cable and a power supply cable, before the function of the machine is finally specified. The switching units can also be mounted and the final function of the machine is determined by programming the switching units.

Additional components can be added through supplementary wiring and appropriate programming of additional connection units and any existing connection units.

The communication line can be branched in any way. so that, for example, loop shape is not required.

The switching units are thus advantageously generally designed and are given their final function through programming. In a preferred embodiment of the system, for this reason the clock device is integrated in the switching units, of which at least one in each group is arranged to also emit a clock pulse applied to all the counting devices when a binary information bit is transmitted.

In order to prevent the system according to the invention from stopping in the event of a fault in a switching unit, at least one of the switching units suitably comprises a monitoring device, which in the absence of a clock pulse during a predetermined time interval which is greater than the normal the time interval between clock pulses, emits a clock pulse to the communication line, so that the faulty switching unit is skipped in the working sequence of the system.

In order to start the system easily and automatically, at least one of the switching units may comprise a reset device, which emits a reset signal to all counting devices as soon as the machine's main switch is switched on, i.e. voltage appears in the power supply line. In this way, the system also always begins its work in one and the same step in its work sequence.

Since the system according to the invention is sequential, the working sequence must be repeated over and over again.

To achieve this, the switching unit for the sensor in the last group connected to the communication line in the sequence may comprise a reset device, which emits a reset signal to all counting devices via the communication line at the switching unit's connection of the associated sensor to the communication line.

When one of the sensors in the system changes state, the associated receiver will be given a change command, which can be a maximum of the time taken to complete the work sequence. According to the invention, however, the reaction time for carrying out a sensor change can be considerably reduced by providing the switching unit to a sensor in a group which requires a very short reaction time with an interrupt device which generates a reset signal supplied via the communication line all counters substantially immediately regardless of where in the work sequence the system is located. This group should normally be engaged as early in the work sequence as possible, so that in the event of a change in the condition of the associated sensor, the accompanying change command will always be executed 460 751 Å 10 15 20 25 30 35 4 within a fraction of the time for the entire work sequence.

For handling complex conditions, i.e. generating a command depending on the condition of several sensors, according to the invention a logic network, for example a combinatorial network, can be used, which network has a number of inputs, possibly. time delays and at least one output, each output being considered as a transducer and each input being considered as a receiver, which must then first receive its command before the composite condition can be formed.

The switching units belonging to the inputs of the combinatorial network must therefore be located earlier in the working sequence than the switching units belonging to the outputs of the combinatorial network.

In a preferred embodiment of the system according to the invention, a switching unit may be common to a plurality of sensors and / or receivers, which form several groups of sensors and receivers. This becomes possible by connecting a counting device common to the groups to a decoder with a plurality of outputs.

The different groups are distinguished by the one of the decoder outputs that is activated.

When using decoders with several outputs, the system according to the invention can also easily transmit information to a receiver, which information represents a digital value consisting of several binary bits, by connecting one and the same output from the decoder consecutively in several steps in the sequence to the commune. the cation line for receiving the binary bits in a sequence.

By making the decoders programmable, the group affiliation for sensors and receivers can be changed and this can even take place during the course of the work sequence by the programming being controlled by the state of one or more sensors. With programmable decoders, the work sequence can also be made to traverse any of several parallel branches depending on the condition of one or more transducers.

By means of a decoder as above, a computer's inputs / outputs can also be connected to the communication line without complicated input / output circuits.

The invention will be described in more detail in the following with reference to the accompanying drawings. Fig. 1 schematically shows an information transmission system according to prior art. Fig. 2 schematically shows an information transmission system according to the invention. Fig. 3 shows a simple embodiment of a coupling unit included in the system according to the invention. Fig. 4 shows signal waveforms occurring in Fig. 3. Fig. 5 shows a more complete embodiment of a coupling unit included in the system according to the invention. Fig. 6 is a block diagram of a switching unit for several groups of sensors and receivers. Fig. 7 is a block diagram of the connection of a computer to the system.

The previously known control system shown in Fig. 1 comprises a central unit in the form of a computer, from which an address line 2 and a data line 3 emanate. By means of connection units 4, 4 ', a receiver 5 and a sensor 6 can be connected to the data line. The connection units 4, 4 'are connected both to the address line 2 and to the data line 3 and more specifically comprise an address decoder 7, 7' and a gate 8, 8 '. The address decoder 7, 7 'further controls the state of the gate 8, 8'.

The sensor 6 can be, for example, a switch and the receiver 5 a solenoid valve.

The central unit 1 controls on and off the receiver 5 connected to the output of the gate 8 by sending the unique address of the address decoder 7 on the address line 2 and at the same time as the address decoder 7 opens the gate 8 sending a data signal on the data line 3, which data signal indicates whether knock-off shall take place and the gate 5 shall be supplied to the receiver 5.

The central unit 1 can thus control the on and off of any number of electrical components and so on. 46oI751 10 15 20 25 30 35 6 6 or units, which via their respective connection unit, which responds to a unique address, are connected to the data line 3 and the address line 2.

The central unit 1 can also retrieve information from the sensor 6 via the connection unit 4 '. The connection unit 4' is similar to the connection unit 4, but the direction of communication is reversed through the gate 8 'relative to that through the gate 8. The addresses of all address decoders 7, 7' are different. so that the central unit 1 only communicates via a connection unit 4, 4 'at a time.

In another known embodiment, the data line 3 is divided into two lines, one of which serves to feed data out of the central unit 1 and the other serves to transmit data into the central unit 1.

Additional variants of the system described above when known but all require the use of a central unit for control and monitoring of the process.

The information transmission system according to the present invention schematically shown in Fig. 2 is, like the known system, intended for a plurality of receivers, of which only the receiver 5 is shown, and a plurality of sensors, of which only the sensor 6 is shown. It further has a data line 9 and a clock line 9 ', on which clock pulses are output by a clock 10. The receiver 5 and the sensor 6 are connectable to the data line 9 by means of a switching unit 11 and 11', respectively, which are also connected to the clock line 9 '. The switching units 11, 11 'contain a counting device, consisting of a counter 12, 12' and a decoder 13, 13 '. The counting devices control the state of a gate 14 and 14 ', respectively, by means of which the receiver 5 and the sensor 6 can be connected to the data line 9.

In the system according to the invention, the decoders 13, 13 'are set to detect one and the same unique address; This means that the gate 14 in the switching unit 11 is opened simultaneously with the gate 14 'in the associated switching unit 11', whereby an input signal from the sensor 6 is transmitted via the data line 9 to the receiver 5. The receiver 5 is switched Xæ. , ', «. s! É-Aša Ä 10 15 20 25 30 35 460 751 7 thus on or off depending on the value of the input signal i from the sensor 6. It will be appreciated that the system according to the invention makes it possible to arrange a very large number of pairs of switching units ll, ll 'in arbitrary positions along the data and clock lines 9, 9'. Multiple receiver switching units can have the same address, so that a sensor can control several receivers simultaneously. In a special case, there does not need to be a receiver for a sensor. Connecting connection units need not be located next to each other but can be at any distance from each other along the lines 9, 9 '. .

In order for all counters 12, 12 'to start their counting of the clock pulses from 10 o'clock at the same time, the fin requires simultaneous resetting of all the counters. This can be done via a separate reset line, which is connected to the reset inputs of all counters 12, 12 'and supplies them with a reset pulse after the clock has emitted a pulse train with as many pulses as the number of addresses or groups of switching units.

In an embodiment of the system according to the invention, therefore, the communication line comprises a data conductor (line 9), a clock conductor (line 9 ') and a reset conductor (not shown). However, in a preferred embodiment of the present invention, a single conductor is used for the transmission of clock pulses, data pulses and reset signals. In this case, the clock 10 is suitably integrated in all switching units and each data pulse is also used as a clock pulse, while the reset signal consists of a specially designed signal.

The information transmission system according to the invention thus operates sequentially in a number of successive steps, wherein in each step a group of switching units with the same address for a short time interval is connected to each other via the communication line, after which the next group of connected switching units connects in the same way. sensors and receivers; 00 460 751 10 15 20 25 30 35 8 to the communication management, etc.

An embodiment of the switching units 11, 11 'included in the system according to the invention is shown in Fig. 3 and some signal waveforms occurring therein are shown in Fig. 4.

The switching unit shown in Fig. 3 is adjustable so that it can function either as the switching unit 11 or the switching unit 11 'in Fig. 2. This is achieved by setting the logic value at a point 15 in the unit. A sensor or a receiver is connectable in a connection point 16, which forms an output to a receiver, if the logic value at point 15 is set equal to "1", the value at point 15 is set equal to "0".

The switching unit transmits signals to a communication and input from a sensor, about the logic line 17, which is a single conductor, via a transistor stage 18 with an output connected to the communication line 17 and two inputs connected to a line 19 and a line 20, respectively. Furthermore, the switching unit receives information from the communication cable 17 via an optocoupler stage 21 with an input connected to the communication conductor 17 and two outputs each connected to the conductor 22 and 23, respectively. The signals appearing on the communication line 17 are either positive pulses or negative pulses. A positive pulse on the communication line 17 results in a positive pulse on the conductor 23, while a negative pulse on the line 17 results in a positive pulse on the conductor 22. Conversely, a positive pulse on the conductor 19 will generate a negative pulse on the line 17. while a positive pulse on the conductor 20 generates a positive pulse on the line 17.

The pulses supplied from the line 17 are supplied via the conductors 22 and 23 partly to the reset input 24 and clock input 25 of the counter 12, partly to an input of an AND gate 26. The pulses on the conductor 23 are also supplied to a data input 27 to a latch 28 All pulses on conductors 22 and 23 are applied to the clock 12 of the counter. ,,. o o .I -. IC II 10 15 20 25 30 35 460 751 9 input 25, while the reset input 24 only receives a pulse when a pulse on the conductor 22 and a pulse on the conductor 23 occur within a short time interval, which is determined by a timing circuit 29. The timing circuit 29, like other time circuits included in the switching unit, is a monostable flip-flop, which is triggered on the descending edge of incoming trigger pulses and at its output emits a positive pulse of predetermined length, which pulse is applied to an input of an AND gate 30, the second input of which is applied to via an OR gate 31 combined the pulses on the conductors 22 and 23.

The output of the decoder 13 is connected to the second input of the gate 26, the output of which is connected to the trigger input of a second timing circuit 32. The timing circuit 32 may be affected by the output signal from the gate 26, if it is activated due to the point 15 being set to logic " O". The output of the decoder 13 is also connected to the read input of the latch circuit 28, the output of which is connected to the input of a NAND circuit 33. The second input of the gate 33 is connected to the point 15.

The output of gate 33 is connected to the base of a transistor 34, the collector of which is connected to the output / input 16.

An OR gate 35 has its one input connected to the output of the timing circuit 32 and its second input connected to the output of an AND gate 36, one input of which is connected to an RC circuit 37 and the other input of which is connected to a programming point 38. , the logical value of which determines whether or not the switching unit belongs to the last step of the work sequence.

The output of gate 35 is connected to the trigger input of a third timing circuit 39, the output of which is connected to the trigger input of a fourth timing circuit 40 and to one input of each of two AND gates 41 and 42. The timing circuit 40 is active or inactive depending on the logical value in point 38. Its output is connected to one input of an OR gate 43, the output of which is connected to the conductor 19. The input / output 16 is also 0O 10 15 20 25 30 35 10 connected to the input of an inverter 44 and to the second input of gate 42. The output of inverter 44 is connected to the second input of gate 41.

The mode of operation of the switching unit in Fig. 3 will now be described with simultaneous reference to Fig. 4 and only assuming that the logic value at point 15 is "0" and at point 38 is "1". When the voltage is switched on in the system in which the switching unit is included, the RC circuit 37 generates a pulse, which is applied via the gates 36 and 35 to the triggering input of the timing circuit 39. Since the selected level at point 38 in this case also requires that the input 16 be set to a high level ("1"), the output pulse from the timing circuit 39 will be applied via the gate 42 to the conductor 20. Thus a positive pulse is obtained on the communication conductor 17. Since the output pulse from the timing circuit 39 is applied to the trigger input to the timing circuit 40, the output pulse from the timing circuit 40 will be applied via the gate 43 to the conductor 19 and thus give rise to a negative pulse on the communication conductor 17 immediately after the positive pulse. is shown in Fig. 4 in the signal waveform I. The reset signal will reset the counter 12 in all the switching units in the system in the manner described above.

Now consider the switching unit, whose decoder 13 is set to the count number 0 in the counter 12 and whose circuit point 15 is "0", i.e. where the circuit point 16 is input from a sensor (not shown). The signal on the output of the decoder 13 will thus have a high level (logic 1) during the time from the reset of the counter 12 until the next clock pulse is applied to the counter 12, as shown by waveform II in Fig. 4. The clock input 25 of the counter 12 is also supplied, but suppressed applied reset pulse also occurs at one input of gate 26 and now also at the output of this gate. This output pulse, which is shown as waveform III in Fig. 4, triggers the timing circuit 32. The output signal from the timing circuit 32 has the appearance shown as waveform 10 in 460 751 11 IV in Fig. 4 and triggers the timing circuit 39, whereby at e.g. high level at the input 16 the output pulse from the timing circuit 39 is fed via the gate 42 to the conductor 20, where a pulse of waveform V in Fig. 4 occurs. Thus, a positive pulse is generated on the communication conductor 17, as can be seen from waveform I in Fig. 4.

This pulse is applied to all counters 12 as a clock pulse and in the switching unit, whose decoder is set to the count 0 and whose circuit point 15 has the logic level 1 (ie where the circuit point 16 is output to a receiver not shown), the downward flank of the waveform II will be read. the value of the signal waveform VI in the latch 28, i.e. in this case a "1". Thus, the signal waveform VII in Fig. 4 will appear at the output of the latch 28, the output of the gate 33 will become logic "0" and a high level will be generated at the output 16. If instead the data and clock pulse output on the communication line 17 had been a negative pulse, the output of latch 28 would be set to the logic value "0" and thus the level of output 16 would have been low.

Through the output data and clock pulse, all counters 12 were set to the count number 1, so that the process described above is repeated for the switching units, the decoders 13 of which are set to this count number. The sequence continues in this way up to the switching unit, in which point 38 the logic value is a "1". This switching unit will thus generate a reset signal on the communication conductor 17 for resetting all counters 12 and repeating the work cycle just completed.

The more generally designed variant of the coupling unit 11, 11 'shown in Fig. 5 contains partly essentially the same components as the coupling unit according to Fig. 3, and partly two further component blocks A and B. Where applicable, the same reference numbers have been used in Figs. . Block A almost replaces the circuit point 38 460 751 10 15 20 25 30 35 12 in Fig. 3 but also has a start function and a monitoring function. Block B enables interruption and restart of the work sequence before it has reached its normal end.

The RC circuit 37 in Fig. 5 is connected to the reset input of a bistable flip-flop 45, the setting input of which is connected to the output of the gate 30. The Q output of the flip-flop 45 is connected to the input of an AND gate 46, the second input of which is connected to the output of gate 31 and whose output is connected to the clock input 25 of the counter f12 25. The 5 output of the rocker 45 is connected to an input of an OR gate 47, the second input of which is connected to the output of gate 30 and whose output is connected to the reset input of the counter 12 and also to the reset input of a counter 48 in block A. The RC circuit 37 is further connected to an inverter 49. Its output is connected to an input of an AND gate 50, the second input of which is connected to the output of the gate 31 and the output of which is connected to an input 51 of the block A.

Block A has outputs 52-55 and contains, in addition to the counter 48 with a clock input 56, four time circuits 57-60, two OR gates 61, 62 and a selector circuit 63 with, for example, two adjustable final value circuit points 64, 65.

These components are connected in the manner shown in Fig. 5.

Block B has inputs 66, 67, which are connected to the conductors 22 and 23, respectively, and an input 68 connected to the circuit point 16. Block B also has an output 69 connected to the input side of the OR gate 43 and an output 70 connected to the input side of an intermediate gate 42 and conductor 20 connected OR gate 71. Block B includes three time circuits 72-74, eight gates 75-82 and an adjustable interrupt circuit point 83 interconnected in the manner shown in Fig. 5.

Finally, the switching unit in Fig. 5 contains three gates 84-86 on the input side of the timing circuit 40 and a gate 87 on its output side. Fig. 5 does not show the communication line 17, the transistor stage 18 and the optocoupler stage 21, if the transmission line 17, the transistor stage 18 and the optocoupler stage 21.

When the voltage is switched on in the system in which the switching unit according to Fig. 5 is included, each RC circuit 33 generates a pulse, which via the rocker 45 directly resets the counters 12 and 48 and blocks the clock input 25 to the counter 12. The pulse from the RC circuit 37 prevents further via gates 49, 50 triggering of the time circuits 58-60 in block A.

In the switching unit belonging to the last step in the working sequence, the input 16 has the logic value "0" and one of the circuit points 64, 65 has the logic value "1", so that the timing circuit 39 is triggered on the downward edge of the RC circuit 37 and then the timing circuit 40. Two pulses of opposite polarities are thus output one after the other via the gates 43 and 71 and the conductors 19, 20 to the communication line 17 and from there to the conductors 22, 23 of all switching units, whereby * the one or the selected of the time circuits 58-60 are started on »the first recurring the descending edge of the pulse and 1 opens the gate 87 for the output of the second pulse to the communication line 17.

Said second pulse will reset the rocker 45 of all switching units, so that its Q output becomes "1", but without advancing the counter 12. The working sequence is now traversed in the same way as for the switching unit according to Fig. 3.

Block A can also function as a monitoring device in the event that one or more clock pulses are absent on the communication line 17. In such a case, the signal level at the output of one of the time circuits 58-60 will normally return to "0", whereby the time circuit I 57 triggered and a clock pulse is output on the communication. line 17 via gate 43 and conductor 19. Thereby E skips the faulty switching unit and the working sequence continues. If the last switching unit 1 in the sequence were to be passed, for example due to a disturbance, the counter 48 will step forward and together with: I 460 10 15 20 25 30 35 751 14 generate a reset signal, so that the working sequence is restarted from its first step .

Several switching units can have the monitoring device connected with different delay, ie with each of the time circuits 58-60 activated via the circuit points 64, 65 and the selector 63. In the event of a fault in a switching unit with switched-on delay, the monitoring is ensured by another switching unit with switched on, longer delay.

Block B in Fig. S constitutes an interrupt device which generates a reset signal supplied via all the counters 12 all the counters 12 substantially immediately when the signal level at the input 16 changes and this regardless of where in the working sequence the system is located. This is achieved by giving the circuit point 83 in a switching unit the logic value "1". In such a signal level change at the input 16, the timing circuit 72 and then the timing circuit 73 or 74 are then triggered depending on the level of the input 66 and 67, respectively. This results in a pulse of opposite polarity to the pulse which caused the triggering of the timing circuit 73 or 74 is output via the outputs 69 and 70, respectively, to the communication line 17, so that a reset signal is generated.

Fig. 6 shows a further embodiment of a coupling unit in the system according to the invention. Here, all the components between the conductors 19, 20, 22, 23, a decoder 13 "and an output / input 16 with associated transistor 34 and optocoupler 88 are shown only as a block 89. In addition, a counter 12 and indicators 90 are shown, which indicates the signal level on the inputs / outputs 16.

The decoder 13 "has several outputs connected to the block 89 and the block 89 has a corresponding number of outputs, which are connected to each of the transistors 34 and a corresponding number of inputs, which are connectable via the optocouplers 88 to each of the inputs 16 and each of its indicator 90. Thus, a coupling unit can be common to a plurality of sensors and / or receivers, which form several groups of sensors and receivers. "Ã Ö c go ao 10 .15. By means of the switching unit shown in Fig. 6, information can also be transmitted, which information represents a digital value formed by several binary bits, by connecting one and the same output from the decoder 13 "and thus from the block 89 to the communication line 17 in several consecutive steps in the working sequence of the system, whereby the current receiver can be supplied to the binary information bits in a sequence.The switching unit shown in Fig. 6 can also be used for connecting one or more groups of sensors and receivers several times during one and the same working sequence, i.e. with intervals which are less than the sum of the clock pulse intervals during a working sequence. By making the decoder 13 "programmable via" programming inputs 91, the group affiliation of sensors and receivers can be changed and this in a dynamic way, i.e. during the course of the work sequence and depending on its development. For example, the programming inputs 91 may be controlled by the state of one or more sensors.

Fig. 7 shows an embodiment of a switching unit which is suitable for connecting an external computer 92 to the system according to the invention. Here, the decoder 13 "controls a data exchange 93, the input side of which is connected to a plurality of latches 94, via which the computer 92 can communicate bidirectionally with the system according to the invention.

Finally, it should be pointed out that the system according to the invention can be applied to several subsystems, which can work independently of each other but also communicate with each other via the connection units according to the invention.

It will be appreciated that a variety of modifications and alternative uses of the binary information transmission system described above are possible, and the invention is therefore to be considered as variable within the scope of the appended claims.

Claims (10)

46Û 751 10 15 20 25 fw 16 PATENTKRAV 1. A system for transmitting binary information between a plurality of sensors (6) and receivers (5), which are connected to a common communication line (9, 9 '; 17), characterized in that each sensor (6) and each receiver (5) is connected to the communication line via its own connection unit (11: 11 '), which comprises a counting device (12, 13; 12', 13 '), the counting devices in those of a group of a sensor and at least one receiver belonging to the switching units is arranged to, after receiving a predetermined number of pulses predetermined for that group, in each case connect that group's sensor and receiver to the communication line for transmitting a binary piece of information from the group's sensor to its receiver, and a clock device (l0; ll, ll ') is connected to emit pulses to all the counting devices for sequential connection of the different groups of sensors and receivers to the communication line. Oh 2. A system according to claim 1, characterized in that the clock device is formed by the switching units (11, 11 '), of which at least one in each characteristic - 1 group is arranged to also, when transmitting a binary piece of information, a clock pulse applied to all counting devices (12, 13; 12 ', 13'). System according to claim 1 or 2, characterized in that at least one of the switching units (11, 11 ') comprises a monitoring device (A), which in the absence of a clock pulse for a predetermined time interval emits a clock pulse to k ä n - 'communication line (17). System according to one of Claims 1 to 3, characterized in that at least one of the switching units (11, 11 ') comprises a reset device (37) for outputting a reset signal to the device. Counters (12, 12 ') via the communication line (17) at the start of the system. SQ System according to any one of claims 1-4, characterized in that the switching unit (11 ') of the sensor (6) in the last group connected in sequence to the communication line (17) comprises a resetting device (38; A) for outputting a reset signal to all counting devices (12, 13; 12 ', 13') via the communication line at the connection of the switching unit to the communication line. System according to one of Claims 1 to 5, characterized in that in at least one of the groups the connection unit (11 ') to the sensor (6) comprises an interrupt device (B) for generating one of the counting devices (17) via the communication line (17). 12, 13; 12 'l3') supplied reset signal, if the sensor's information change. A system according to any one of claims 1-6, characterized by a logic network with a plurality of inputs and at least one output, which network forms a sensor (6) for each output and a receiver (5) for each input. . System according to one of Claims 1 to 7, characterized by a counting device common to at least one group, the counter (12) of which is connected to a "decoder (13") with a plurality of outputs, whereby the "switching unit (11, 11") , in which the counting device is included, is common to a plurality of sensors (6) and / or sensor - receivers (5). 9. A system according to claim 8, characterized in that the decoder (13 ") is set to connect one and the same output receiver (5) consecutively or characteristic - 'at predetermined intervals, which is less than the sum of the clock pulse intervals, to the communication line ( 17) for receiving a value represented by one of several binary bits and the information bit of the sensor a corresponding number of times during each working sequence. 10. A system according to claim 8, characterized in that the decoder (13 '') is programmable.