EP0348972A2 - Halbleiteranordnung und Verfahren zum Herstellen derselben - Google Patents

Halbleiteranordnung und Verfahren zum Herstellen derselben Download PDF

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Publication number
EP0348972A2
EP0348972A2 EP89111856A EP89111856A EP0348972A2 EP 0348972 A2 EP0348972 A2 EP 0348972A2 EP 89111856 A EP89111856 A EP 89111856A EP 89111856 A EP89111856 A EP 89111856A EP 0348972 A2 EP0348972 A2 EP 0348972A2
Authority
EP
European Patent Office
Prior art keywords
resin
semiconductor chip
semiconductor
principal plane
deformation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89111856A
Other languages
English (en)
French (fr)
Other versions
EP0348972A3 (de
Inventor
Keiji Yamamura
Akiteru Rai
Takashi Nukii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of EP0348972A2 publication Critical patent/EP0348972A2/de
Publication of EP0348972A3 publication Critical patent/EP0348972A3/de
Withdrawn legal-status Critical Current

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Classifications

    • H10W90/00—
    • H10W72/0198—
    • H10W74/012—
    • H10W74/121—
    • H10W74/15—
    • H10W72/536—
    • H10W72/5363—
    • H10W72/5522—
    • H10W72/5524—
    • H10W72/856—
    • H10W72/884—
    • H10W74/00—
    • H10W90/291—
    • H10W90/722—
    • H10W90/724—
    • H10W90/732—
    • H10W90/736—
    • H10W90/754—
    • H10W90/756—

Definitions

  • the present invention relates to a semiconductor device, more particularly to its packaging and a process for manufacturing thereof.
  • the semiconductor chips are fixed to both sides of the chip mounting part of the lead frame, and the electrical connection between semiconductor chips is effected through the lead frame, and therefore multi-terminal connection between semiconductor chips is not realized.
  • a semiconductor device comprises a plurality of semiconductor chips and a lead frame incorporated in a single package made of a molding resin, in which all or majority of a space between a pricnipal plane of the first semiconductor chip and a principal plane of the second semiconductor chip is filled up with a deformation preventive resin for preventing damages due to deformation of semiconductor chips.
  • the deformation preventive resin is capable of withstanding resin forming heat and resin filling pressure of a molding resin as the characteristic after curing.
  • the deformation preventive resin is capable of flowing smoothly into the space between the semiconductor chips as the character­istic before curing.
  • the deformation preventive resin is of solvent-free type and small in contraction.
  • the deformation preventive resin comprises a filler and one or plural resin selected from the group of epoxy resin, urea resin, melamin resin and phenol resin.
  • a process for manufacturing semiconductor device in another aspect of the invention comprises the steps of: forming on a principal plane of a first semiconductor chip, electrode terminals electrically connected with electrode terminals of a second semiconductor chip and electrode terminals electrically connected with an electrode terminal of the lead frame; forming a protective film on the other principal plane of the first semiconductor chip; forming on a principal plane of the second semiconductor chip, electrode terminals electrically connected with the electrode terminals of the first semiconductor chip; forming a protective film on the other principal plane of the second semiconductor chip; connecting electrically a metallic film of the electrode terminals of the first semiconductor chip and a metallic film of the electrode terminals of the second semiconductor chip by way of the solder bumps; filling a space of the principal plane of the first semiconductor chip and the principal plane of the second semiconductor chip with a deformation preventive resin other than a molding resin; packaging the semiconductor chips by the molding resin; and cutting and forming the lead frame into a desired shape.
  • the deformation prevent resin may contain a gap enough to withstand resin molding heat and resin filling pressure of the molding resin.
  • the deformation prevent resin has the coefficient of thermal expansion nearly equal to that of solder material of the solder bumps.
  • a different semiconductor chip is connected on the first semiconductor chip.
  • two or more other semiconductor chips are connected on the first semiconductor chip.
  • a third or more semiconductor chip is connected on the second semiconductor chip.
  • deterioration of element characteristics derived from deformation of semiconductor chips due to heat or pressure of filling with molding resin can be prevented by filling the space between the principal plane of the first semiconductor chip and the principal plane of the second semiconductor chip with a deformation preventive resin capable of withstanding the resin molding heat and resin filling pressure of the molding resin, and therefore excellent effects are brought about, such as multi-terminal connection of plural semiconductor chips and resin molded packaging without deterioration of element characteristics due to deformation of semi­conductor chips.
  • Fig. 1 is a sectional view of a semiconductor device in a first embodiment of the invention
  • Fig. 2 is an enlarged sectional view of the essential parts of the same.
  • the semiconductor device of the invention has a plurality of semiconductor chips 3, 4 and a frame 5 incorporated in a single package 2 made of a molding resin 1, in which the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of other at least one second semiconductor chip 4 are disposed opposite to each other.
  • electrode terminals 3b to be electrically connected with electrode terminals 4b of the second semiconductor chip 4, and electrode terminals 3c to be electrically connected with an electrode terminal 5a of the lead frame 5 are formed, and a protective film 6 for example SiO2, SiN and so on is formed on the other principal plane 3a.
  • the electrode terminals 4b to be electrically connected with the electrode terminals 3b of the first semiconductor chip 3 are formed, and a protective film 7 for example SiO2, SiN and so on is formed on the other principal plane 4a.
  • solder bumps 8 On the surface of the electrode terminals 4b, in order to form the solder bumps 8, a two-layered metal film 10 of, for example, titanium-tungsten alloy (800 ⁇ )/­copper (2400 ⁇ ) is formed, and the solder bumps 8 are formed thereon by vacuum deposition, plating or other method.
  • a two-layered metal film 10 of, for example, titanium-tungsten alloy (800 ⁇ )/­copper (2400 ⁇ ) is formed, and the solder bumps 8 are formed thereon by vacuum deposition, plating or other method.
  • the electrode terminals 3b of the first semiconductor chip 3 and the electrode terminals 4b of the second semiconductor chip 4 are connected together by the reflow method by overlaying the electrode terminals 4b on the electrode terminals 3b.
  • the lead frame 5 is composed of, as shown in Fig. 1, the electrode terminal 5a and a mounting part 5b on which the first semiconductor chip 3 is mounted, and the first semiconductor chip 3 is affixed to the mounting part 5b by means of a die-bonding agent 11.
  • the electrode terminal 5a and the electrode terminals 3c are electrically connected by means of bonding wire 12 such as aluminum wire and gold wire.
  • the space between the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of the second semiconductor chip 4 is preliminarily filled with a deformation preventive resin 13 (liquid thermoset resin) other than the molding resin by means of dispenser or the like, and is later cured in a heating over or the like.
  • a deformation preventive resin 13 liquid thermoset resin
  • the liquid thermoset resin 13 is required to flow smoothly into the space between the semiconductor chips as the characteristic before curing, and to be of solvent-free type and small in contraction by hardening owing to the necessity of filling the interface completely also after curing. Also as the characteristic after curing, owing to the necessity of minimizing the stress of the connections of solder bumps 8, it is desired that the coefficient of thermal expansion be nearly equal to that of solder material, and it is also necessary to select a material having mechanical properties capable of sufficiently withstanding the resin injection pressure of the molding resin 1 in the subsequent resin forming process. This is particularly important for preventing damages due to deformation of semiconductor chips caused by the stress of injection of molding resin.
  • an epoxy resin containing a filler e.g. XNR5008-1, manufactured by Nagase Chiba K.K., 1-1-17 Shimmachi, Nishi-ku, Osaka
  • XNR5008-1 manufactured by Nagase Chiba K.K., 1-1-17 Shimmachi, Nishi-ku, Osaka
  • the semiconductor chips 3, 4 are packaged by the molding resin 1 using a die, and the lead frame is cut and formed into a desired shape.
  • the space of the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of the second semiconductor chip 4 is preliminarily filled with the deformation preventive resin 13 other than the molding resin 1.
  • the material should be selected from those having the coefficient of thermal expansion nearly equal to that of the solder material and mechanical properties capable of sufficiently withstanding the injection pressure of the molding resin 1 in the resin forming process.
  • the curing state of the setting resin of the deformation preventive resin may not always be in the airtight state as in the first embodiment, but also contain a gap 15 enough to withstand the resin molding heat and resin filling pressure of the molding resin.
  • thermoset resin instead of the epoxy resin used as the deformation preventive resin (thermoset resin) in the mentioned embodiment, urea resin, melamin resin, or phenol resin may be used. These thermoset resins are generally excellent in heat resistance and solvent resistance, and are capable of realizing a tough forming by using a filler.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
EP19890111856 1988-07-01 1989-06-29 Halbleiteranordnung und Verfahren zum Herstellen derselben Withdrawn EP0348972A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP165551/88 1988-07-01
JP63165551A JPH0750759B2 (ja) 1988-07-01 1988-07-01 半導体装置

Publications (2)

Publication Number Publication Date
EP0348972A2 true EP0348972A2 (de) 1990-01-03
EP0348972A3 EP0348972A3 (de) 1990-09-19

Family

ID=15814520

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890111856 Withdrawn EP0348972A3 (de) 1988-07-01 1989-06-29 Halbleiteranordnung und Verfahren zum Herstellen derselben

Country Status (2)

Country Link
EP (1) EP0348972A3 (de)
JP (1) JPH0750759B2 (de)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992002039A1 (en) * 1990-07-18 1992-02-06 International Business Machines Corporation Improved interconnection structure and test method
US5274913A (en) * 1991-10-25 1994-01-04 International Business Machines Corporation Method of fabricating a reworkable module
AU656595B2 (en) * 1991-07-09 1995-02-09 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
EP0642157A1 (de) * 1993-09-06 1995-03-08 Commissariat A L'energie Atomique Verfahren zur Anordnung von Bauelementen mittels Kleber
EP0706219A1 (de) * 1994-09-26 1996-04-10 International Business Machines Corporation Verfahren und Apparat für einen elektronischen Modul ohne Spannungen
WO1997037374A3 (en) * 1996-03-26 1997-11-20 Advanced Micro Devices Inc Method of packaging multiple integrated circuit chips in a standard semiconductor device package
EP0841700A3 (de) * 1996-11-12 1998-12-02 Nec Corporation Auf Standard-IC montierte Halbleiter-Schaltung mit kundenspezifischer Schaltung
EP0913866A4 (de) * 1997-03-10 2000-03-22 Seiko Epson Corp Elektronische komponente und halbleiter anordnung herstellungsverfahren, eine damit beschichtete leiterplatte und elektronische einrichtung mit einer solchen leiteplatte
EP0740343A3 (de) * 1995-04-24 2000-04-05 Matsushita Electric Industrial Co., Ltd. Chip-auf-Chip-Struktur zum Verhindern von Übersprechungsrauschen
EP0961319A3 (de) * 1998-05-28 2002-04-24 Xerox Corporation Integrierte, flexible Verbindung
WO2004064139A3 (de) * 2003-01-10 2005-04-21 Infineon Technologies Ag Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels
EP1688993A3 (de) * 1996-04-02 2007-12-26 Micron Technology, Inc. Standardisierte Bond-Platzbestimmung und Apparat

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04179263A (ja) * 1990-11-14 1992-06-25 Hitachi Ltd 樹脂封止型半導体装置とその製造方法
JPH0574774A (ja) * 1991-09-12 1993-03-26 Nec Kyushu Ltd 樹脂封止型半導体装置
JPH05109977A (ja) * 1991-10-18 1993-04-30 Mitsubishi Electric Corp 半導体装置
KR100235108B1 (ko) * 1993-03-19 1999-12-15 윤종용 반도체 패키지
US5583747A (en) * 1993-11-01 1996-12-10 Baird; John H. Thermoplastic interconnect for electronic device and method for making
KR100443484B1 (ko) * 1996-02-19 2004-09-18 마츠시타 덴끼 산교 가부시키가이샤 반도체장치및그제조방법
KR100559664B1 (ko) * 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP5481724B2 (ja) * 2009-12-24 2014-04-23 新光電気工業株式会社 半導体素子内蔵基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687395A (en) * 1979-12-18 1981-07-15 Fujitsu Ltd Semiconductor device
JPS5979561A (ja) * 1982-10-29 1984-05-08 Hitachi Ltd 半導体装置
JPS6094744A (ja) * 1983-10-27 1985-05-27 Nippon Denso Co Ltd 混成集積回路装置
JPS63142663A (ja) * 1986-12-04 1988-06-15 Sharp Corp 半導体装置とその製造方法

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992002039A1 (en) * 1990-07-18 1992-02-06 International Business Machines Corporation Improved interconnection structure and test method
AU656595B2 (en) * 1991-07-09 1995-02-09 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
US5274913A (en) * 1991-10-25 1994-01-04 International Business Machines Corporation Method of fabricating a reworkable module
EP0642157A1 (de) * 1993-09-06 1995-03-08 Commissariat A L'energie Atomique Verfahren zur Anordnung von Bauelementen mittels Kleber
FR2709871A1 (fr) * 1993-09-06 1995-03-17 Commissariat Energie Atomique Procédé d'assemblage de composants par hybridation et collage.
EP0706219A1 (de) * 1994-09-26 1996-04-10 International Business Machines Corporation Verfahren und Apparat für einen elektronischen Modul ohne Spannungen
CN1110094C (zh) * 1994-09-26 2003-05-28 国际商业机器公司 用于消除电子组件应力的方法和装置
CN1041579C (zh) * 1994-09-26 1999-01-06 国际商业机器公司 用于消除电子组件应力的方法和装置
EP0740343A3 (de) * 1995-04-24 2000-04-05 Matsushita Electric Industrial Co., Ltd. Chip-auf-Chip-Struktur zum Verhindern von Übersprechungsrauschen
WO1997037374A3 (en) * 1996-03-26 1997-11-20 Advanced Micro Devices Inc Method of packaging multiple integrated circuit chips in a standard semiconductor device package
EP1688993A3 (de) * 1996-04-02 2007-12-26 Micron Technology, Inc. Standardisierte Bond-Platzbestimmung und Apparat
US6037666A (en) * 1996-11-12 2000-03-14 Nec Corporation Semiconductor integrated circuit having standard and custom circuit regions
EP0841700A3 (de) * 1996-11-12 1998-12-02 Nec Corporation Auf Standard-IC montierte Halbleiter-Schaltung mit kundenspezifischer Schaltung
EP1427016A3 (de) * 1997-03-10 2005-07-20 Seiko Epson Corporation Halbleiterbauelement und mit demselben versehene Leiterplatte
US7119445B2 (en) 1997-03-10 2006-10-10 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6803663B2 (en) 1997-03-10 2004-10-12 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US8134237B2 (en) 1997-03-10 2012-03-13 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
EP1447849A3 (de) * 1997-03-10 2005-07-20 Seiko Epson Corporation Halbleiterbauelement und mit demselben versehene Leiterplatte
US7932612B2 (en) 1997-03-10 2011-04-26 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6989605B2 (en) 1997-03-10 2006-01-24 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6515370B2 (en) 1997-03-10 2003-02-04 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
US7598619B2 (en) 1997-03-10 2009-10-06 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
EP0913866A4 (de) * 1997-03-10 2000-03-22 Seiko Epson Corp Elektronische komponente und halbleiter anordnung herstellungsverfahren, eine damit beschichtete leiterplatte und elektronische einrichtung mit einer solchen leiteplatte
US7436071B2 (en) 1997-03-10 2008-10-14 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
EP0961319A3 (de) * 1998-05-28 2002-04-24 Xerox Corporation Integrierte, flexible Verbindung
US7229851B2 (en) 2003-01-10 2007-06-12 Infineon Technologies Ag Semiconductor chip stack
WO2004064139A3 (de) * 2003-01-10 2005-04-21 Infineon Technologies Ag Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels

Also Published As

Publication number Publication date
EP0348972A3 (de) 1990-09-19
JPH0215660A (ja) 1990-01-19
JPH0750759B2 (ja) 1995-05-31

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