EP0337752A2 - Système d'affichage graphique permettant d'extraire une image partielle - Google Patents

Système d'affichage graphique permettant d'extraire une image partielle Download PDF

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Publication number
EP0337752A2
EP0337752A2 EP89303602A EP89303602A EP0337752A2 EP 0337752 A2 EP0337752 A2 EP 0337752A2 EP 89303602 A EP89303602 A EP 89303602A EP 89303602 A EP89303602 A EP 89303602A EP 0337752 A2 EP0337752 A2 EP 0337752A2
Authority
EP
European Patent Office
Prior art keywords
storage area
outline
image
display system
graphic display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89303602A
Other languages
German (de)
English (en)
Other versions
EP0337752A3 (fr
EP0337752B1 (fr
Inventor
Yutaka Aoki
Kazunori Takayanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0337752A2 publication Critical patent/EP0337752A2/fr
Publication of EP0337752A3 publication Critical patent/EP0337752A3/fr
Application granted granted Critical
Publication of EP0337752B1 publication Critical patent/EP0337752B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster

Definitions

  • This invention relates to a graphic display system and more particu­larly, to a graphic display system capable of cutting out any desired partial image by utilising a raster operation.
  • an object of the invention is to allow any desired partial image to be cut out by utilising a raster operation function that an ordinary graphic display system has.
  • the graphic display system capable of cutting out a partial image according to the invention comprises image storage means, outline drawing means for drawing an outline of the partial image to be cut out, mask data generator means for generating mask data according to the outline, and partial image write means for writing into the image storage means only a portion of the source image which is not masked by the mask data.
  • the image storage means is an all point addressable (APA) memory in which an source image storage area for storing the source image, a work storage area for storing a dot pattern representing the outline, and a destination storage area for storing the partial image are allocated.
  • the mask data generator means generates mask data, whereby a region enclosed with the outline dot pattern is put in the non-masked state, while the rest is put in the masked state.
  • the partial image write means may write the partial image and predetermined pattern data into the destination storage area by combining them.
  • the system comprises an APA memory 10 for storing a source image from which a partial image is cut out, an outline drawing unit 12 for drawing an outline of the partial image to be cut out, a mask data generator 14 for generating mask data based on the outline data drawn by the outline drawing unit 12, a bit operation circuit 16 that allows bit-by-bit operations on the image data read from the APA memory 10, a raster operation circuit 18, a multiplexer (MUX) 20 for selecting either the mask data from the mask data generator 14 or the image data from the raster operation circuit 18 and supplying it to data input terminals of the APA memory 10, a video circuit 22 for converting the image data read from the APA memory 10 into signals for display, a display unit 24 for providing a visual display by the signals from the video circuit 22, and a controller 26 for controlling the entire system.
  • a colour display system for storing a source image from which a partial image is cut out
  • an outline drawing unit 12 for drawing an outline of the partial image to be cut out
  • a mask data generator 14 for
  • the APA memory 10 con­sists of n memory planes.
  • Figure 2 illustrates the contents of the APA memory 10 which contains a source image storage area 10A, a work storage area 10B for drawing the outline of the partial image to be cut out, and a destination storage area 10C to which the cut out partial image is transferred. These storage areas 10A - 10C are of the same size.
  • the APA memory 10 may further contain pattern data 10D and 10E. These pattern data are combined with the source image data in the raster operation circuit 18.
  • the user When it is desired to cut out a partial image, the user first uses the outline drawing unit 12 to draw an outline (for example, a circle) defining a partial image that the user wants to cut out from a source image stored in the storage area 10A.
  • the outline drawing unit 12 may be a hardware drawing facility that is usually provided in the graphic display system.
  • European Patent Application No. 86105380.9 (JA9-85-011) assigned to the same assignee as the present invention discloses a technique for drawing a quadratic curve including a circle by using such a hardware drawing facility. If it is desired to interactively draw the outline while viewing the screen of the display 24, a mouse may be used as the outline drawing unit 12.
  • the dot pattern 11 representing the outline drawn by the outline drawing unit 12 is written in the work storage area 10B.
  • the location of the outline dot pattern 11 in the work storage area 10B corresponds to that of the partial image 11′ in the source image storage area 10A.
  • one dot consists of n bits, but as far as the outline dot is concerned, it may be a single bit.
  • the outline dots are written in a selected one of the n memory planes. In case where one dot consists of n bits, it is sufficient to assign a specific colour code of n bits to the outline dot.
  • the outline dot pattern 11 written in the work storage area 10B has an even number of outline dots per line when it is viewed laterally. For example, in a case of a circle, it is easily recognised that the num­ber of dots turned on is two per line except for the upper and lower ends. At the upper and lower ends, writing is performed in the work storage area 10B so that two adjacent or close dots are turned on. Although two or more adjacent dots may be turned on to approximate a curve in an ordinary drawing facility, only the outermost dot is turned on when the outline of the partial image is drawn. This sat­isfies a condition to make the number of outline dots per line even. This condition is required to distinguish on each line the start and end points of a region enclosed with the outline. In this embodiment, an even-numbered dot including No. 0 represents the start point while an odd-numbered dot represents the end point.
  • the con­tents of the work storage area 10B in the APA memory 10 are read out to the mask data generator 14 under control of the controller 26. It is assumed here that a unit of access for the APA memory 10 is one word (16 bits).
  • the controller 26 reads the words one by one begin­ning from the address at the upper left corner of the work storage area 10B or its start address, and supplies it to the mask data generator 14.
  • the mask data generator 14 checks whether the read word contains the even- or odd-numbered outline dot. Then, it generates mask data that put on each line a region from the even- numbered outline dot to the next odd-numbered one in the non-masked state, and the rest in the masked state.
  • Figure 3 shows an illustrative configuration of the mask data generator 14.
  • the exclusive OR gates 30-i are cascade connected in which the output of each gate becomes the input of the next gate.
  • the output of the last exclusive OR gate 30-15 is fed to the first exclusive OR gate 30-0 through the latch 32.
  • the second input of each gate is supplied with a corresponding bit B0 - B15 in a word read from the work storage area 10B.
  • Outputs M0 - M15 of the exclusive OR gates 30-i form a word of mask data.
  • the latch 32 is first cleared prior to the operation.
  • the mask data bits M0 - M15 are all 0's because B0 - B15 and Q output of the latch 32 are all 0's. This con­dition is maintained as long as the 16 bits B0 - B15 of each word read from the work storage area 10B are all 0's.
  • a read word contains the first or number 0 outline dot.
  • a corre­sponding bit Bi is 1 so that the output Mi of the exclusive OR gate 30-i, which receives it as its input, becomes 1.
  • the output Mi is fed to the next exclusive OR gate 30-(i+1), its output Mi+1 also becomes 1 as long as its second input Bi+1 is not 1, that is, the next odd-numbered outline dot is not contained.
  • the mask data with Mi-M15 being all 1's is gener­ated.
  • an enable signal is generated and applied to a clock input C of the latch 32. This sets the latch 32 which then supplies the Q output of 1 to the first exclusive OR gate 30-0. This is to maintain the previous state in preparation for the next word reading. Under this condition, even if an all 0 word is read next, an all 1 mask data is generated.
  • the output Mj of the exclusive OR gate 30-j which receives a corresponding 1 bit at Bj, becomes 0 because another input from the previous stage is also 1.
  • the mask data generator 14 generates 0 mask bits which represent the masked state, for the outside of the outline dot pattern 11 written in the work storage area 10B, and 1 mask bits which represent the non-masked state, for the inside of the outline dot pattern 11.
  • a word of mask data M0 - M15 from the mask data generator 14 is supplied to the data input terminals of the APA memory 10 through the multiplexer 20 and the bus 28.
  • the APA memory 10 is a dynamic RAM having write per bit capability, in which only a data input terminal receiving a 1 mask bit can perform writing.
  • the controller 26 reads a corresponding image data word of 16 bits from the source image storage area 10A and supplies it to the bit ope­ration circuit 16.
  • the bit operation circuit 16 is a hardware facil­ity which allows a bit boundary transfer for the image data from the APA memory 10 which is accessed only at a word boundary.
  • Such hard­ware is well known in the bit block transfer technique (generally called BitBlt), detailed description of which is omitted.
  • the image data from the bit operation circuit 16 is entered into the raster operation circuit 18.
  • the raster operation circuit 18 performs a specific logic operation on the image data read from the APA memory 10 and other image data (such as a predetermined pattern data), and supplies its result to the multiplexer 20.
  • a logic operation such as pass (allowing a selected image data to pass through as it is), AND, OR or exclusive OR is specified by the controller 26.
  • a partial image can be cut out from the source image as it is without any change, or in an overlapped manner with a desired pattern. Examples of such a raster operation circuit are disclosed in European Patent Application No. 87101587.1 (Docket No. JA9-85-023) assigned to the same assignee as the present invention, and IBM Technical Disclosure Bulletin, Vol. 27, No. 7A, pp. 4019 - 4020, December 1984.
  • the image data word from the raster operation circuit 18 is supplied to the data input terminals of the APA memory 10 through the multi­plexer 20 and the bus 28.
  • the controller 26 sends a write command and an appropriate address of the destination storage area 10C to the APA memory 10.
  • writing of the image data is performed at the data input terminals that have received the 1 mask bits representing the non-masked state.
  • the work storage area 10B of the APA memory 10 is provided separately from the source image storage area 10A and the destination storage area 10B, it may be allocated the same area as either one of them. It is noted, however, if the work storage area 10B is allocated the same area as the source image storage area 10A, it is necessary to use a colour code not used in the source image for the outline dots because the outline dots are represented by a colour code of n bits. In case of a monochrome sys­tem, the work storage area 10B cannot be the same as the original image storage area 10A.
  • the outline of the partial image is a circle, but any desired outline such as an ellipse, rectangle or doughnut shape may be drawn.
  • dots of upper and lower horizontal sides are not written in the work storage area 10B.
  • Generated for the upper side are mask data that put a region between the uppermost ends of the left and right sides in the non-masked state, and for the lower side are mask data that put a region between the lowermost ends of the left and right sides in the non- masked state.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
  • Digital Computer Display Output (AREA)
  • Image Processing (AREA)
EP89303602A 1988-04-15 1989-04-12 Système d'affichage graphique permettant d'extraire une image partielle Expired - Lifetime EP0337752B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63091913A JPH01270176A (ja) 1988-04-15 1988-04-15 部分イメージの切出しが可能なグラフイツク表示システム
JP91913/88 1988-04-15

Publications (3)

Publication Number Publication Date
EP0337752A2 true EP0337752A2 (fr) 1989-10-18
EP0337752A3 EP0337752A3 (fr) 1991-11-21
EP0337752B1 EP0337752B1 (fr) 1995-01-04

Family

ID=14039823

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89303602A Expired - Lifetime EP0337752B1 (fr) 1988-04-15 1989-04-12 Système d'affichage graphique permettant d'extraire une image partielle

Country Status (6)

Country Link
EP (1) EP0337752B1 (fr)
JP (1) JPH01270176A (fr)
KR (1) KR930004023B1 (fr)
CN (1) CN1011092B (fr)
BR (1) BR8901475A (fr)
DE (1) DE68920353T2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1058797C (zh) * 1993-03-19 2000-11-22 富士通株式会社 消除锯齿的线条显示设备
US8769406B2 (en) 2006-08-14 2014-07-01 Konica Minolta, Inc. Image display apparatus capable of displaying image while retaining confidentiality

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145821A1 (fr) * 1983-12-22 1985-06-26 International Business Machines Corporation Circuit de remplissage de surfaces pour une mémoire de trame d'images graphiques en couleurs

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145821A1 (fr) * 1983-12-22 1985-06-26 International Business Machines Corporation Circuit de remplissage de surfaces pour une mémoire de trame d'images graphiques en couleurs

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 28, no. 6, November 1985, NEW YORK US pages 2721 - 2724; 'GRAPHIC BIT-BLT COPY UNDER MASK ' *
JEE JOURNAL OF ELECTRONIC ENGINEERING. vol. 24, no. 251, November 1987, TOKYO JP pages 28 - 31; MASAYOSHI NAKANE: 'VIDEO RAM CHIPS DESIGNED FOR COMPUTER GRAPHICS ' *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1058797C (zh) * 1993-03-19 2000-11-22 富士通株式会社 消除锯齿的线条显示设备
US8769406B2 (en) 2006-08-14 2014-07-01 Konica Minolta, Inc. Image display apparatus capable of displaying image while retaining confidentiality

Also Published As

Publication number Publication date
KR930004023B1 (ko) 1993-05-19
EP0337752A3 (fr) 1991-11-21
DE68920353D1 (de) 1995-02-16
DE68920353T2 (de) 1995-07-13
EP0337752B1 (fr) 1995-01-04
CN1011092B (zh) 1991-01-02
CN1037975A (zh) 1989-12-13
KR890016434A (ko) 1989-11-29
BR8901475A (pt) 1989-11-14
JPH01270176A (ja) 1989-10-27

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