EP0279662A2 - Circuit interface à mémoire vidéo - Google Patents

Circuit interface à mémoire vidéo Download PDF

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Publication number
EP0279662A2
EP0279662A2 EP88301353A EP88301353A EP0279662A2 EP 0279662 A2 EP0279662 A2 EP 0279662A2 EP 88301353 A EP88301353 A EP 88301353A EP 88301353 A EP88301353 A EP 88301353A EP 0279662 A2 EP0279662 A2 EP 0279662A2
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EP
European Patent Office
Prior art keywords
memory
character
data
chip
attribute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88301353A
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German (de)
English (en)
Inventor
Korbin S. Van Dijke
Daniel W. Yoder
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Philips Semiconductors Inc
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VLSI Technology Inc
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Publication of EP0279662A2 publication Critical patent/EP0279662A2/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/40—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory

Definitions

  • This invention relates generally to video display circuits, and relates more particularly to a video controller chip and interconnections among the video controller chip and video memory chips.
  • a video display circuit functions as an interface between a processor, which generates data to be displayed, and a video display device, which provides means for visually displaying such data.
  • the video display circuit typically includes two functionally distinct circuits, a video controller and a video memory.
  • the video controller receives data to be displayed from the processor, stores that data in the video memory, and, upon demand, generates a corresponding video signal using data from the video memory to drive the video display device. Changes in the visual display are accomplished by changing the data stored in the video memory.
  • the video display device such as a cathode ray tube (CRT) or liquid crystal display can be considered as comprising a rectangular array of picture elements, known as pixels, that visually represent the data to be displayed. Each pixel is turned on or turned off according to the video signal. If the pixels are displayed in color, the video signal turns on and off the color components of each pixel.
  • the video signal defines horizontal raster lines (rows of pixels) in a scanning sequence that repetitively covers the display area of the video display device.
  • Alphanumeric text is typically represented within a computer in two forms: coded and bit-mapped. Associated with each character in the character set is a code and a two-dimensional bit-map.
  • the coded form is used in the processing and memory portions of the computer because the coded form requires far less storage space than does the bit-mapped form.
  • ASCII American Standard Code for Information Interchange
  • characters are represented in their bit-mapped form as character pixel data, which defines the on/off states of the pixels that visually represent the characters.
  • the character pixel representation is a two-dimensional bit pattern or map that defines the visual display of the character.
  • the pixel data associated with each character in the character set is stored in a font memory portion of the video memory.
  • the font memory contains character pixel representations for all of the different characters that can be displayed. If the font memory is sufficiently large, alternative pixel representations of the characters can be stored in the font memory to provide a choice of font styles.
  • Some video display circuits are capable of displaying characters in various optional formats such as underlined, blinking, or inverse video.
  • attribute codes of the characters to be displayed are stored in an attribute memory portion of the video memory.
  • the attribute codes specify which of the special display options is to be invoked.
  • the video controller section of the video display circuit To display alphanumeric text, the video controller section of the video display circuit generates a video signal that defines the on/off states of the pixels of the video display device.
  • the video signal contains data that defines the pixels of the character display row by row, with several adjacent rows of pixels defining each row of characters.
  • the video display circuit converts the coded form of each character into its corresponding pixel representation. For each character, the video controller addresses a character memory to read a stored character code, and then uses the character code to address the font memory to read one row of the corresponding character pixel representation. The data read from the font memory defines the video signal. If, for example, the size of each character pixel representation is seven pixels wide by nine pixels high, then each entry into the font memory will yield seven bits of display data that define the states of seven pixels. The video controller repeats this process for each character in the row. When the end of the character row is reached, the video controller returns to the first character in the row and repeats the above process to generate the video signal for the next adjacent row of pixels.
  • the video controller will address the font memory nine times for each character because nine rows of pixels are needed to display each row of characters. After a video signal for a complete row of characters has been generated, the video signal for the next row of characters is generated in the same fashion.
  • the video signal may need to be modified in order to display the characters according to the selected display options.
  • the video controller must read the character attribute data by addressing the attribute memory each time the character memory is addressed and then transform the character pixel data into the form dictated by the attribute data.
  • graphics display data is usually represented within the processor and the video memory in a pixel or bit-mapped form, wherein the memory cells of the video memory correspond one-to-one with the pixels of the video display device.
  • the processor periodically updates the pixel data stored in the video memory in order to incorporate new graphics display data.
  • the video controller simply reads the video memory cell by cell.
  • several bits of the graphics display data are read in parallel from the video memory into a high-speed shift register, which shifts the bits out serially to the video display device.
  • Video display devices with increased pixel resolution and color display capability are increasingly in demand. Such demand increases both the size of the video memory and the data processing bandwidth of the video controller.
  • Another demand is that computers have the capability to display both alphanumeric and graphics data. This complicates the design of the video controller and video memory.
  • Another trend throughout the electronics industry is one of reducing the number of integrated circuit chips necessary to perform a given function in order to reduce cost and size. The overall effect of these trends is to push designers of video display circuits to utilize single chip video controllers coupled to fast access memories in order to fulfill the performance and cost requirements.
  • the design of a single chip video controller involves much more than simply combining the functions of a multichip video controller into a single chip. Because the cost of a chip is directly related to the number of input/output pins, the chip designer must carefully consider the interconnections between the video controller chip and the processor, the video memory, and the video display device. Assuming that the video memory will consist of more than one chip, the number of pins of the video controller chip needed to interface to the video memory, as well as the performance of the video display circuit, will depend on whether the video memory chips are connected directly or through a bus. In a direct connection, separate address and data pins are allotted for each video memory chip, while in a bus connection, one set of address and data pins are shared among all video memory chips.
  • a direct memory connection In a direct memory connection, all of the memory chips can be accessed simultaneously, while in a bus connection, only a single selected memory chip can be accessed at any one time, due to the shared address and data connections.
  • a direct connection allows fast access to all of the video memory chips, but requires dedicated address and data inpuy/output pins for each video memory chip, which significantly increases cost.
  • a bus connection minimzes the number of pins and their associated cost, but degrades the circuit performance because such a connection increases the effective access time to the video memory.
  • One design approach is to use fast access memory devices to improve the performance by reducing memory access time. Since two or three memory cycles are required, faster memory chips will significantly speed up the performance of the video display circuit. The disadvantage of this approach is the extra cost of such memories.
  • the video controller chip designer often must ensure that the controller chip can also handle graphics display data.
  • the interconnections between the video controller chip and video memory chips must allow for the efficient transfer of both alphanumeric and graphics display data.
  • the present invention provides a video display circuit and method for receiving and storing character code data provided by a processor and for supplying character pixel data in the form of a video signal to a video display device.
  • the circuit includes a controller chip for receiving the character code data from the processor and for supplying the character pixel data to the video display device, and also includes memory chips that are coupled to the controller chip.
  • the memory chips include a character memory chip that stores the character code data received from the processor, and a font memory chip that stores the character pixel data, or bit-maps, of each character of the character set.
  • the data output pins of the character memory chip are connected to several of the address pins of the font memory chip as well as to the controller chip.
  • These address pins of the font memory chip are denoted character font address pins, which select within the font memory chip a block of memory cells containing the bit-map of a character when the corresponding character code is supplied to the character font address pins.
  • Other address pins of the font memory chip are denoted row address pins, which are connected to the controller chip and which select a row of memory cells within the selected block of memory cells. The character pixel data stored in the selected font memory chip memory locations is accessed and used to compose the video signal.
  • the method includes the steps of receiving the character code data from the processor and storing it in the character memory chip, and supplying character pixel data to the video display device from the font memory chip.
  • the step of supplying character pixel data further includes the steps of addressing a memory location in the character memory chip by the controller chip, then supplying the character code data stored at that memory location directly to the character font address pins of the font memory chip by the character memory chip and supplying a row address to the row address pins of the font memory chip by the controller chip, and then supplying to the controller chip the character pixel data stored at the addressed row of the font memory chip.
  • the video display circuit of the present invention further includes an attribute memory chip in which is stored attribute data that specifies certain attributes of the character code data stored in the character memory chip.
  • the address pins of both the character memory chip and the attribute memory chip are connected in common to the controller chip so that both memory chips are addressed simultaneously.
  • the data pins of the attribute memory chip and the data pins of the font memory chip are connected in common to the controller chip to reduce the number of pins of the controller chip.
  • a fourth memory chip is coupled to the controller to provide extra memory for storing graphics display data.
  • the address pins of this extra memory chip are connected to the controller chip in common with the address pins of the font memory chip, so that both memory chips are addressed simultaneously.
  • the data pins of the extra memory chip are connected to the controller chip in common with some of the address pins of the character and attribute memory chips in order to reduce the number of pins of the controller chip.
  • One key feature of the present invention is that the number of input/output pins of the controller chip is reduced due to the overlapping functions served by the address and data pins of the controller chip. Such minimization is important to the development of an economical single chip video controller.
  • the font memory chip is directly addressed by the data output signals of the character memory chip. Since the controller chip need not read and store the character code data from the character memory chip prior to addressing the font memory chip, the access time for the character pixel data is reduced from two full memory cycles to somewhere between one and two memory cycles. Such a reduction in the font memory access time allows either increased pixel data rates from a particular type of memory chip or the use of slower and lower cost memory chips while providing the same overall pixel data rate.
  • the video display circuit can operate in both character and graphics modes.
  • graphics mode the four memory chips are utilized as a bit-mapped graphics memory.
  • the interconnection between the memory chips and the controller chip provides direct access to the character and attribute memory chips and direct access to the font and extra memory chips.
  • FIGS 1 through 4 of the drawings depict various preferred embodiments of the present invention for purposes of illustration only.
  • One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein.
  • the preferred embodiment of the present invention is a video display circuit 10 that is operable for receiving and storing character and graphics display data provided by a processor 12 and for supplying character pixel data in the form of a video signal to a video display device 14.
  • the video display circuit 10 includes a controller chip 16 and four memory chips: a character memory chip 18, an attribute memory chip 20, a font memory chip 22, and an extra memory chip 24.
  • the interconnections between the memory chips 18-24 and the controller chip 16 will first be described with reference to Figure 1, followed by a description of the controller chip with reference to Figure 2, and thereafter followed by an explanation of the operation of the video display circuit.
  • Each of the four memory chips 18-24 is connected to the controller chip 16 via address pins (A), data pins (D), a write enable pin (WE), an output enable pin (OE), and a chip select pin (CS).
  • the address pins of both the character memory chip 18 and the attribute memory chip 20 are connected in common to the controller chip 16 at pins labeled A(CA), (which signifies the a ddress pins for the c haracter and a ttribute memory chips).
  • the d ata pins of the c haracter memory chip 18 are connected to the controller chip 16 at D(C), while the d ata pins of the a ttribute memory chip 20 are connected to the controller chip at D(AF) (which also connects to the f ont memory chip 22).
  • Figure 1 indicates the number of signal lines in the address and data connections for memory chips having an 8K x 8 bit configuration, which requires thirteen address lines and eight data lines. Of course, other memory configurations could be substituted.
  • the write enable pins of the character and attribute memory chips are connected in common to the controller chip at WE.
  • the output enable pins of the character and attribute memory chips are individually connected to the controller chip at OE(C) and OE(A), respectively, while the chip select pins of the character and attribute memory chips are individually connected to the controller chip at CS(C) and CS(A), respectively.
  • the character memory chip 18 and the attribute memory chip 20 are, thus, connected to the controller chip 16 through separate data and control lines and common address lines.
  • the font memory chip 22 and the extra memory chip 24 are also connected to the controller chip through separate data and control lines and common address lines.
  • Several of the address pins of both the font memory chip 22 and the extra memory chip 24 are connected in common to the data pins of the character memory chip 18 and to the controller chip at AL(FE), (which signifies the l ow a ddress pins for the f ont and e xtra memory chips, and which are the same pins as D(C)).
  • AL(FE) which signifies the l ow a ddress pins for the f ont and e xtra memory chips, and which are the same pins as D(C)
  • the remaining address pins of the font memory chip 22 and the extra memory chip 24 are connected in common to the controller chip 16 at pins labeled AH(FE) (which signifies the h igh a ddress pins for the f ont and e xtra memory chips). These are the "row" address pins, which will also be discussed in greater detail below.
  • the data pins of the font memory chip 22 are connected in common with the data pins of the attribute memory chip 20 to the controller chip 16 at D(AF).
  • the data pins of the extra memory chip 24 are connected in common with some of the address pins of the character and attribute memory chips to the controller chip 16 at D(E) which also serve as some of the A(CA) pins.
  • the write enable pins of the font and extra memory chips are connected in common to the controller chip at WE.
  • the output enable pins of the font and extra memory chips are connected in common to the controller chip at OE(FE) while the chip select pins of the font and extra memory chips are individually connected to the controller chip at CS(F) and CS(E), respectively.
  • the interconnections between the controller chip 16 and the memory chips 18-24 are accomplished using forty-two pins of the controller chip: thirteen for the address pins of the character and attribute memory chips and the data pins of the extra memory chip, eight for the data pins of the attribute and font memory chips, eight for the data pins of the character memory chip and the low address pins of the font and extra memory chips, five for the high address pins of the font and extra memory chips, four for the chip select pins, three for the output enable pins, and one for the write enable pin. Additional pins (not shown) of the controller chip 16 are used for interconnections with the processor 12 and the video display device 14.
  • the circuitry of the controller chip 16 is illustrated schematically in Figure 2.
  • the controller chip 16 serves two basic functions: (1) to provide access by the processor 12 to the memory chips 18-24 for the storage and retrieval of both character and graphics display data, and (2) to generate a video signal that drives the video display device 14 according to the display data stored in the memory chips.
  • the controller chip includes four multiplexers 26, 28, 30 and 32 that selectively connect the processor 12 through a processor interface circuit 34 to the memory chips 18-24.
  • the controller chip also includes a memory address control circuit 36 that defines memory addresses during the generation of the video signal, and a display interface circuit 38 that generates the video signal by converting parallel data bits from the memory chips into a serial stream of data bits in a format compatible with the video display device 14.
  • a memory interface control circuit 40 coordinates the access to the memory chips 18-24 by controlling several latches 42-54, buffers 56-60, and multiplexers 26-32, and by generating the write enable, output enable, and chip select signals.
  • addresses are sent from either the memory address control circuit 36 or the processor interface circuit 34 to the character and attribute memory chips 18 and 20 through multiplexer 30, latch 52, buffer 60, and pins A(CA).
  • Data is sent from the processor interface circuit 34 to the extra memory chip 24 also through multiplexer 30, latch 52, buffer 60, and pins D(E).
  • Data is sent from the processor interface circuit 34 to either the attribute memory chip 20 or the font memory chip 22 through latch 48, buffer 58, and pins D(AF).
  • the eight bit low addresses of the font and extra memory chips 22 and 24 may be sent from either the processor interface circuit 34 or the memory address control circuit 36 to the font and extra memory chips through multiplexer 28, latch 44, buffer 56, and pins AL(FE).
  • Data is sent from the processor interface circuit 34 to the character memory chip 18 also through multiplexer 28, latch 44, buffer 56, and pins D(C).
  • the five bit high addresses of the font and extra memory chips 22 and 24 are sent from either the processor interface circuit 34 or the memory address control circuit 36 to the font and extra memory chips through multiplexer 26, latch 42, a buffer 62 and pins AH(FE).
  • Five lines of the video signal may be sent to the video display device 14 through multiplexer 26, latch 42, and buffer 62 via pins AH(FE) of the controller chip (shown in Figure 1) as an alternative route between the display interface circuit 38 and the video display device 14.
  • Data can also be received by the controller chip 16 from the memory chips 18-24.
  • Data from the character memory chip 18 is received by the controller chip 16 through pins D(C), a buffer 64, and latch 46.
  • Data from the attribute memory chip 20 and the font memory chip 22 is received by the controller chip through pins D(AF), a buffer 66, and latch 50.
  • Data from the extra memory chip 24 is received by the controller chip through pins D(E), a buffer 68, and latch 54.
  • the output pins of the latches 46, 50, and 54 are coupled to the display interface circuit 38 for supplying data thereto for the generation of the video signal, and are coupled to the multiplexer 32 for selectable transmission of data to the processor 12 via the processor interface circuit 34.
  • the video display circuit 10 operates in two modes: character mode and graphics mode.
  • character codes and attributes of each character to be displayed are provided to the controller chip 16 by the processor 12 and are stored in the character and attribute memory chips 18 and 20, respectively.
  • the memory interface control circuit 40 activates the write enable signal (WE) and the character memory chip select signal (CS(C)), activates buffers 56 and 60, directs multiplexer 30 to select the address lines from the processor interface circuit 34 for connection to latch 52, and directs multiplexer 28 to select the data-in line from the processor interface circuit for connection to latch 44.
  • WE write enable signal
  • CS(C) character memory chip select signal
  • the memory interface control circuit 40 activates the write enable signal (WE) and the attribute chip select signal (CS(A)), activates buffers 58 and 60, and directs multiplexer 30 to select the address lines from the processor interface circuit 34 for connection to latch 52.
  • the attribute data is supplied to the attribute memory chip 20 through the processor interface 34, latch 48, and buffer 58.
  • the individual bit-maps of the characters of the character set are also provided to the video display circuit 10 by the processor 12, and this font data is stored in the font memory chip 22.
  • the memory interface control circuit 40 activates the write enable signal (WE) and the font memory chip select signal (CS(F)), activates buffers 56, 58, and 62 directs multiplexer 26 to select the address lines from the processor interface circuit 34 for connection to latch 42 and directs multiplexer 28 to select the address lines from the processor interface circuit for connection to latch 44.
  • the bit-map data is supplied to the font memory chip 22 through the processor interface 34, latch 48, and buffer 58.
  • Graphics display data is transferred to the extra memory chip 24 in a manner similar to data transfers to the font memory chip 22, except the data passes through the processor interface 34, multiplexer 30, latch 52, and buffer 60.
  • the controller chip 16 provides the capability for the processor 12 to read the contents of the memory chips 18-24. Read operations are similar to the write operations, but separate buffers 64, 66 and 68 and latches 46, 50 and 54 are used to capture the data from the memory chips. Data is supplied to the processor 12 through multiplexer 32 and the processor interface 34.
  • each memory cell 74 in the character memory chip 18 has a corresponding memory cell 76 at the same address in the attribute memory chip 20.
  • a character code which is preferably a one byte ASCII code, is stored in the character memory to represent each character to be displayed.
  • the hexadecimal value of 31, which is the ASCII code for the numeral "1” is stored in the addressed memory cell of the character memory chip.
  • An attribute code of that character is optionally stored in the attribute memory chip at the same address.
  • the attribute code might indicate, for example, that the displayed character is to be underlinked, blinking, or inverse video.
  • the attribute might also indicate a font selection if several alternative fonts are available in the font memory chip.
  • the individual bit-maps of the characters of the character set are stored in a block of memory cells 78 in the font memory chip 22.
  • the numeral "1" is represented by a sixteen bit by eight bit binary bit-map.
  • Each memory cell contains a value of either one or zero, depending upon whether the corresponding pixel of the visual display is to be illuminated or not.
  • the character bit-map is addressed one row at a time, rather than one memory cell at a time.
  • Each of the sixteen rows of the bit-map contains eight memory cells.
  • the bit-map data in the font memory chip 22 is addressed by a combination of character code data stored in the character memory chip 18 and a row address supplied by the memory address control circuit 36 of the controller chip 16.
  • the eight bit value stored in the character memory chip directly supplies the low address to the character font address pins of the font memory chip. This eight bit value locates within the font memory the bit-map of the character code stored in the character memory.
  • a four bit row address is supplied by the memory address control circuit 36 of the controller chip 16 to the row address pins of the font memory chip. This four bit value locates a particular row within the bit-map. If one or more alternative fonts are stored in the font memory chip, a font select signal from the controller chip is also supplied to the character font address pins to select the font.
  • the video display circuit 10 As another step in character mode operation, the video display circuit 10 generates a video signal in the form of character pixel data.
  • the video signal is a serial stream of bits that defines the states of the pixels of the video display device 14 according to the character and attribute data stored in the video screen memory.
  • the display screen of the video display device can be partitioned into a rectangular array of character blocks 80, which in turn are partitioned into a rectangular array of pixels 82.
  • the video display device might be capable of displaying twenty-five rows of characters, with each row containing eight characters.
  • Each character block has the same number of pixels that are contained in the character bit-maps stored in the font memory chip 22, namely, sixteen rows by eight columns.
  • the display screen would thus contain a total of 400 rows (25 x 16) by 640 columns (80 x 8) of pixels.
  • the video display circuit 10 generates the video signal to define horizontal rows, or scan lines, of pixels. Each scan line defines the states of all the pixels in that row, the next scan line defines the states of all the pixels in the next row, and so on.
  • the video signal is a serial stream of bits that define the pixels along a scan direction in each scan line of the video display device.
  • the above-described example requires sixteen scan lines to define each row of characters, and 400 scan lines to define a complete screen of twenty-five rows of characters.
  • the controller chip 16 To generate the video signal, the controller chip 16 first addresses the character and attribute memory chips 18 and 20 and then addresses the font memory chip 22 to read each row in the bit-map of each character to be displayed. Firstly, the memory address control circuit 36 of the controller chip 16 determines the address in the character and attribute memory chips 18 and 20 of a character to be displayed, the memory interface control circuit 40 activates the CS(C) and CS(A) chip select signals and the OE(C) and OE(A) output enable signals, and the memory interface control circuit directs multiplexer 30 to send the address to the address pins of the character and attribute memory chips. The memory address control circuit 36 also determines the current row address, which is supplied to the font memory chip 22 through multiplexer 26.
  • the character memory chip supplies its character code data to the character font address pins of the font memory chip, and the controller chip reads the attribute data supplied to it by the attribute memory chip.
  • the memory interface control circuit 40 then deactivates the attribute memory chip select and output enable signals, CS(A) and OE(A), and activates the font memory chip select and output enable signals, CS(F) and OE(FE).
  • the controller chip then reads the character pixel data for the selected row from the font memory chip, and the display interface circuit 38 converts the character pixel data into the video signal by serializing the data and by processing it according to the selected attributes.
  • the two access cycles of the character and font memory chips overlap to speed up the performance of the video display circuit 10.
  • the controller chip does not have to read the character code data from the character memory chip and then rebroadcast it to the font memory chip because the character code data goes directly from the data pins of the character memory chip to the character font address pins of the font memory chip.
  • the attribute data from the attribute memory chip and the character pixel data from the font memory chip enters the controller chip through the same pins, thereby reducing the number of pins required to interface the controller chip to the memory chips.
  • the processor 12 provides bit-by-bit graphics data to the video display circuit 10, which is then stored in the four memory chips 18-24.
  • the controller 16 reads the stored graphics data from each pair of memories, namely the character and attribute memory chips 18 and 20, and the font and extra memory chips 22 and 24. Since each pair of memory chips is coupled to common address lines and separate data lines, the controller chip can read sixteen bits of graphics data per each memory access cycle.
  • the font memory chip is addressed solely from the controller chip 16, not the character memory chip 18 as in character mode.
  • An alternative embodiment of the present invention provides an additional interconnection between the controller chip 16 and the video display device 14.
  • the AH(FE) pins of the controller chip 16 are needed to access the font memory chip 22 only during the second part of the access cycle.
  • the five AH(FE) pins may be used for other purposes, such as relaying additional information to the video display device 14.
  • the multiplexer 26 is used to selectively connect certain video signals from the display interface circuit 38 to the AH(FE) pins during the first part of the access cycle and to connect address signals from the memory address control circuit 36 to the AH(FE) pins during the second part of the access cycle.
  • Such multiplexing provides an additional interconnection between the video display circuit 10 and the video display device 14 without increasing the number of pins on the controller chip 16.
  • each memory chip of the present invention need not be a discrete integrated circuit.
  • the several claimed memory chips could be combined into a single, monolithic memory device having the designated interconnections with the controller chip.
  • each of the claimed memory chips could actually consist of several integrated circuits.
  • memory chip is not to be read as limited to only a single, monolithic integrated circuit. More generally, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP88301353A 1987-02-19 1988-02-18 Circuit interface à mémoire vidéo Withdrawn EP0279662A2 (fr)

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US1628487A 1987-02-19 1987-02-19
US16284 1987-02-19

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EP0279662A2 true EP0279662A2 (fr) 1988-08-24

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JP (1) JPS63206793A (fr)

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US5805905A (en) * 1995-09-06 1998-09-08 Opti Inc. Method and apparatus for arbitrating requests at two or more levels of priority using a single request line

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DK2406679T3 (da) 2009-03-11 2017-04-18 Sakura Finetek Usa Inc Autofokusfremgangsmåde og autofokusanordning
US10139613B2 (en) 2010-08-20 2018-11-27 Sakura Finetek U.S.A., Inc. Digital microscope and method of sensing an image of a tissue sample
DE102013103971A1 (de) 2013-04-19 2014-11-06 Sensovation Ag Verfahren zum Erzeugen eines aus mehreren Teilbildern zusammengesetzten Gesamtbilds eines Objekts
US10007102B2 (en) 2013-12-23 2018-06-26 Sakura Finetek U.S.A., Inc. Microscope with slide clamping assembly
US11280803B2 (en) 2016-11-22 2022-03-22 Sakura Finetek U.S.A., Inc. Slide management system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805905A (en) * 1995-09-06 1998-09-08 Opti Inc. Method and apparatus for arbitrating requests at two or more levels of priority using a single request line

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