EP0327412B1 - Passivation process of a integrated circuit - Google Patents

Description

The present invention relates to a new method for passivation of integrated circuits.

In fact, in integrated circuits, it is usual to cover the active surfaces with a passivation layer or protective layer, the aim of which is to avoid pollution which could alter the characteristics of the components forming the integrated circuit. This layer consists of a stable dielectric such as silicon dioxide, silicon nitride or silicon oxynitride. The materials used as dielectric have the disadvantage of being relatively hard. This characteristic involves the risk of cracks in the passivation layer, these cracks being able to propagate as far as the active surfaces. As a result, the passivation layer no longer plays its protective role.

On the other hand, the passivation layers are generally deposited on the last metallization layer. The metallization layer is etched to make the metal conductors. In general, the etching is carried out under reactive plasma. It is practically anisotropic and takes place in the direction of the thickness of the layer. As a result, the conductors have an approximately rectangular section. Also, when the passivation layer is deposited on the conductors, it can be seen that the passivation layer is not deposited uniformly but has a hilly structure with particularly large recesses at the edges of the conductors.

JP-A-61-232646 (see PATENT ABSTRACTS OF JAPAN Vol.11 Number 77 (E-487) (2524)) concerns the reduction of thermal stresses between a protective resin and a protective layer, by inserting two layers between them of SiO₂ or SiN₄ separated by a layer which absorbs these thermal stresses. This layer has low elasticity.

The object of the present invention is to remedy the drawbacks mentioned above.

It relates to a new process for passivation of an integrated circuit comprising the formation of at least one final dielectric layer, characterized in that it consists in depositing on the integrated circuit a first layer of hard dielectric material, deposit on this layer, a layer of a dielectric material stretch and deposit on the surface thus obtained a second layer of a hard dielectric material.

The use of a soft layer makes it possible to fill the undulations of the layer of lower hard dielectric material and to obtain a relatively flat surface on which a second protective layer of hard dielectric material can be easily deposited. This soft layer interposed between two hard layers makes it possible to absorb the mechanical stresses coming from the outside and in particular prevents the propagation of cracks which could have been produced in the layers of hard dielectric material. In addition, the outer hard layer prevents plastic deformation of the soft layer and distributes the external stresses in the soft layer. By hard layer or soft layer in the present invention means a layer defined by a measurement of microhardness. Thus, a hard layer will have a hardness greater than 700 HK (HK = knoop hardness) (hardness measured at 15 g on a thin film of a few micrometers, deposited on a silicon wafer). A soft layer will have a hardness of less than 400 HK.

According to another characteristic of the present invention, the following steps are also carried out one or more times: namely, the last dielectric layer is covered with a soft dielectric layer, then a layer of d is deposited on this new layer '' a hard dielectric material. By using this process, a "mille feuille" type structure is produced, intercalating hard dielectric layers with soft dielectric layers, which allows better absorption of stresses and blocking of the transmission of cracks.

According to a preferred embodiment, the soft layer is obtained from a viscous suspension which is subjected to annealing.

On the other hand, according to yet another characteristic of the present invention, the dielectric suspension is eliminated once it has been annealed to a certain thickness so as to obtain a flat upper surface.

Preferably, the dielectric suspension consists of a gel based on mineral silica which will advantageously be in colloidal form, such as the gel commonly called S.O.G (for Spin On Glass in English) well known in the art.

Optionally, the soft layer can be produced by a polyimide layer, but this has the drawback of having a large thickness.

On the other hand, the layer of hard dielectric material will consist of a material such as silicon dioxide SiO₂, silicon nitride Si₃ N₄ or a silicon oxy-nitride of the form SiO _x N _y .

• la figure 1 est une vue en coupe schématique d'un circuit intégré comportant une couche de passivation réalisée conformément à l'art antérieur,
• la figure 2 est une vue en coupe par AA des deux couches supérieures de la figure 1,
• les figures 3A à 3E sont des vues analogues à celles de la figure 2, illustrant les étapes essentielles du procédé de passivation conforme à l'invention et,
• la figure 4 est une vue analogue à celle de la figure 3B représentant une variante du procédé de passivation conforme à la présente invention.

Other characteristics and advantages of the present invention will appear on reading the description of an embodiment made with reference to the appended drawings and in which:

• FIG. 1 is a schematic sectional view of an integrated circuit comprising a passivation layer produced in accordance with the prior art,
• FIG. 2 is a sectional view through AA of the two upper layers of FIG. 1,
• FIGS. 3A to 3E are views similar to those of FIG. 2, illustrating the essential steps of the passivation process according to the invention and,
• Figure 4 is a view similar to that of Figure 3B showing a variant of the passivation method according to the present invention.

To allow a better understanding of the process of the present invention, the different layers have been shown on an enlarged scale and without respecting their dimensions.

The integrated circuit shown in FIG. 1 is made up of a semiconductor substrate 1, for example an N-type silicon substrate in which isolation zones have been produced between the components constituted, for example, by thick oxide. 2 and diffused zones 3 such as for example P + doped zones. Thin oxide zones 4 have been produced on the substrate, which have been covered for example with grids 5 made of polycrystalline silicon. The different areas above were obtained using conventional methods well known to those skilled in the art. These different zones have been covered with an insulating layer 7 made for example of silicon dioxide SiO₂. The circuit shown in FIG. 1 by way of illustrative example consists of two N-type MOS transistors. To make the connection between different zones such as, for example, between two corresponding diffusions of the two MOS (Metal Oxide Semiconductor) transistors ) shown in Figure 1, the layer 7 has been etched in a known manner and a metal layer 8 has been deposited on the insulating layer 7. This metal layer is made, for example, of aluminum. The conductors are then produced by etching, by placing the metal layer under reactive plasma. This engraving is generally anisotropic. It is carried out in the direction of the thickness of the layer and thus gives the conductor an approximately rectangular section as shown in FIG. 2.

If the circuit has only one level of interconnections, the conductors 8 are then covered with a passivation layer or protective layer which can be produced in silicon oxide Si O₂, in silicon nitride Si₃ N₄ or in silicon oxynitride Si O _x N _y . The material used to produce this passivation layer 9 is a hard material which can fracture following stresses as shown by reference 6 in FIG. 1. On the other hand, in particular in MOS technology where several layers of different materials are superimposed and engraved, the passivation layer has a hilly profile.

We will now describe, with reference to FIGS. 3A to 3E, the different stages of the passivation process of an integrated circuit according to the present invention in the case where the soft layer is obtained from a viscous dielectric suspension subjected to annealing. . This case corresponds to a particularly advantageous embodiment of the present invention. The method consists in depositing on the hilly layer 9 a dielectric suspension viscous 10. This suspension is spread uniformly over the entire surface of the dielectric layer 9. Due to its viscosity, this suspension completely fills the existing voids and forms a thin layer over the entire surface of the dielectric layer 9.

For example, the suspension used can be a gel based on mineral silica advantageously in colloidal form such as the gel commonly called S.O.G. (Spin On Glass) well known to those skilled in the art. In this case, the dielectric suspension is used in the same way as the photosensitive resins used for the configuration of the elements of the integrated circuit. The suspension 10 is then annealed. This annealing is carried out for 1/2 hour at 425 ° C. Thus, the solvent in the suspension evaporates while the dielectric forms a compact mass 10 ′ as shown in Figure 3B. This mass forms a thin film on the dielectric layer 9 located above the conductors 8. Next, this layer is covered with another layer 11 of hard dielectric material such as silicon nitride, silicon dioxide or silicon oxynitride. In known manner, this dielectric layer is deposited using a chemical vapor deposition process well known to those skilled in the art.

For example, the layer 9 has a thickness of approximately 500 nm, the layer 10 a thickness of approximately 300 nm and the layer 11 a thickness of approximately 12 00 nm. The thicknesses of layers 9 and 11 can be modified provided that their sum is constant and equal to 1700 nm ± 300 nm.

The use for the passivation layer of a composite structure consisting of a first hard dielectric layer 9 covering the conductors 8 and then a soft layer of a viscous dielectric material which has been annealed, this layer being covered with another layer of hard dielectric material, absorbs the stresses generated on the circuit and prevents the propagation of cracks inside the integrated circuit.

In addition, the surface of the integrated circuit presents a less accentuated undulation, because the soft layer partially fills the undulations of the first hard layer.

According to an alternative embodiment shown in FIG. 4, to obtain an even more planar upper surface, it is possible to uniformly remove a film of small thickness from the dielectric layer 10 ′ by placing this layer under reactive plasma. This results in an almost flat surface 10.

To improve the absorption of external stresses and avoid the propagation of cracks inside the passivation layer, the upper hard dielectric layer 11 can be again covered with a viscous dielectric suspension. This layer is then subjected to annealing to obtain the layer 12 ′ in FIG. 3E. This layer 12 ′ is again covered with a layer of hard dielectric material 13. The materials used for the viscous layer 12 and the hard dielectric layer 13 are identical to the materials already used for the hard dielectric layers 9 and 11 and for the viscous layer 10. This superposition of layers gives a structure of the "millefeuille" type and can be renewed one or more times. It provides a relatively flat upper surface and improves stress absorption.

Claims (10)

1. Method of passivating an integrated circuit comprising the formation of at least one final dielectric layer, characterised in that it consists of depositing a first layer (9) of a hard dielectric material, depositing on this layer a layer of a soft dielectric material (10) obtained from a viscous suspension which is subjected to baking, and depositing on the surface thus obtained a second layer (11) of a hard dielectric material.
2. Method according to Claim 1, characterised in that, in addition, the following steps are carried out one or more times:

   - covering the last hard dielectric layer with a soft dielectric layer (12), and then

   - depositing a layer (13) of a hard dielectric material so as to produce a structure of the "millefeuille" type.
3. Method according to either one of Claims 1 and 2, characterised in that the soft layer is a layer of polyimide.
4. Method according to Claim 1, 2 or 3, characterised in that the baked dielectric suspension is eliminated over a certain thickness so as to obtain a plane top surface.
5. Method according to any one of Claims 1 to 4, characterised in that the dielectric suspension is a gel based on mineral silica, advantageously in a colloidal form.
6. Method according to any one of Claims 1 to 5, characterised in that the layer of hard dielectric material is a layer of SiO₂, Si₃N₄ or SiO_xN_y.
7. Integrated circuit comprising at least one final passivation layer, characterised in that this layer comprises a first layer of hard dielectric material (9), a first layer of soft dielectric material (10) obtained from a viscous suspension subjected to a circuit, and a second layer (11) of hard dielectric material.
8. Integrated circuit according to Claim 7, characterised in that the layer (10) of soft dielectric material has a thickness of around 300 nm.
9. Integrated circuit according to Claim 7 or 8, characterised in that the first (10) and second (11) layers of hard material have a variable thickness, the sum of which is constant and equal to 1700 nm ± 300 nm.
10. Integrated circuit according to Claim 9, characterised in that the first layer (9) of hard dielectric material has a thickness of around 500 nm and in that the second layer (11) of hard dielectric material has a thickness of around 1200 nm.

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