JPS6179233A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6179233A
JPS6179233A JP59202294A JP20229484A JPS6179233A JP S6179233 A JPS6179233 A JP S6179233A JP 59202294 A JP59202294 A JP 59202294A JP 20229484 A JP20229484 A JP 20229484A JP S6179233 A JPS6179233 A JP S6179233A
Authority
JP
Japan
Prior art keywords
film
insulating film
cover insulating
stress
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59202294A
Other languages
Japanese (ja)
Inventor
Shuichi Harajiri
原尻 秀一
Kazuaki Kondo
和昭 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59202294A priority Critical patent/JPS6179233A/en
Publication of JPS6179233A publication Critical patent/JPS6179233A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent the generation of cracks of an insulating film by providing a cover insulating film composed of a three-layer film in which the first insulating films sandwiches the second insulating film which has the opposite stress. CONSTITUTION:A cover insulating film has the composite film structure composed of three layers in which a PSG film 10, an Si nitride film 11, a PSG film 12 are laminated and the film 11 is sandwiched. Namely, the cover insulating film composed of a three-layer film in which the PSG film 10 and 12 whose film quality is soft, sandwich the Si nitride film 11 having the opposite stress is arranged. Thus the balance of the stress in the cover insulating film is contrived and the surface is formed by the soft PSG films 10 and 12, so that even if the cover insulating film is in contact with a plastic mold package, the stress is small and generation of cracks can be restrained.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置に係り、特にその半導体チップ上を
被覆するカバー絶縁膜に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a cover insulating film that covers a semiconductor chip thereof.

周知のように、ICなどの半導体装置は、半導体チップ
が作成され、そのチップがパッケージに収納されている
As is well known, in a semiconductor device such as an IC, a semiconductor chip is manufactured and the chip is housed in a package.

この半導体チップはウェハープロセスによって作成され
るが、ウェハープロセスの最終工程ではウェハー上面に
カバー絶縁膜を被覆して、内部に設けた素子を保護した
後、ダイス状のチップに分割される。
This semiconductor chip is created by a wafer process, and in the final step of the wafer process, the upper surface of the wafer is coated with a cover insulating film to protect the elements provided inside, and then it is divided into dice-shaped chips.

従って、チップ表面のカバー絶縁膜はパッケージに収容
された後にも、十分に内部保護の役目を果たしており、
その保護性については十分に配慮されなければならない
Therefore, the cover insulating film on the surface of the chip sufficiently plays the role of internal protection even after it is housed in the package.
Sufficient consideration must be given to its protection.

[従来の技術] さて、第2図ta+は半導体チップの部分断面図を例示
しており、1はシリコン基板、2は二酸化シリコン(S
i02)膜、3はMO3+−ランジスタ素子、4は燐シ
リケートガラス(PSG)膜、5はアルミニウム配線、
6はカバー絶縁膜である。
[Prior Art] Now, FIG. 2 ta+ illustrates a partial cross-sectional view of a semiconductor chip, in which 1 is a silicon substrate, 2 is a silicon dioxide (S)
i02) film, 3 is MO3+- transistor element, 4 is phosphorus silicate glass (PSG) film, 5 is aluminum wiring,
6 is a cover insulating film.

カバー絶縁膜6には、PSG膜あるいはプラズマ窒化シ
リコン(プラズマSi  N  )膜が良く利用され、
これらは通常、化学気相底Ju(CVD)法によって、
約1μm程度の膜厚に被着される。
For the cover insulating film 6, a PSG film or a plasma silicon nitride (plasma SiN) film is often used.
These are usually produced by chemical vapor deposition Ju (CVD) method.
It is deposited to a film thickness of approximately 1 μm.

数々ある被着方法のうち、CVD法、特に減圧CVD法
は極めてカパーレイジ(被覆性)の良い被着方法として
知られている。
Among the many deposition methods, the CVD method, especially the low pressure CVD method, is known as a deposition method with extremely good coverage.

尚、プラズマ窒化シリコン膜とはプラズマCVD法で被
着した窒化シリコン膜と云う意味であって、窒化シリコ
ン膜を通常のCVD法によって被着すると、高温度の分
解反応のためアルミニウム配線5が熔融される。それを
避けるために、低温度の分解可能なプラズマCVD法で
被着するものである。
Note that the plasma silicon nitride film refers to a silicon nitride film deposited by a plasma CVD method, and when a silicon nitride film is deposited by a normal CVD method, the aluminum wiring 5 melts due to a high-temperature decomposition reaction. be done. In order to avoid this, the film is deposited using a low-temperature decomposable plasma CVD method.

[発明が解決しようとする問題点] ところで、被着したPSG膜はそれ自体に引張応力が生
じ、それによってクラック(割れ)が入り易い。また、
窒化シリコン膜は圧縮応力が生じて、そのためにクラッ
クが入り易くなる。従って、セラミックや金属のパンケ
ージの場合は、封止後には比較的問題はないが、例えば
、パッケージがプラスチックモールドの場合は、水分が
チップ内に侵入して信頼性上の致命的な問題が起こり易
い。
[Problems to be Solved by the Invention] Incidentally, the deposited PSG film itself generates tensile stress, which tends to cause cracks. Also,
Compressive stress occurs in the silicon nitride film, which makes it susceptible to cracking. Therefore, in the case of a ceramic or metal pancage, there are relatively no problems after sealing, but if the package is a plastic mold, for example, moisture can enter the chip and cause a fatal reliability problem. easy.

そのため、最近、プラスチックモールドパッケージを使
用する場合には、第2図山)に示す部分断面図のように
、カバー絶縁膜を膜厚1μmのpsG膜7と膜厚0.3
μmの窒化シリコン膜8とからなる複合膜にする構造が
採られている。そうすれば、引張と圧縮との両応力が相
殺してクランクの発生が減少し、信頼性が向上するから
である。
Therefore, recently, when using a plastic mold package, as shown in the partial cross-sectional view shown in Fig.
A composite film structure consisting of a silicon nitride film 8 of μm thickness is adopted. This is because both the tensile and compressive stresses cancel each other out, reducing the occurrence of cranks and improving reliability.

しかし、現実には必ずしもクラックが減少しないことが
判ってきた。それは、プラスチックモールドとカバー絶
縁膜とが接触すると、硬いモールドと窒化シリコン膜と
の間にストレスが生じ、それによってクラックが発生す
るためと考えられる。
However, it has become clear that cracks do not necessarily decrease in reality. This is thought to be because when the plastic mold and the cover insulating film come into contact, stress is generated between the hard mold and the silicon nitride film, which causes cracks to occur.

本発明は、このような問題点をなくするためのカバー絶
縁膜を提案するものである。
The present invention proposes a cover insulating film to eliminate such problems.

[問題点を解決するための手段1 その問題点は、第1絶縁体膜とは反対の応力が加わる第
2絶縁体膜を、前記第1絶縁体膜の間に挟んだ複合カバ
ー絶1i nが、半導体チップ上に設けられている半導
体装置によって解決される。
[Means for Solving the Problem 1] The problem is that a composite cover film in which a second insulating film to which stress opposite to that of the first insulating film is applied is sandwiched between the first insulating films is used. This can be solved by a semiconductor device provided on a semiconductor chip.

例えば、燐シリケート膜とは反対の応力が加わる窒化シ
リコン膜を、前記燐シリケート膜の間に ゛挟んだ複合
カバー絶縁膜が、半導体チップ上に設けられている半導
体装置によって解決される。
For example, a composite cover insulating film in which a silicon nitride film, which is subjected to stress opposite to that of the phosphosilicate film, is sandwiched between the phosphosilicate films is solved by a semiconductor device provided on a semiconductor chip.

[作用] 即ち、膜質の軟らかいpscl*によって、反対応力を
もった窒化シリコン膜を挟んだ3層膜からなるカバー絶
縁膜を設ける。かくして、カバー絶縁膜内の応力の均衡
を図り、且つ、表面を軟らかいPSG膜にすると、たと
えプラスチックモールドパッケージとカバー絶縁膜が接
触していても、ストレスは少なく、クラックは抑制され
る。
[Function] That is, a cover insulating film consisting of three layers sandwiching a silicon nitride film having opposite stress is provided using pscl* having a soft film quality. In this way, by balancing the stress within the cover insulating film and using a soft PSG film on the surface, even if the plastic mold package and the cover insulating film are in contact, the stress is small and cracks are suppressed.

[実施例〕 以下9図面を参照して実施例によって詳細に説明する。[Example〕 Examples will be described in detail below with reference to nine drawings.

第1図は本発明にかかるカバー絶縁膜を被覆した半導体
チップの部分断面図を例示しており、上記した第2図と
同一部材には同一記号が付しである。図示のように、カ
バー絶縁膜はPSG膜10゜窒化シリコン膜11.PS
G膜12を積層して、窒化シリコン膜11をサンドイッ
チ状に挟んだ3層からなる複合膜構造にする。
FIG. 1 illustrates a partial cross-sectional view of a semiconductor chip covered with a cover insulating film according to the present invention, and the same members as in FIG. 2 described above are given the same symbols. As shown in the figure, the cover insulating film is a PSG film 10 degrees, a silicon nitride film 11 degrees, and a silicon nitride film 11 degrees. P.S.
The G film 12 is laminated to form a composite film structure consisting of three layers sandwiching the silicon nitride film 11.

例えば、PSGllliloの膜厚0.5μm、窒化シ
リコン膜11の膜厚0.5μm、p3Q膜12の膜厚0
.5μmとして、この複合膜からなるカバー絶縁膜内の
応力のバランスをとり、理想的に内部応力を零にする。
For example, the thickness of the PSGllilo is 0.5 μm, the thickness of the silicon nitride film 11 is 0.5 μm, and the thickness of the p3Q film 12 is 0.
.. 5 μm, the stress within the cover insulating film made of this composite film is balanced and the internal stress is ideally reduced to zero.

そうすると、カバー絶縁膜にクラック発生はなくなる。This eliminates the occurrence of cracks in the cover insulating film.

この際、PSG膜の引張応力は燐の含有量によっても調
整できるから、それをも考慮して応力のバランスを図る
At this time, since the tensile stress of the PSG film can also be adjusted by the phosphorus content, the stress is balanced by taking this into account.

且つ、表面はPSG膜12が存在して軟らかいため、硬
いプラスチックモールド材、例えばエポキシ樹脂に接し
ても、このPSG膜12が緩衝剤となってストレスは解
消される。
In addition, since the surface is soft due to the presence of the PSG film 12, even if it comes into contact with a hard plastic molding material, such as an epoxy resin, the PSG film 12 acts as a buffer and relieves stress.

更に、このカバー絶縁膜の内面にはPSG膜10があり
、そのために半導体チップに設けたトランジスタ素子と
は軟らかく接し、また、PSG膜は可動イオンを吸収す
るバンシベーション効果が大きく、従前より知られてい
るそれらの利点は、本構造によっても決して減殺される
ものではない。
Furthermore, there is a PSG film 10 on the inner surface of this cover insulating film, which makes soft contact with the transistor elements provided on the semiconductor chip.The PSG film also has a large bancivation effect that absorbs mobile ions, which has been known for a long time. These advantages are in no way diminished by the present structure.

[発明の効果] 従って、上記説明から明らかなように、本発明にかかる
複合カバー絶縁膜を設けた半導体装置は、カパーレイシ
が良くなって高信頼化され、特にプラスチックモールド
型パッケージを有する半導体装置の信頼IQ−1′n1
J=に顕著に寄与するものである。
[Effects of the Invention] Therefore, as is clear from the above explanation, the semiconductor device provided with the composite cover insulating film according to the present invention has improved capacitance and is highly reliable, and is particularly suitable for semiconductor devices having plastic molded packages. Trust IQ-1'n1
It contributes significantly to J=.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明にかかる半導体チップの部分断面図を示
す図、 第2図(al、 (b)は何れも従来の半導体チップの
部分断面図を示す図である。 図において、 1はシリコン基板、   2は二酸化シリコン股、3は
MO3+−ランジスタ素子、 4ばPSG膜、    5はアルミニウム配線、6はカ
バー絶縁膜(psc膜あるいはプラズマ窒化シリコン膜
)、 10、12はpsc膜(カバー絶縁膜のうち)、11は
窒化シリコン膜(カバー絶縁膜のうち)を示している。 第1図 第2図 ら
FIG. 1 is a partial sectional view of a semiconductor chip according to the present invention, and FIGS. 2(a) and 2(b) are partial sectional views of a conventional semiconductor chip. In the figure, 1 is silicon. 2 is a silicon dioxide crotch, 3 is an MO3+- transistor element, 4 is a PSG film, 5 is an aluminum wiring, 6 is a cover insulating film (PSC film or plasma silicon nitride film), 10 and 12 are PSC films (cover insulating film) ), 11 indicates the silicon nitride film (of the cover insulating film).

Claims (2)

【特許請求の範囲】[Claims] (1)第1絶縁体膜とは反対の応力が加わる第2絶縁体
膜を、前記第1絶縁体膜の間に挟んだ複合カバー絶縁膜
が、半導体チップ上に設けられていることを特徴とする
半導体装置。
(1) A composite cover insulating film in which a second insulating film to which stress opposite to that of the first insulating film is applied is sandwiched between the first insulating films is provided on the semiconductor chip. semiconductor device.
(2)燐シリケートガラス膜とは反対の応力が加わる窒
化シリコン膜を、前記燐シリケート膜の間に挟んだ複合
カバー絶縁膜が、半導体チップ上に設けられていること
を特徴とする特許請求の範囲第1項記載の半導体装置。
(2) A composite cover insulating film in which a silicon nitride film to which a stress opposite to that of the phosphorus silicate glass film is applied is sandwiched between the phosphorus silicate films is provided on the semiconductor chip. A semiconductor device according to scope 1.
JP59202294A 1984-09-26 1984-09-26 Semiconductor device Pending JPS6179233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59202294A JPS6179233A (en) 1984-09-26 1984-09-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59202294A JPS6179233A (en) 1984-09-26 1984-09-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6179233A true JPS6179233A (en) 1986-04-22

Family

ID=16455157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59202294A Pending JPS6179233A (en) 1984-09-26 1984-09-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6179233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625839A1 (en) * 1988-01-13 1989-07-13 Sgs Thomson Microelectronics METHOD OF PASSIVATING AN INTEGRATED CIRCUIT
WO2014064873A1 (en) * 2012-10-22 2014-05-01 シャープ株式会社 Semiconductor device manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625839A1 (en) * 1988-01-13 1989-07-13 Sgs Thomson Microelectronics METHOD OF PASSIVATING AN INTEGRATED CIRCUIT
WO2014064873A1 (en) * 2012-10-22 2014-05-01 シャープ株式会社 Semiconductor device manufacturing method
JPWO2014064873A1 (en) * 2012-10-22 2016-09-08 シャープ株式会社 Manufacturing method of semiconductor device

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