JPS60233829A - Formation of insulation layer - Google Patents

Formation of insulation layer

Info

Publication number
JPS60233829A
JPS60233829A JP59007499A JP749984A JPS60233829A JP S60233829 A JPS60233829 A JP S60233829A JP 59007499 A JP59007499 A JP 59007499A JP 749984 A JP749984 A JP 749984A JP S60233829 A JPS60233829 A JP S60233829A
Authority
JP
Japan
Prior art keywords
film
films
insulation
substrate
insulation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59007499A
Other languages
Japanese (ja)
Inventor
Hiroshi Kitajima
洋 北島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59007499A priority Critical patent/JPS60233829A/en
Publication of JPS60233829A publication Critical patent/JPS60233829A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain the insulation layer exerting no effect on Si even through high-temperature processes by a method wherein three layers or more of CVD Si3N4 films produced in the same manner as an SiO2 film are provided by lamination in forming an insulation layer used for element isolation, interlayer insulation, and passivation. CONSTITUTION:On an Si substrate 11 provided with an SiO2 film 15 on the surface, three layers CVD SiO2 films 12 approx. 1,500Angstrom thick and plasma CVD Si3N4 films 13 approx. 2,000Angstrom thick are alternately combined into a field insulation film, and apertures 14 are bored by reactive ion etching. Such a formation of an element isolating insulation or a passivation film besides a field insulation film yields little lattice defect in the neighborhood of the edge of the aperture 14 at the time of selective epitaxial growth while filling the apertures 14. In other words, the laminated films cancel influences on the Si substrate 11 with each other, and the adjustment of stress becomes automatic.

Description

【発明の詳細な説明】 本発明は、素子分離、眉間絶縁、パッシベーション等に
用いられる絶縁層の形成法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming an insulating layer used for element isolation, glabellar insulation, passivation, etc.

シリコン・プロセスに用いられる絶縁膜は素子分離、層
間分離、パッシベーションに応用されている。このうち
素子分離への応用は熱酸化膜、０ＶＤ（Ｃｈｅｍｉｃａ
ｌ−’Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ　）酸化シリ
コン膜、ＯＶＤ窒化窒化シリコンボ用いられているが、
分離膜を形成した後、デバイス作製等のための高温プロ
セスを経るため、Ｓｉ部に加わる応力が間題となる。特
にパターンを形成した後では、局部的に応力集中が生じ
、欠陥発生の原因となることがある。Insulating films used in silicon processes are used for element isolation, interlayer isolation, and passivation. Of these, thermal oxide films, 0VD (Chemical
l-'Vapor Deposition) Silicon oxide film, OVD silicon nitride film is used,
After the separation film is formed, it undergoes a high-temperature process for device fabrication, so stress applied to the Si portion becomes an issue. Particularly after forming a pattern, local stress concentration may occur and cause defects.

本発明は、特に応力集中が欠陥発生、ひいてはデバイス
気性の劣化をもたらすような場合に、応力の少ない絶縁
層を形成することを特徴とするものである。The present invention is characterized in that it forms an insulating layer with low stress, especially in cases where stress concentration causes defects and ultimately deterioration of device properties.

以下、選択エピタキシャル成長用のフィールド絶縁膜へ
の適用を例にとシ詳細に説明する。The present invention will be described in detail below, taking as an example an application to a field insulating film for selective epitaxial growth.

第１図は従来法を示し、フィールド絶縁膜としてＯＶＤ
酸化酸化シリコ金膜いた場合の例を示す。Figure 1 shows the conventional method, in which OVD is used as the field insulating film.
An example is shown in which a silicon oxide gold film is used.

Ｓｉ基板１の上に薄い熱酸化シリコン膜２とＯＶＤ酸化
酸化シリコン膜形成し、反応性イオンエツチング等で開
口部４を設けた基板を用い、　８ｉＨ２Ｇ／２　＋ＨＣ
Ｌを原料ガスとして開口部４にシリコン膜を選択的にエ
ピタキシャル成長させた。透過電顕を用いて選択エピタ
キシャル成長膜を評価したところ、開口部の端付近に積
層欠陥や転位が発生しておシ、フィールド酸化膜の厚さ
が厚い程また開口部間の距離５が短い程欠陥密度は高か
った。この欠陥密度に及ぼすパターン構造から、開口部
の端付近に集中する応力が欠陥発生の一因と考えられた
。Using a substrate in which a thin thermally oxidized silicon film 2 and an OVD oxidized silicon oxide film are formed on a Si substrate 1 and an opening 4 is formed by reactive ion etching or the like, 8iH2G/2 +HC
A silicon film was selectively epitaxially grown in the opening 4 using L as a source gas. When selectively epitaxially grown films were evaluated using transmission electron microscopy, stacking faults and dislocations occurred near the edges of the openings, and the thicker the field oxide film and the shorter the distance between the openings, the more dislocations occurred near the edges of the openings. Defect density was high. From the effect of the pattern structure on the defect density, stress concentrated near the edge of the opening was thought to be a factor in the occurrence of defects.

この様な従来法の欠点を除くために、フィールド絶縁膜
としてＣＶＤ酸化シリコン膜及びプラズマＯＶＤ窒化シ
リコン膜を組合わせる方法を用いた。In order to eliminate such drawbacks of the conventional method, a method was used in which a CVD silicon oxide film and a plasma OVD silicon nitride film were combined as a field insulating film.

第２図は本発明の一実施例を示している。シリコン基板
１１の上に厚さ１５００ＡのＯＶＤ酸化酸化シリコンク
１２さ２０００　ＡのプラズマＯＶＤ窒化シリコン膜１
３を交互に３層ずつ組合わせたフィールド絶縁層を形成
し反応性イオンエツチングで開口部１４をを設けた。尚
８ｉ基板の表面は、汚染等を避けるため厚さ５００Ａの
熱酸化膜１５が残してあった。この熱酸化膜はエピタキ
シャル成長直前に除去した。FIG. 2 shows an embodiment of the invention. An OVD silicon oxide film 12 with a thickness of 1500 A and a plasma OVD silicon nitride film 1 with a thickness of 2000 A are deposited on a silicon substrate 11.
A field insulating layer was formed by alternately combining three layers of 3 layers, and an opening 14 was formed by reactive ion etching. Note that a thermal oxide film 15 with a thickness of 500 Å was left on the surface of the 8i substrate to avoid contamination and the like. This thermal oxide film was removed immediately before epitaxial growth.

この様な基板に従来例と同様にして選択エピタキシャル
成長を行って透過電顕で評価を行った。その結果、従来
例に於いて開口部の端付近に存在した格子欠陥はほとん
ど観察されなくなった。選択エピタキシャル成長膜に形
成したｐ−ｎダイオードの特性を比較したところ、逆バ
イアスでの耐圧やリーク特性に関しても顕著な改善が見
られた。Selective epitaxial growth was performed on such a substrate in the same manner as in the conventional example, and evaluation was performed using a transmission electron microscope. As a result, the lattice defects that existed near the edges of the opening in the conventional example were almost no longer observed. A comparison of the characteristics of pn diodes formed on selectively epitaxially grown films revealed significant improvements in reverse bias voltage resistance and leakage characteristics.

ＣＶＤ酸化シリコン膜の真性膜応力は引張応力であり、
プラズマＯＶＤ窒化シリコン膜は圧縮応力であることが
知られている。単一の膜をＳｉ基板上に形成した場合膜
厚が厚い程８ｉに及ぼす影響が大きくなる。しかし２ｓ
類の膜を積層することによって、２種類の膜の効果が打
消し合い、Ｓｉ基板に及ぼす影響が小さくなったためと
考えられる。しかも３層以上積層することで、応力の調
整もしやすい。The intrinsic film stress of the CVD silicon oxide film is tensile stress,
Plasma OVD silicon nitride films are known to be compressively stressed. When a single film is formed on a Si substrate, the thicker the film, the greater the influence on 8i. But 2s
This is thought to be because by stacking similar films, the effects of the two types of films cancel each other out, and the influence on the Si substrate becomes smaller. Moreover, by laminating three or more layers, it is easy to adjust the stress.

以上述べたように、本発明は素子分離用絶縁層としてＣ
ＶＤ酸化シリコン膜とプラズマＯＶＤ窒化シリコン膜と
を組合わせることによシ、それ以後の高温プロセスを経
てもＳｉへの影響が小さい絶縁層を得ることができた。As described above, the present invention uses C as an insulating layer for element isolation.
By combining the VD silicon oxide film and the plasma OVD silicon nitride film, it was possible to obtain an insulating layer that has little effect on Si even after subsequent high-temperature processes.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を説明するための概略断面図、第２図は
本発明の詳細な説明するだめの概略断面図。 １・・・・・・８１基板、　２・・・・・・熱酸化シリ
コン膜。 ３・・・・・・ＣＶＤ酸化シリコン膜。 ４・・・・・・選択エピタキシャル成長用の開口部。 ５・・・・・・開口部間の距離。 １１・・・・・・８ｉ基板、１２・・・・・・ＣＶＤ酸
化シリコン膜。 １３・・・・・・プラズマＯＶＤ窒化シリコン膜。 １４・・・・・・選択エピタキシャル成長用の開口部。 １５・・・・・・熱酸化シリコン膜。 第１図FIG. 1 is a schematic sectional view for explaining a conventional example, and FIG. 2 is a schematic sectional view for explaining the present invention in detail. 1...81 substrate, 2...Thermal oxidation silicon film. 3...CVD silicon oxide film. 4...Opening for selective epitaxial growth. 5... Distance between openings. 11...8i substrate, 12...CVD silicon oxide film. 13...Plasma OVD silicon nitride film. 14... Opening for selective epitaxial growth. 15...Thermal oxidation silicon film. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 絶縁層としてＯＶＤ法で形成した酸化シリコン膜とプラ
ズマＯＶＤ法で形成した窒化シリコン膜とをあわせて３
層以上嬢層することを特徴とする絶縁層形成法。A total of 3 silicon oxide films formed by OVD and silicon nitride films formed by plasma OVD are used as insulating layers.
A method for forming an insulating layer characterized by forming more than one layer.
JP59007499A 1984-01-19 1984-01-19 Formation of insulation layer Pending JPS60233829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59007499A JPS60233829A (en) 1984-01-19 1984-01-19 Formation of insulation layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59007499A JPS60233829A (en) 1984-01-19 1984-01-19 Formation of insulation layer

Publications (1)

Publication Number Publication Date
JPS60233829A true JPS60233829A (en) 1985-11-20

Family

ID=11667467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59007499A Pending JPS60233829A (en) 1984-01-19 1984-01-19 Formation of insulation layer

Country Status (1)

Country Link
JP (1) JPS60233829A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01207932A (en) * 1988-02-16 1989-08-21 Fuji Electric Co Ltd Semiconductor device
JPH01225326A (en) * 1988-01-13 1989-09-08 Sgs Thomson Microelectron Sa Method of passivation of integrated circuit
WO2010035481A1 (en) * 2008-09-26 2010-04-01 ローム株式会社 Semiconductor device and semiconductor device manufacturing method
JP2010080773A (en) * 2008-09-26 2010-04-08 Rohm Co Ltd Semiconductor device
JP2010080774A (en) * 2008-09-26 2010-04-08 Rohm Co Ltd Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225326A (en) * 1988-01-13 1989-09-08 Sgs Thomson Microelectron Sa Method of passivation of integrated circuit
JPH01207932A (en) * 1988-02-16 1989-08-21 Fuji Electric Co Ltd Semiconductor device
WO2010035481A1 (en) * 2008-09-26 2010-04-01 ローム株式会社 Semiconductor device and semiconductor device manufacturing method
JP2010080773A (en) * 2008-09-26 2010-04-08 Rohm Co Ltd Semiconductor device
JP2010080774A (en) * 2008-09-26 2010-04-08 Rohm Co Ltd Semiconductor device
US9735110B2 (en) 2008-09-26 2017-08-15 Rohm Co., Ltd. Semiconductor device and semiconductor device manufacturing method

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