EP0325344B1 - Transfer circuit for signal lines - Google Patents

Transfer circuit for signal lines Download PDF

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Publication number
EP0325344B1
EP0325344B1 EP89300051A EP89300051A EP0325344B1 EP 0325344 B1 EP0325344 B1 EP 0325344B1 EP 89300051 A EP89300051 A EP 89300051A EP 89300051 A EP89300051 A EP 89300051A EP 0325344 B1 EP0325344 B1 EP 0325344B1
Authority
EP
European Patent Office
Prior art keywords
transistor
mis transistor
electrode
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89300051A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0325344A2 (en
EP0325344A3 (en
Inventor
Atuo Koshizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0325344A2 publication Critical patent/EP0325344A2/en
Publication of EP0325344A3 publication Critical patent/EP0325344A3/en
Application granted granted Critical
Publication of EP0325344B1 publication Critical patent/EP0325344B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Definitions

  • the present invention relates to a transfer circuit for signal lines and utilized, for example, for selectively transferring data on one of a plurality of local data buses to a common data bus.
  • a memory cell array is divided into a plurality of blocks, to obtain a low power consumption or a high speed processing.
  • one of a plurality of local buses connected to the memory cell array block must be selected and the data thereon transferred to a common data bus. This selection and transfer are carried out by a transfer gate circuit.
  • a transfer circuit for signal lines using a transfer gate since all of the transistors are MIS (metal insulator semiconductor) transistors, the resistance in a conductive state is relatively high, the overdrive voltage is low, and the local data bus has a large electrostatic capacity due to the connection of many memory cells. Therefore, a time constant for a charge in the bus is long, and a problem arises in that it takes a long time to transfer data from the local data bus to the common data bus.
  • MIS metal insulator semiconductor
  • a transfer circuit for controlling a signal transfer between a first signal line and a second signal line in response to a control signal comprising a first MIS transistor including a first electrode connected to the first signal line, a second electrode, and a gate electrode; a second MIS transistor including a first electrode connected to the second electrode of the first MIS transistor, a second electrode connected to the second signal line, and a gate electrode; and a bipolar transistor including a base electrode connected to the first signal line, a first electrode connected to a power supply line, and a second electrode connected to the first electrode of the second MIS transistor; the gate electrodes of the first MIS transistor and the second MIS transistor being controlled in response to the control signal such that the first MIS transistor and the second MIS transistor operate in a complementary manner.
  • the present invention may provide a high speed transfer circuit for signal lines by using a bipolar transistor and MIS transistors.
  • SRAM static random access memory
  • blocks BLK1 and BLK2 enclosed by broken lines are divided into memory cell array blocks (shown as a partially abbreviated diagram).
  • Each block comprises memory cells (MC's) as memory elements, and in each block, one column is selected by column selection circuits controlled by signals CA0 to CA n from a decoder, and one word line (WL0 to WL m ) is selected by the decoder. Then, data is read from an MC arranged at a cross point of the word line and a pair of bit lines (e.g.
  • the transfer circuit for signal lines comprises transistors Q21 , Q22 , Q31 , and Q32 , which are controlled by a signal BS1 or BS2.
  • Write data (D in ) for this SRAM is supplied to write amplifiers (WRITE AMP 1 and 2) through a data-in buffer (DATA-IN BUF) and data bus (DBW, DBW ).
  • One memory cell array block is selected by the selection of a write amplifier controlled by a control signal (WS1 or WS2) and the data is supplied to the selected MC through the local data bus.
  • FIG. 2 shows a portion of the SRAM in Fig. 1 in detail.
  • Data from each MC is supplied to local data buses (DB1 , DB 1; DB2 , DB 2) through a transfer gate circuit TG B , which comprises transistors Q11 and Q12 , and one of the transfer gate circuits (TG1 , TG2) is selected by a block selection control signal (BS1 or BS2) and is made conductive to the common data bus as a transfer circuit for signal line.
  • DB1 , DB 1; DB2 , DB 2 a transfer gate circuit TG B , which comprises transistors Q11 and Q12 , and one of the transfer gate circuits (TG1 , TG2) is selected by a block selection control signal (BS1 or BS2) and is made conductive to the common data bus as a transfer circuit for signal line.
  • BS1 or BS2 block selection control signal
  • the TG1 comprises MIS transistors Q21 and Q22 , and each transistor is made conductive by the block selection control signal BS1.
  • MIS transistors Q23 and Q24 are used to apply a voltage, e.g., Vcc (5 volts), through an effective resistance, so that a floating state thereof does not exist when the local bus is at the non-selection state.
  • the transfer gate TG2 comprises MIS transistors Q31 and Q32 , the power source voltage Vcc is connected to the local data bus (DB2 , DB 2) through MIS transistors Q33 and Q34 , and the operation thereof is the same as that of the TG1.
  • FIG. 3 A transfer circuit for signal lines according to a first embodiment of the invention is explained with reference to Fig. 3. Note, in Fig. 3, a portion of the SRAM is abbreviated as in Fig. 2.
  • a memory cell is a memory element in the SRAM as shown in Figs. 1 and 2 and is a flip-flop circuit shown at the top of Fig. 3.
  • the memory cell for example, comprises four MIS transistors and two resistors, and two series-connected resistors and transistors are arranged in parallel between the power source and ground. A drain of one of the transistors is cross-connected to a gate of another transistor, and vice versa. The gate of each transistor is connected to a MIS transistor to be selected by a word line (WL) and to be connected to a respective bit line.
  • WL word line
  • a pair of bit lines (BL0 , BL 0) is connected to a local data bus (DB1 , DB 1) through a transfer gate circuit TG B , which comprises transistors Q11 and Q12 as a column selection circuit.
  • Another pair of bit lines from another memory cell array block is connected to a local data bus (e.g. DB2 , DB 2) in the same way.
  • the local data bus (DB1 , DB 1) is connected to the common data bus through a transfer gate circuit TG11 , according to the first embodiment of the invention, and a selection signal BS 1 makes the transfer gate circuit conductive or disconnects same.
  • the local data bus (DB2 , DB 2) and the local data bus belonging to other blocks are connected and controlled in the same way.
  • the transfer gate circuit TG11 (transfer circuit assembly) is explained.
  • the TG11 comprises a symmetrical circuit for transmitting a complementary pair of signals.
  • a half of the symmetrical circuit is explained, but the other half thereof is exactly the same.
  • the half circuit comprises a bipolar transistor (QB11 or QB12), an n channel MIS transistor (QN31 or QN32), and a p channel MIS transistor (QP33 or QP34).
  • one of the local data bus signal lines DB1 is connected to a base of the NPN type bipolar transistor QB11; a collector of the transistor QB11 is connected to the power source Vcc; a source of the transistor QN31 is connected to a source of the transistor QP33; a gate of the transistor QN31 is connected to a gate of the transistor QP33; a drain of the transistor QN31 is connected to the base of the transistor QB11; and, a drain of the transistor QP33 is connected to the common data bus DB.
  • the transistor QB11 is replaced by the transistor QB12
  • the transistor QN31 is replaced by the transistor QN32
  • the transistor QP33 is replaced by the transistor QP34
  • the drain of the transistor QP34 is connected to the common data bus DB .
  • the remaining circuit constitution of the another signal line of the local data bus is the same as that of one of the local data bus signal lines. Note, the interconnected MIS transistor gates are supplied with the selection signal BS 1.
  • the line to be transferred is not complementary to a bus line but is an individual line, a half circuit application in the symmetrical circuit is sufficient.
  • the selection signal BS 1 is at a "low” level, the n channel MIS transistors QN31 and QN32 are OFF, and the p channel MIS transistors QP33 and QP34 are ON (conductive).
  • the data signal on the local data bus DB1 is applied to the base of the transistor QB11 , the current is amplified, and the data is transferred to the common data bus DB instantly through the emitter of the transistor QB11 and the transistor QP33.
  • a data signal on the local data bus DB 1 is applied to the base of the transistor QB12 , the current is amplified, and the data is transferred to the common data bus DB instantly through the emitter of the transistor QB12 and the transistor QP34.
  • the selection signal BS 1 is at a high level, the n channel transistors QN31 and QN32 are ON, and the p channel transistors QP33 and QP34 are OFF. Accordingly, the transistor Q11 and QB12 are made OFF by a short circuit between the base and emitter thereof, and thus the data signals from the local data bus (DB1 , DB 1) are completely disconnected.
  • the transistor QN31 since the transistor QN31 is short circuited during the non-selection time, delay of the conductive operation at the next step is prevented due to the absence of an emitter voltage higher than the base voltage in the transistor QB11.
  • the bipolar transistor QB11 amplifies the signal current from the MC by using an emitter follower, the transistor QP33 supplies the electric current from the transistor QB11 to the common data bus DB when the transfer circuit for signal lines is in a selection state, and the transistor QP33 disconnects the signal from the MC so that the signal from the bus DB1 does not reach the bus DB when the transfer circuit is in a non-selection state.
  • the common data bus is connected to a sense amplifier SA, and the data is output through an output buffer circuit.
  • a pull-down circuit PD is connected to the common data bus.
  • This circuit PD comprises two MIS transistors Q15 and Q16 , and a drain of the transistor Q15 is connected to the common data bus DB and a drain of the transistor Q16 is connected to the common data bus DB .
  • Sources of the transistors Q15 and Q16 are grounded and bases of the transistors Q15 and Q16 are connected to the power source V1 or Vcc.
  • the circuit PD lowers the bus voltage when the voltage of the common data bus is changed from high to low.
  • the channel widths of the transistors Q15 and Q16 are made narrower than that of the MIS transistor QP33 or the like.
  • the voltage levels of connecting points between the sources of the transistors QN31 and QP33 and between the sources of the transistors QN32 and QP34 are A and B, respectively, as shown in Fig. 3, the voltage levels of the connecting points, of the local data bus (DB2 , DB 2) and of the common data bus (DB , DB ) are as shown in Fig. 7.
  • the waveforms in Fig. 7 are generated when a high level of the selection signal is transferred from BS 2 to BS 1.
  • the axis of the ordinates shows a voltage (volt) and the quadrature axis shows the time (t).
  • FIG. 4 A circuit diagram of a transfer circuit for signal lines according to a second embodiment of the invention is shown in Fig. 4.
  • This circuit comprises two NPN type bipolar transistors QB11 and QB12 , two p channel MIS transistors QP41 and QP42 , and two n channel MIS transistor QN43 and QN44.
  • the local data bus DB1 is connected to the base of the transistor QB11 and a drain of the transistor QP41 , and the collector of the transistor QB11 is connected to the power source Vcc.
  • Sources of the transistors QP41 and QN43 are interconnected and the connecting point is connected to the emitter of the transistor QB11 , and a drain of transistor QN43 is connected to the common data bus DB.
  • Gates of the transistors QP41 and QN43 are interconnected and are applied with a selection signal BS.
  • the local data bus DB 1 is connected to the base of the transistor QB12 and a drain of the transistor QP42 , the collector of the transistor QB12 is connected to the power source Vcc, sources of the transistors QP42 and QN44 are interconnected and the connecting point is connected to the emitter of the transistor QB12 , and a drain of the transistor QN44 is connected to the common data bus DB .
  • Gates of the transistors QP42 and QN44 are interconnected and are applied with a selection signal BS. In this circuit, during the selection (i.e. the signal BS is high level), the transistors QP41 and QP42 are OFF and the transistors QN43 and QN44 are ON. The operation of this circuit is the same as that of the first embodiment.
  • FIG. 5 A circuit diagram of a transfer circuit for signal lines according to a third embodiment of the invention is shown in Fig. 5.
  • This circuit comprises two NPN type bipolar transistors QB11 and QB12 and four n channel MIS transistors QN51 , QN52 , QN53 , and QN54.
  • the local data bus DB1 is connected to the base of the transistor QB11 and a drain of the transistor QN51 , the collector of the transistor QB11 is connected to the power source Vcc, sources of the transistors QN51 and QN53 are interconnected and the connecting point is connected to the emitter of the transistor QB11 , and a drain of the transistor QN53 is connected to the common data bus DB.
  • a gate of the transistors QN51 is supplied with the signal BS
  • a gate of the transistor QN53 is supplied with the signal BS (inverted BS signal).
  • the local data bus DB 1 is connected to the base of the transistor QB12 and a drain of the transistor QN52 , the collector of the transistor QB12 is connected to the power source Vcc, sources of the transistors QN52 and QN54 are interconnected and the connecting point is connected to the emitter of the transistor QB12 , and a drain of the transistor QN54 is connected to the common data bus DB .
  • a gate of the transistor QN52 is supplied with the selection signal BS and a gate of the transistor QN54 is supplied with the selection signal BS.
  • the transistors QN51 and QN52 are OFF and the transistors QN53 and QN54 are ON.
  • the operation of this circuit is the same as that of the first embodiment.
  • FIG. 6 A circuit diagram of a transfer circuit for signal lines according to a fourth embodiment of the invention is shown in Fig. 6.
  • This circuit comprises two NPN type bipolar transistors QB11 and QB12 and four p channel MIS transistors QP61 , QP62 , QP63 , and QP64.
  • the local data bus DB1 is connected to the base of the transistor QB11 and a drain of the transistor QP61 , the collector of the transistor QB11 is connected to the power source Vcc, sources of the transistors QP61 and QP63 are interconnected and the connecting point is connected to the emitter of the transistor QB11 , and a drain of the transistor QP63 is connected to the common data bus DB.
  • a gate of the transistor QP61 is supplied with the selection signal BS, and a gate of the transistor QP63 is supplied with the selection signal BS .
  • the local data bus DB 1 is connected to the base of the transistor QB12 and a drain of the transistor QP62 , the collector of the transistor QB12 is connected to the power source Vcc, sources of the transistors QP62 and QP64 are interconnected and the connecting point is connected to the emitter of the transistor QB12 , and a drain of the transistor QP64 is connected to the common data bus DB .
  • a gate of the transistor QP62 is supplied with the selection signal BS and a gate of the transistor QP64 is supplied with the selection signal BS . In this circuit, during the transfer state the transistors QP61 and QP62 are OFF and the transistors QP63 and QP64 are ON. The operation of this circuit is the same as that of the first embodiment.
  • a pair of transfer circuits is used with transfer buses supplied with a pair of complementary signals, but this transfer circuit for signal lines can function using only one of the pair of circuits, to transfer data from one signal line to another signal line.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
EP89300051A 1988-01-11 1989-01-05 Transfer circuit for signal lines Expired - Lifetime EP0325344B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2531/88 1988-01-11
JP63002531A JPH01184694A (ja) 1988-01-11 1988-01-11 信号線切り替え回路

Publications (3)

Publication Number Publication Date
EP0325344A2 EP0325344A2 (en) 1989-07-26
EP0325344A3 EP0325344A3 (en) 1992-02-26
EP0325344B1 true EP0325344B1 (en) 1994-03-09

Family

ID=11531964

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89300051A Expired - Lifetime EP0325344B1 (en) 1988-01-11 1989-01-05 Transfer circuit for signal lines

Country Status (4)

Country Link
US (1) US4876467A (ko)
EP (1) EP0325344B1 (ko)
JP (1) JPH01184694A (ko)
KR (1) KR920008054B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134319A (en) * 1990-01-10 1992-07-28 Fujitsu Limited Bicmos differential amplifier having improved switching speed

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570993A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Memory circuit
JPS62230221A (ja) * 1986-03-31 1987-10-08 Toshiba Corp バツフア回路
JPS63209220A (ja) * 1987-02-26 1988-08-30 Toshiba Corp インバ−タ回路

Also Published As

Publication number Publication date
EP0325344A2 (en) 1989-07-26
JPH01184694A (ja) 1989-07-24
KR920008054B1 (ko) 1992-09-22
KR890012468A (ko) 1989-08-26
US4876467A (en) 1989-10-24
EP0325344A3 (en) 1992-02-26

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