EP0324020A1 - Verfahren zur herstellung aufgefüllter gräben - Google Patents

Verfahren zur herstellung aufgefüllter gräben

Info

Publication number
EP0324020A1
EP0324020A1 EP19880906932 EP88906932A EP0324020A1 EP 0324020 A1 EP0324020 A1 EP 0324020A1 EP 19880906932 EP19880906932 EP 19880906932 EP 88906932 A EP88906932 A EP 88906932A EP 0324020 A1 EP0324020 A1 EP 0324020A1
Authority
EP
European Patent Office
Prior art keywords
trench
glass
layer
spin
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880906932
Other languages
English (en)
French (fr)
Inventor
Shane Duncan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Semiconductors Ltd
Original Assignee
Plessey Overseas Ltd
Plessey Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Ltd, Plessey Semiconductors Ltd filed Critical Plessey Overseas Ltd
Publication of EP0324020A1 publication Critical patent/EP0324020A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Definitions

  • the present invention relates to a method of providing refilled trenches and in particular to a method of refilling deep trenches with spin-on glass.
  • trenches in integrated circuit (i.c) technology is a known technique for providing component isolation and mechanical stability.
  • the trenches are formed by etching through the epitaxial layer and buried N+ layer.
  • the trench is then refilled with a refill material which is usually polysilicon.
  • One such method comprises refilling the trench completely with polysilicon.
  • a grain boundary is formed down the middle of the trench since the deposition of polysilicon extends from the side walls of the trench inwards.
  • This grain boundary is fissile such that during field oxidation, the oxide may extend into the trench along the grain boundary.
  • the oxide acts on the polysilicon, creating pressure on the sidewalls of the trench which can result in defects being formed in the epitaxial layer. Attempts have ' been made to reduce this pressure by depositing a thinner layer of polysilicon on the sidewalls. However, it has proven impractical to control the required thickness for minimising pressure on the sidewalls whilst ensuring that the trench is filled.
  • a more preferable refill material is spin-on glass since it can be applied by a less specialised process and is a material which is self-planarising.
  • spin-on glass is a known material in the art and comprises polymethyle syloxane.
  • the present invention seeks to provide a method for refilling deep trenches using spin-on glass whilst substantially eliminating the aforementioned disadvantages.
  • a method of providing refilled trenches comprises: etching a trench; growing a passivating layer for lining the trench: providing fillets along each respective sidewall of the trench contiguous with the passivating layer, having a void therebetween; and filing the said void with spin-on glass.
  • the fillets are provided by depositing a layer of polysilicon and anisotropically etching the said layer.
  • the method may comprise the following steps of curing the spin-on glass and etching the spin-on glass, thereby providing a planarised trench surface.
  • Figures 1, 2, 3, and 4 are schematic cross-sections of trenches at various stages of the method in accordance with a first embodiment
  • Figures 5, 6, and 7 are schematic cross-sections of trenches at various stages of the method in accordance with a second embodiment.
  • a trench 2 is plasma etched through the epitaxial layer 4 and buried N+ layer 6.
  • the dimensions of the trench are typically 5 ⁇ m deep and 2 ⁇ m wide.
  • the trench 2 is introduced to provide component isolation in the integrated circuit, the components (not shown) being disposed in the epitaxial layer 4.
  • a layer of thermal oxide 8 is grown to provide a suitable passivating layer.
  • This layer of thermal oxide 8 typically comprises a homogenous, amorphous material possessing a structure of silicon-oxygen bonds grown at a high temperature.
  • a thick layer of polysilicon 10 is then deposited usually by a low pressure chemical vapour deposition (LPCVD) process.
  • LPCVD low pressure chemical vapour deposition
  • This layer is then anisotropically etched in a vertical direction to form large sidewall fillets 12 running down the sidewalls of the trench 2 as shown in figure 2.
  • the width of the fillets 12 is approximately 0.7 ⁇ m.
  • These fillets 12 leave a void 13 running down the middle of the trench 2, of a width approximately 0.5 ⁇ m.
  • the trench 2 is etched through the epitaxial layer 4 and buried N+ layer 6.
  • a passivating layer is provided by growing the layer of thermal oxide 8.
  • a layer of silicon nitride 16 is then deposited, followed by a thin layer of polysilicon 10.
  • the depth of the polysilicon is approximately 0.3 ⁇ m.
  • This layer of polysilicon 10 is anisotropically etched in a vertical direction, to leave thin sidewall fillets 18 as shown in Figure 6.
  • a void 20 remains therebetween running down the trench 2, of an approximate width 1.4 ⁇ m.
  • the width of this void 20 is too wide to avoid cracking of the spin-on glass during the curing process, if introduced at this stage. Therefore, the fillets 18 are completely oxidised and swell so as to leave a narrower void 20, see Figure 7.
  • the layer of silicon nitride 16 protects the surface and sidewalls of the trench 2 from this oxidation process.
  • the void 20 is then filled with spin- on glass, cured at a high temperature and then etched back to provide a planarised trench 2.
  • spin-on glass as a refill material ensures low isolation capacitance between adjacent buried N+ layers whilst improving surface planarity after refill. Furthermore, the probability of defect formation in the eptaxial layer 4 is reduced.
  • this is due to a reduced exposure area of the polysilicon fillets 12 to any subsequent field oxidation. Also if the top of the fillets 12 do become oxidised, then the resultant pressure tends to act on the spin-on glass 14 rather than the sidewalls of the trench 2.
  • the refill material in the trench namely the fillets 18 and the spin-on glass 20
  • the refill material in the trench namely the fillets 18 and the spin-on glass 20
  • the problem of defect formation is obviated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
EP19880906932 1987-07-24 1988-07-22 Verfahren zur herstellung aufgefüllter gräben Withdrawn EP0324020A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8717612A GB2207281B (en) 1987-07-24 1987-07-24 A method of providing refilled trenches
GB8717612 1987-07-24

Publications (1)

Publication Number Publication Date
EP0324020A1 true EP0324020A1 (de) 1989-07-19

Family

ID=10621273

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880906932 Withdrawn EP0324020A1 (de) 1987-07-24 1988-07-22 Verfahren zur herstellung aufgefüllter gräben

Country Status (4)

Country Link
EP (1) EP0324020A1 (de)
JP (1) JPH02500153A (de)
GB (1) GB2207281B (de)
WO (1) WO1989001236A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931409A (en) * 1988-01-30 1990-06-05 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having trench isolation
US5244827A (en) * 1991-10-31 1993-09-14 Sgs-Thomson Microelectronics, Inc. Method for planarized isolation for cmos devices
US5472022A (en) * 1993-11-02 1995-12-05 Genentech, Inc. Injection pen solution transfer apparatus and method
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US5439846A (en) * 1993-12-17 1995-08-08 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
SE520115C2 (sv) * 1997-03-26 2003-05-27 Ericsson Telefon Ab L M Diken med plan ovansida
US6063693A (en) * 1998-03-23 2000-05-16 Telefonaktiebolaget Lm Ericsson Planar trenches
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4385975A (en) * 1981-12-30 1983-05-31 International Business Machines Corp. Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate
JPS60121737A (ja) * 1983-12-06 1985-06-29 Nec Corp 半導体装置の素子分離方法
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8901236A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches

Also Published As

Publication number Publication date
GB2207281B (en) 1992-02-05
GB8717612D0 (en) 1987-09-03
JPH02500153A (ja) 1990-01-18
GB2207281A (en) 1989-01-25
WO1989001236A1 (en) 1989-02-09

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