EP0304657A2 - Active matrix cell and method of manufacturing the same - Google Patents
Active matrix cell and method of manufacturing the same Download PDFInfo
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- EP0304657A2 EP0304657A2 EP88112172A EP88112172A EP0304657A2 EP 0304657 A2 EP0304657 A2 EP 0304657A2 EP 88112172 A EP88112172 A EP 88112172A EP 88112172 A EP88112172 A EP 88112172A EP 0304657 A2 EP0304657 A2 EP 0304657A2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Definitions
- the present invention relates to an active matrix cell driven by a thin-film field effect transistor (to be referred to as a TFT hereinafter) used in a liquid crystal display, and a method of manufacturing the active matrix cell.
- a thin-film field effect transistor to be referred to as a TFT hereinafter
- a liquid crystal display (LCD) using a liquid crystal as a display medium has been studied and developed in place of a CRT display since the LCD has a small depth and low power consumption and is compact as compared with the CRT display, and some liquid crystal display models are popular in practical applications.
- an active matrix type liquid crystal display has received a great deal of attention.
- TFTs are arranged in each pixel to drive the pixel.
- a typical active matrix type liquid crystal display has a structure wherein a liquid crystal is sandwiched between an active matrix substrate having TFTs thereon and a counter substrate, an entire surface of which receives a uniform potential.
- Basic units consisting of TFTs and pixel electrodes are arranged on the active matrix substrate in a matrix form.
- Scanning lines for controlling the TFTs and data lines for supplying data to the pixel electrodes are arranged in a matrix form along the X and Y directions.
- the repetition unit is defined as an active matrix cell herein.
- reference numeral 5 denotes a source of the TFT 3; 6, a drain of the TFT 3; 7, an intersection region between the data and scanning lines 1 and 2. It should be noted that the drain and source of a general TFT are not discriminated from each other.
- an active matrix substrate having TFTs formed thereon is used in an active matrix type liquid crystal display, the fabrication process is more complex than a simple multiplex type liquid crystal display in which a liquid crystal is sandwiched between an X-direction wiring substrate and a Y-direction wiring substrate. Therefore, the product yield of the active matrix type displays is undesirably decreased, and it is difficult to provide a high-quality large display at low cost.
- the number of masks under discussion is the number required for manufacturing the active matrix substrate. Therefore, masks required for forming an alignment layer are excluded from the number of masks.
- a conventional active matrix substrate manufacturing method from which the manufacturing steps are reduced will be described below.
- the scanning and data lines are indispensable elements in the active matrix substrate. Therefore, two masks for the scanning and data lines cannot be eliminated.
- the active matrix cell can be manufactured by only a first mask (non-hatched region) for forming data lines 10 and a pixel electrode 11 and a second mask (region of hatches inclined upward to the right) for forming a scanning line 12.
- Fig. 8B is a sectional view of the active matrix cell in Fig. 8A along the line VIIIB - VIIIB′ thereof.
- Reference numerals 13a and 13b denote indium-tin-oxide (to be referred to as ITO hereinafter) conductive films; 14a and 14b, n-type amorphous silicon (to be referred to as n+a-Si hereinafter); 15, amorphous silicon (to be referred to as a-Si hereinafter); 16, silicon oxide (SiO2) serving as a gate insulating film; and 17, an aluminum (to be referred to as Al hereinafter) wiring.
- ITO indium-tin-oxide
- a parasitic TFT region 19 as an unnecessary TFT region in addition to a TFT region 18 serving as a necessary active element is undesirably formed under the scanning line 12, resulting in a decisive drawback. That is, when a channel length of the parasitic TFT region 19 is large, a conductivity is small and the display characteristics are not so adversely affected. However, when the channel length is decreased, the display characteristics are greatly degraded.
- the three-mask process is a process wherein a TFT formation mask is added to the data line mask. For this reason, each TFT is limited to the necessary region and a parasitic TFT region can be eliminated, thus manufacturing an ideal structure.
- Figs. 9A to 9E are sectional views showing steps in manufacturing an active matrix cell according to the three-mask process, as described in "A 640 x 400 Pixel Active-Matrix LCD Using a-Si TFT's", T. Sunata, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-33, No. 8, 1986, pp. 1218 - 1221.
- a protective layer 21 is formed on a glass substrate 20
- a transparent conductive film to be used for source and drain of the TFT the data line, and the pixel electrode is deposited.
- an ITO film is used and patterned to form a transparent conductive film 22 (first mask), as shown in Fig. 9A.
- a phosphorus-doped n+a-Si film 23 is selectively formed on the transparent conductive film 22 to form the source and and drain of the TFT, as shown in Fig. 9B.
- An a-Si film is deposited and patterned to form a TFT semiconductor region 24 (second mask).
- the a-Si film and the n+a-Si film excluding the TFT region 24 are simultaneously removed, as shown in Fig. 9C.
- a silicon nitride (to be referred to as SiN x hereinafter) film 25 serving as a gate insulating film is deposited.
- a metal film e.g., an Al film is deposited and patterned to obtain a scanning line 26 so as to include the gate electrode (third mask), as shown in Fig. 9E.
- the active matrix cell is formed using first to third masks in this process. Since the TFT thus formed has a gate electrode as the uppermost layer, this TFT is called a top gate staggered TFT.
- the drain and source of the TFT consist of lead lines for externally extracting currents and regions for effectively injecting only necessary carrier into the semiconductor.
- source and drain regions having a high impurity concentration i.e., n+ or p+ region
- n+a-Si film is used for source and drain to be deposited separately and additionally in a TFT using a-Si.
- a photolithographic step and an a-Si film etching step are required between formation of the a-Si film serving as a TFT active region and formation of the SiN x film serving as the gate insulating film.
- An important interface for determining characteristics of a metal-insulator-semiconductor (MIS) field effect TFT tends to be contaminated. It is therefore difficult to form a high-mobility TFT with high reproducibility.
- the transparent conductive film 22 as the lowermost layer serves as the data line. When a display area is to be increased, the resistance of the transparent conductive film 22 must be reduced. However, the thickness of the transparent conductive film 22 cannot be extremely increased due to the following reason.
- a film formed by normal plasma chemical vapor deposition (to be referred to as a PCVD hereinafter) used as a deposition method of the a-Si film has poor step coverage at the pattern edge and causes degradation of the TFT characteristics. In particular, when a step height increases, these affections become severe.
- through holes must be formed in the SiN x film 25 existing on the entire surface and another metal wiring pattern must be formed to decrease the data line resistance.
- this process requires at least an additional mask for forming the through holes, thus losing the advantage of the three-mask process. Terminals must be extracted from the peripheral portion of the substrate to apply voltages to the data lines formed of the transparent conductive film 22 as the lowermost layer in the above process.
- aninsulating film should not exit on the peripheral transparent conductive film 22 portion.
- a metal mask In order to manufacture an active matrix using the above mentioned active matrix cell, a metal mask must be prepared not to deposit the SiN x 25 on the peripheral transparent conductive film 22 portion during deposition of the SiN x 25 serving as a gate insulating film. The metal mask is aligned with the pattern on the substrate with a microscope. Poor mask alignment and poor contact between the metal mask and the substrate cause undesirable deposition of the insulating film under the metal mask.
- a principal object of the present invention to provide an active matrix cell and a method of manufacturing the same with good reproducibility at a high yield and, more particularly, to provide an active matrix cell and a method of manufacturing the same, wherein a wiring pattern is formed on a substantially smooth surface, and possibilities of a disconnection and a short circuit by poor step coverage can be greatly reduced.
- an active matrix cell comprising a first conductor group formed on a transparent substrate and constituting a source and a drain of a field effect thin-film transistor, part of a data line, and a pixel electrode, two-layered regions formed on the transparent substrate and consisting of a semiconductor film and a first insulating film which is formed on the semiconductor film and an area of the first insulating film in the two-layered regions has substantially the same area as that of the semiconductor film, a second insulating film contacting a side surface of the two-layered regions, having substantially the same thickness as that of the two-layered regions, and covering a region excluding the two-layered regions and the first conductor group, and a second conductor group serving as a scanning line and part of the data line, wherein one of the two-layered regions connects the source and the drain, partially overlaps the source and the drain so as to serve as an active region of the thin-film transistor, and the other of the two-layered regions overlaps the data line so
- Figs. 1, 2A, and 2B show an active matrix cell according to an embodiment of the present invention.
- the active matrix cell of this embodiment includes a data line 1, a scanning line 2, a field effect TFT 3, and a pixel electrode 4.
- the active matrix cell comprises: a protective film 101 formed on a transparent glass substrate 100 to prevent impurity contamination of a TFT 3; a first conductive film or conductor group 102 consisting of a multilayered film of an ITO film, an Mo film, and an n+a-Si film, which serve a source 5 of the TFT 3, a drain 6 of the TFT 3, part of the data line 1, and the pixel electrode 4; two-layered regions 103A, 103B consisting of an a-Si semiconductor film 103a partially overlapping the first conductor group 102 and an SiN x first insulating film or insulator 103b formed on the semiconductor 103a so as to have a same area as that of the semiconductor; a second insulating film or insulator 104 which consists of a photosensitive polyimide, contacts the side surface of the two-layered regions 103A, 103B, has substantially the same thickness as that of the two-layered regions, and covers a region excluding the two-layered regions 103A,
- the two-layered region 103A constitutes an active region of the TFT 3 by connecting the source 5 and the drain 6.
- the two-layered region 103B insulates the intersection region 7 between the data line 1 and the scanning line 2 and has an area larger than an area defined by the widths of adjacent data and scanning lines 1 and 2.
- One second conductor of the second conductor group 105 partially overlap the source 5 and the drain 6 to have a width larger than the distance between the source 5 and the drain 6 and is formed between the source 5 and the drain 6 to constitute the scanning line 2 including the gate electrode of the TFT 3, as shown in Fig. 1.
- the other of the second conductor group 105 is in contact with the data line 1 of the first conductive film to decrease the resistance of the data line 1 while being not connected to the scanning line 2.
- the data line 1 is constituted by a multilayered film consisting of one first conductor of the first conductor group 102 and parts of the second conductor group 105.
- Figs. 3A, 3B, and 3C show the layout patterns of masks required for forming the active matrix cell structure. The required number of masks is three, and these masks correspond to those in Fig. 1.
- a mask shown in Fig. 3A is the first mask for forming the first conductor group 102.
- a mask shown in Fig. 3B is the second mask for forming the two-layered regions 103A, 103B.
- a mask shown in Fig. 3C is the third mask for forming the second conductor group 105. These masks are represented by the same hatched portions as in Fig. 1.
- FIG. 4E A method of manufacturing the active matrix cell having the structure described above will be described with reference to Figs. 4A to 4E.
- the sectional view along the line IIA - IIA′ in Fig. 1 is represented by (1); and the sectional view along the line IV - IV′ in Fig. 1 is represented by (2).
- Barium borosilicate glass (Corning 7059) is used as a material for a substrate 100.
- a 2,000- ⁇ thick SiN x is deposited by PCVD as a protective layer 101 on the substrate 100 to prevent characteristic degradation caused by impurity contamination from the substrate glass to the TFT.
- the substrate has a high transparency for an exposure light when exposed from the back side of the substrate.
- this exposure light is the exposure wavelength for a negative type photosensitive resin (to be described later).
- a 500- ⁇ thick ITO transparent conductive film is deposited by sputtering.
- a 400- ⁇ thick Mo film is then deposited by electron beam evaporation (EB) and serves as a light-shielding mask for exposure from the back side of the substrate.
- a 200- ⁇ thick phosphorus-doped n+a-Si film is deposited by the PCVD method.
- a photoresist pattern for the source and drain of the TFT, part of the data line, and the pixel electrode is formed on a multilayered structure consisting of the ITO film, the Mo film, and the n+a-Si film by using the first mask.
- the photoresist pattern serves as an etching preventive film.
- the n+a-Si film is patterned by reactive ion etching using CCl2F2 gas, the Mo film is then etched by reactive ion etching using a gas mixture of CCl2F2 and O2, and the ITO film is etched by an aqueous solution containing HCl and NHO3, thereby forming the first conductor group 102, as shown in (1) and (2) in Fig. 4A.
- the 1,200- ⁇ thick a-Si semiconductor film 103a and 200- ⁇ thick SiN x first insulating film 103b are continuously deposited by the PCVD without breaking vacuum, as shown in Fig. 4B.
- a photoresist pattern for the two-layered region 103A, 103B for the TFT and the intersection between lines are formed to etch the SiN x film by reactive ion etching using CF4 gas, and to etch the a-Si film by reactive ion etching using CCl2F2 gas.
- the two-layered regions 103A, 103B are formed as indicated by (1) and (2) in Fig. 4C.
- a negative type photosensitive polyimide 104a (e.g., Toray Photoneese UR-3600) is applied to the substrate by spin coating.
- the polyimide 104a is prebaked at a recommended temperature of 83°C.
- the polyimide 104a is exposed with an ultraviolet light 110 of 1,000 mJ/cm2 from the back side of the substrate.
- the nonexposed polyimide 104a is removed by a recommended developing solution.
- the resultant structure is annealed at 250°C to cause a chemical reaction for imidization, thereby forming the second insulating film 104 which covers the area excluding the two-layered regions 103A, 103B and the first conductor group 102.
- the second insulating film 104 is self-aligned with respect to the two-layered regions 103A, 103B, and the first conductor film 102 so as to fill the gap therebetween.
- a 1- ⁇ m thick Al film for a scanning line including the gate electrode is deposited and patterned using the third mask, thereby forming the second conductor group 105.
- the Mo film in the first conductor group 102 is removed together with Al. Therefore, the pixel electrode 4 consisting of the first conductor group 102 is made of only the ITO film, thereby completing the active matrix cell.
- the semiconductor layer 103a and the first insulating film 103b serving as the gate insulator can be continuously deposited without breaking vacuum, so that stability of an interface between the semiconductor layer 103a and the first insulating film 103b can be improved.
- Alumina borosilicate glass or the like may be used in place of the barium borosilicate glass (typical example is Corning 7059) for an active matrix display.
- Such glass materials have a high transparency for ultraviolet light used in exposure of the photosensitive resin. Therefore, exposure can be performed from the back side of the substrate.
- an Si-based semiconductor has a low transparency and can serve as a light-shielding mask when the resin is exposed from the back side of the substrate.
- the second insulating film can be easily self-aligned in a region excluding the first conductor group and the two-layered regions.
- the second insulating film electrically insulates the scanning line of the second conductor group from the two-layered regions, and it must therefore be perfectly formed to cover the side surface of the semiconductor layer.
- the resin is exposed from the back side of the substrate while the two-layered regions serve as a light-shielding mask, the peripheral region on the two-layered regions is exposed by light diffraction, and the photosensitive resin is left on the peripheral region of the two-layered regions. Therefore, the side surface of the semiconductor layer can be completely covered with the photosensitive resin, thus assuring high reliability of the method of the present invention.
- the second insulating film can be formed on the entire surface excluding the first conductor group and the two-layered region and does not require perfect transparency and light-shielding properties.
- Transparency and the light-shielding properties can be adjusted in accordance with properties of photosensitive resins, exposure conditions, and developing conditions.
- a third insulating film 200 may be formed around a first conductor group, as shown in Fig. 5, due to the following reasons. Even if the thickness of the Mo film is increased to reduce the resistance of the intersection region 7 and an increase in step height of the source and drain of the TFT occurs, degradation of the TFT characteristics can be prevented. In addition, the scanning line 1 can be made on the more flat surface. Therefore, defects, e.g., disconnections and short circuits, caused by poor step coverage can be prevented.
- the back side exposure technique with a negative type photosensitive resin used for forming the second insulating film can be performed such that the first conductor group is used as a light-shielding mask without modifications.
- SiN x or SiO2 may be used in place of the photosensitive resin.
- Figs. 6A to 6E show steps to form the third insulating film when SiN x is used. As shown in Fig. 6A corresponding to Fig. 4A, after a protective film 101 is formed on a substrate 100, a first conductor group 102 is formed. Subsequently , as shown in Fig. 6B, after an SiN x film 300 is formed on the first conductor group (Fig. 6B).
- a negative photoresist 310 is applied (Fig. 6°C), and back side exposure is performed with an ultraviolet light.
- a negative photoresist 310A can be left except for a region on the first conductive film, as shown in Fig. 6D.
- the SiN x film is removed by dry etching or the like to obtain the structure shown in Fig. 6E. In this case, the photoresist is removed after etching. After this, steps in Figs. 4B to 4E are used to complete the active matrix cell without modifications.
- poly-Si conventionally used in an active matrix display may be used to form the semiconductor layer 103a. If a p-channel TFT is used, a p-type semiconductor is used in place of an n-type semiconductor.
- SiN x is used to form the first insulating film 103b.
- SiO2 or the like may be used if a material has excellent insulating properties and can be used to form a TFT gate insulating film.
- the second insulating film 104 must be made of a negative photosensitive resin.
- the type of negative photosensitive resin is not limited to any specific one but can be a commercially available negative photoresist, a rubber- or isoprene-based photoresist, or a high-temperature torelant resist.
- Any material suitable for the gate electrode, such as Mo or poly-Si may be used to form the second conductor group 105.
- the protective film SiN x film or the like
- the substrate to prevent impurity contamination from the substrate
- the active matrix cell is formed on the protective film.
- the protective film may be omitted.
- Fig. 1 The arrangement shown in Fig. 1 is only an illustrative embodiment of the present invention. Various changes and modifications may be made without departing the spirit and scope of the invention.
- the second conductor group 105 on the data line 1 made of the first conductor group 102 is separated from the two-layered region at a position corresponding to the intersection region, the second conductor group 105 may overlap the two-layered region 103 at the intersection region 7 if there is not fear of short-circuiting the second conductor group 105 with the scanning line 2 made of the second conductor group 105.
- the resistance of the data line can be further reduced.
- the two-layered region 103A constituting the TFT active region is perfectly separated from the two-layered region 103B at the intersection region, as shown in Fig. 1.
- an unnecessary current is not supplied from the data line 1 to the pixel electrode 4 during the OFF state of the TFT 3, they need not be perfectly separated but can be partially connected to each other.
- the active matrix cell can be advantageously arranged and manufactured with excellent reproducibility at a high product yield.
- the data line is made of a two-layered conductor structure, so that the data line resistance can be minimized. Therefore, the display area can be advantageously increased.
- the insulating film is not formed on the pixel electrode, and the film structure of the display portion consists of only the alignment layer and the liquid crystal. Therefore, the design of the display portion can be advantageously facilitated.
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Abstract
Description
- The present invention relates to an active matrix cell driven by a thin-film field effect transistor (to be referred to as a TFT hereinafter) used in a liquid crystal display, and a method of manufacturing the active matrix cell.
- A liquid crystal display (LCD) using a liquid crystal as a display medium has been studied and developed in place of a CRT display since the LCD has a small depth and low power consumption and is compact as compared with the CRT display, and some liquid crystal display models are popular in practical applications. In recent years, an active matrix type liquid crystal display has received a great deal of attention. In this active matrix type liquid crystal display, TFTs are arranged in each pixel to drive the pixel.
- A typical active matrix type liquid crystal display has a structure wherein a liquid crystal is sandwiched between an active matrix substrate having TFTs thereon and a counter substrate, an entire surface of which receives a uniform potential. Basic units (pixels) consisting of TFTs and pixel electrodes are arranged on the active matrix substrate in a matrix form. Scanning lines for controlling the TFTs and data lines for supplying data to the pixel electrodes are arranged in a matrix form along the X and Y directions. On a discussion of an active matrix substrate, only a repetition unit including parts of data and
scanning lines TFT 3, and apixel electrode 4, as shown in Fig. 7, can be taken into consideration to grasp the entire structure of the active matrix substrate. The repetition unit is defined as an active matrix cell herein. Referring to Fig. 7,reference numeral 5 denotes a source of theTFT 3; 6, a drain of theTFT 3; 7, an intersection region between the data andscanning lines - Since an active matrix substrate having TFTs formed thereon is used in an active matrix type liquid crystal display, the fabrication process is more complex than a simple multiplex type liquid crystal display in which a liquid crystal is sandwiched between an X-direction wiring substrate and a Y-direction wiring substrate. Therefore, the product yield of the active matrix type displays is undesirably decreased, and it is difficult to provide a high-quality large display at low cost. Various attempts have been made to decrease the number of steps in manufacturing the active matrix substrate. The process is often evaluated by the number of photomasks (to be referred to as masks hereinafter). Active matrix substrate manufacturing processes from which manufacturing steps are reduced are called two- and three-mask processes, which are reported as transactions and the like. The number of masks under discussion is the number required for manufacturing the active matrix substrate. Therefore, masks required for forming an alignment layer are excluded from the number of masks.
- A conventional active matrix substrate manufacturing method from which the manufacturing steps are reduced will be described below. The scanning and data lines are indispensable elements in the active matrix substrate. Therefore, two masks for the scanning and data lines cannot be eliminated.
- The two-mask process is described in "AN IMPROVED DESIGN OF ACTIVE MATRIX LCD REQUIRING ONLY TWO PHOTOLITHOGRAPHIC STEPS", Y. Lebosq, et al., 1985 INTERNATIONAL DISPLAY RESEARCH CONFERENCE, pp. 34 - 36. This reference describes a process for forming scanning lines, data lines, TFTs, and pixel electrodes by using only two masks. Structural diagrams of an active matrix cell manufactured by the above process are illustrated in Figs. 8A and 8B. Referring to Fig. 8A, the active matrix cell can be manufactured by only a first mask (non-hatched region) for forming
data lines 10 and apixel electrode 11 and a second mask (region of hatches inclined upward to the right) for forming ascanning line 12. Fig. 8B is a sectional view of the active matrix cell in Fig. 8A along the line VIIIB - VIIIB′ thereof.Reference numerals - According to the above method, since only two masks are used, a
parasitic TFT region 19 as an unnecessary TFT region in addition to aTFT region 18 serving as a necessary active element is undesirably formed under thescanning line 12, resulting in a decisive drawback. That is, when a channel length of theparasitic TFT region 19 is large, a conductivity is small and the display characteristics are not so adversely affected. However, when the channel length is decreased, the display characteristics are greatly degraded. - The three-mask process is a process wherein a TFT formation mask is added to the data line mask. For this reason, each TFT is limited to the necessary region and a parasitic TFT region can be eliminated, thus manufacturing an ideal structure.
- Figs. 9A to 9E are sectional views showing steps in manufacturing an active matrix cell according to the three-mask process, as described in "A 640 x 400 Pixel Active-Matrix LCD Using a-Si TFT's", T. Sunata, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-33, No. 8, 1986, pp. 1218 - 1221. In this process, after a
protective layer 21 is formed on aglass substrate 20, a transparent conductive film to be used for source and drain of the TFT, the data line, and the pixel electrode is deposited. In this case, an ITO film is used and patterned to form a transparent conductive film 22 (first mask), as shown in Fig. 9A. A phosphorus-doped n⁺a-Sifilm 23 is selectively formed on the transparentconductive film 22 to form the source and and drain of the TFT, as shown in Fig. 9B. An a-Si film is deposited and patterned to form a TFT semiconductor region 24 (second mask). The a-Si film and the n⁺a-Si film excluding theTFT region 24 are simultaneously removed, as shown in Fig. 9C. As shown in Fig. 9D, a silicon nitride (to be referred to as SiNx hereinafter)film 25 serving as a gate insulating film is deposited. Finally, a metal film, e.g., an Al film is deposited and patterned to obtain ascanning line 26 so as to include the gate electrode (third mask), as shown in Fig. 9E. The active matrix cell is formed using first to third masks in this process. Since the TFT thus formed has a gate electrode as the uppermost layer, this TFT is called a top gate staggered TFT. The drain and source of the TFT consist of lead lines for externally extracting currents and regions for effectively injecting only necessary carrier into the semiconductor. Although source and drain regions having a high impurity concentration (i.e., n⁺ or p⁺ region) formed by diffusion or the like is used in a transistor using crystalline silicon, an n⁺a-Si film is used for source and drain to be deposited separately and additionally in a TFT using a-Si. - In the three-mask process, however, a photolithographic step and an a-Si film etching step are required between formation of the a-Si film serving as a TFT active region and formation of the SiNx film serving as the gate insulating film. An important interface for determining characteristics of a metal-insulator-semiconductor (MIS) field effect TFT tends to be contaminated. It is therefore difficult to form a high-mobility TFT with high reproducibility. In addition, the transparent
conductive film 22 as the lowermost layer serves as the data line. When a display area is to be increased, the resistance of the transparentconductive film 22 must be reduced. However, the thickness of the transparentconductive film 22 cannot be extremely increased due to the following reason. - A film formed by normal plasma chemical vapor deposition (to be referred to as a PCVD hereinafter) used as a deposition method of the a-Si film has poor step coverage at the pattern edge and causes degradation of the TFT characteristics. In particular, when a step height increases, these affections become severe. In order to decrease a data line resistance in the above process, through holes must be formed in the SiNx film 25 existing on the entire surface and another metal wiring pattern must be formed to decrease the data line resistance. However, this process requires at least an additional mask for forming the through holes, thus losing the advantage of the three-mask process. Terminals must be extracted from the peripheral portion of the substrate to apply voltages to the data lines formed of the transparent
conductive film 22 as the lowermost layer in the above process. For this reason, aninsulating film should not exit on the peripheral transparentconductive film 22 portion. In order to manufacture an active matrix using the above mentioned active matrix cell, a metal mask must be prepared not to deposit theSiN x 25 on the peripheral transparentconductive film 22 portion during deposition of theSiN x 25 serving as a gate insulating film. The metal mask is aligned with the pattern on the substrate with a microscope. Poor mask alignment and poor contact between the metal mask and the substrate cause undesirable deposition of the insulating film under the metal mask. - It is, therefore, a principal object of the present invention to provide an active matrix cell and a method of manufacturing the same with good reproducibility at a high yield and, more particularly, to provide an active matrix cell and a method of manufacturing the same, wherein a wiring pattern is formed on a substantially smooth surface, and possibilities of a disconnection and a short circuit by poor step coverage can be greatly reduced.
- It is another object of the present invention to provide an active matrix cell having a minimum line resistance and a method of manufacturing the same.
- It is still another object of the present invention to provide an active matrix cell and a method of manufacturing the same, wherein a display area can be easily increased.
- It is still another object of the present invention to provide an active matrix cell and a method of manufacturing the same according to a three-mask process having a smaller number of manufacturing steps.
- In order to achieve the above objects of the present invention, there is provided an active matrix cell comprising a first conductor group formed on a transparent substrate and constituting a source and a drain of a field effect thin-film transistor, part of a data line, and a pixel electrode, two-layered regions formed on the transparent substrate and consisting of a semiconductor film and a first insulating film which is formed on the semiconductor film and an area of the first insulating film in the two-layered regions has substantially the same area as that of the semiconductor film, a second insulating film contacting a side surface of the two-layered regions, having substantially the same thickness as that of the two-layered regions, and covering a region excluding the two-layered regions and the first conductor group, and a second conductor group serving as a scanning line and part of the data line, wherein one of the two-layered regions connects the source and the drain, partially overlaps the source and the drain so as to serve as an active region of the thin-film transistor, and the other of the two-layered regions overlaps the data line so as to have an area larger than an area defined by widths of adjacent ones of the data and scanning lines at an intersection region between the data and scanning lines, and one second conductor of the second conductor group serving as the scanning line partially overlaps the source and the drain therebetween on the two-layered region serving as the active region of the thin-film transistor so as to have a width larger than a distance between the source and the drain, and the other second conductors of the second conductor group serving as the parts of the data line are insulated from the scanning line.
-
- Fig. 1 is a plan view showing an active matrix cell according to an embodiment of the present invention;
- Fig. 2A is a sectional view of the active matrix cell in Fig. 1 along the line IIA - IIA′ thereof;
- Fig. 2B is a sectional view of the active matrix cell in Fig. 1 along the line IIB - IIB′ thereof;
- Figs. 3A to 3C are views showing the layout patterns of the three masks for forming the active matrix cell in Fig. 1;
- Figs. 4A to 4E are sectional views showing steps in manufacturing the active matrix cell shown in Fig. 1;
- Fig. 5 is a sectional view showing the main part of a modification of the present invention;
- Figs. 6A to 6E are views showing the modification of the present invention;
- Fig. 7 is a view showing a basic structure of an active matrix cell; and
- Figs. 8A and 8B are a plan view and a sectional view showing a conventional active matrix cell.
- Figs. 9A to 9E are sectional views showing the steps in manufacturing another conventional active matrix cell.
- Figs. 1, 2A, and 2B show an active matrix cell according to an embodiment of the present invention. As in the cell shown in Fig. 7, the active matrix cell of this embodiment includes a
data line 1, ascanning line 2, afield effect TFT 3, and apixel electrode 4. The active matrix cell comprises: aprotective film 101 formed on atransparent glass substrate 100 to prevent impurity contamination of aTFT 3; a first conductive film orconductor group 102 consisting of a multilayered film of an ITO film, an Mo film, and an n⁺a-Si film, which serve asource 5 of theTFT 3, adrain 6 of theTFT 3, part of thedata line 1, and thepixel electrode 4; two-layeredregions a-Si semiconductor film 103a partially overlapping thefirst conductor group 102 and an SiNx first insulating film orinsulator 103b formed on thesemiconductor 103a so as to have a same area as that of the semiconductor; a second insulating film orinsulator 104 which consists of a photosensitive polyimide, contacts the side surface of the two-layeredregions regions conductive film 102; and a second conductive film orconductor group 105 formed on the two-layeredregion insulating film 104, and thefirst conductor group 102 serving as thescanning line 2 and part ofdata line 1. The two-layeredregion 103A constitutes an active region of theTFT 3 by connecting thesource 5 and thedrain 6. The two-layeredregion 103B insulates theintersection region 7 between thedata line 1 and thescanning line 2 and has an area larger than an area defined by the widths of adjacent data andscanning lines second conductor group 105 partially overlap thesource 5 and thedrain 6 to have a width larger than the distance between thesource 5 and thedrain 6 and is formed between thesource 5 and thedrain 6 to constitute thescanning line 2 including the gate electrode of theTFT 3, as shown in Fig. 1. The other of thesecond conductor group 105 is in contact with thedata line 1 of the first conductive film to decrease the resistance of thedata line 1 while being not connected to thescanning line 2. - As shown in Fig. 2A, in the
intersection region 7 between the data andscanning lines TFT 3, one second conductor of thesecond conductor group 105 as the uppermost layer and thesemiconductor layer 103a are insulated from each other through the secondinsulating film 104. Thescanning line 2 is formed on a substantially flat surface. As is apparent from Fig. 2B, thedata line 1 is constituted by a multilayered film consisting of one first conductor of thefirst conductor group 102 and parts of thesecond conductor group 105. - Figs. 3A, 3B, and 3C show the layout patterns of masks required for forming the active matrix cell structure. The required number of masks is three, and these masks correspond to those in Fig. 1. A mask shown in Fig. 3A is the first mask for forming the
first conductor group 102. A mask shown in Fig. 3B is the second mask for forming the two-layeredregions second conductor group 105. These masks are represented by the same hatched portions as in Fig. 1. - A method of manufacturing the active matrix cell having the structure described above will be described with reference to Figs. 4A to 4E. The sectional view along the line IIA - IIA′ in Fig. 1 is represented by (1); and the sectional view along the line IV - IV′ in Fig. 1 is represented by (2). Barium borosilicate glass (Corning 7059) is used as a material for a
substrate 100. A 2,000-Å thick SiNx is deposited by PCVD as aprotective layer 101 on thesubstrate 100 to prevent characteristic degradation caused by impurity contamination from the substrate glass to the TFT. The substrate has a high transparency for an exposure light when exposed from the back side of the substrate. In other words, this exposure light is the exposure wavelength for a negative type photosensitive resin (to be described later). A 500-Å thick ITO transparent conductive film is deposited by sputtering. A 400-Å thick Mo film is then deposited by electron beam evaporation (EB) and serves as a light-shielding mask for exposure from the back side of the substrate. A 200-Å thick phosphorus-doped n⁺a-Si film is deposited by the PCVD method. A photoresist pattern for the source and drain of the TFT, part of the data line, and the pixel electrode is formed on a multilayered structure consisting of the ITO film, the Mo film, and the n⁺a-Si film by using the first mask. The photoresist pattern serves as an etching preventive film. The n⁺a-Si film is patterned by reactive ion etching using CCl₂F₂ gas, the Mo film is then etched by reactive ion etching using a gas mixture of CCl₂F₂ and O₂, and the ITO film is etched by an aqueous solution containing HCl and NHO₃, thereby forming thefirst conductor group 102, as shown in (1) and (2) in Fig. 4A. - After the photoresist pattern is removed, the 1,200-Å thick
a-Si semiconductor film 103a and 200-Å thick SiNx first insulatingfilm 103b are continuously deposited by the PCVD without breaking vacuum, as shown in Fig. 4B. By using the second mask, a photoresist pattern for the two-layeredregion regions first conductor group 102 except for the two-layeredregions insulating film 104 which covers the area excluding the two-layeredregions first conductor group 102. At this time, the secondinsulating film 104 is self-aligned with respect to the two-layeredregions first conductor film 102 so as to fill the gap therebetween. - Thereafter, as shown in (1) and (2) of Fig. 4E, a 1-µm thick Al film for a scanning line including the gate electrode is deposited and patterned using the third mask, thereby forming the
second conductor group 105. At this time, the Mo film in thefirst conductor group 102 is removed together with Al. Therefore, thepixel electrode 4 consisting of thefirst conductor group 102 is made of only the ITO film, thereby completing the active matrix cell. - When the characteristics of the
resultant TFT 3 were measured, a field effect mobility µ was 0.5 cm²/Vsec, a leaking current was 10⁻¹² A, and an ON-OFF ratio was some 10⁶ value. These characteristics were found to be sufficient for the active matrix TFT. Electrical insulation between the scanning line of thesecond conductor group 105 and thea-Si semiconductor 103b is perfectly maintained at the TFT and the intersection, and no abnormal current leakage from thescanning line 105 to thesemiconductor 103b was found. Since the data line is made of a multilayered film consisting of thefirst conductor group 102 and thesecond conductor group 105, the data line resistance can be reduced to about 1/10 that of the conventional data line structure. - According to this embodiment, the
semiconductor layer 103a and the first insulatingfilm 103b serving as the gate insulator can be continuously deposited without breaking vacuum, so that stability of an interface between thesemiconductor layer 103a and the first insulatingfilm 103b can be improved. - The technique for exposing the photosensitive resin from the back side of the substrate, which is a characteristic feature of the present invention, will be supplementarily described below. Alumina borosilicate glass or the like may be used in place of the barium borosilicate glass (typical example is Corning 7059) for an active matrix display. Such glass materials have a high transparency for ultraviolet light used in exposure of the photosensitive resin. Therefore, exposure can be performed from the back side of the substrate. In this case, an Si-based semiconductor has a low transparency and can serve as a light-shielding mask when the resin is exposed from the back side of the substrate. As the first conductor group includes an opaque conductor, the second insulating film can be easily self-aligned in a region excluding the first conductor group and the two-layered regions. The second insulating film electrically insulates the scanning line of the second conductor group from the two-layered regions, and it must therefore be perfectly formed to cover the side surface of the semiconductor layer. When the resin is exposed from the back side of the substrate while the two-layered regions serve as a light-shielding mask, the peripheral region on the two-layered regions is exposed by light diffraction, and the photosensitive resin is left on the peripheral region of the two-layered regions. Therefore, the side surface of the semiconductor layer can be completely covered with the photosensitive resin, thus assuring high reliability of the method of the present invention.
- Since transparency of the substrate and the light-shielding properties of the first conductor group and the two-layered region are associated with the objects of the present invention to some degree that the second insulating film can be formed on the entire surface excluding the first conductor group and the two-layered region and does not require perfect transparency and light-shielding properties. Transparency and the light-shielding properties can be adjusted in accordance with properties of photosensitive resins, exposure conditions, and developing conditions.
- As a shape corresponding to Fig. 2A in this embodiment, a third insulating film 200 may be formed around a first conductor group, as shown in Fig. 5, due to the following reasons. Even if the thickness of the Mo film is increased to reduce the resistance of the
intersection region 7 and an increase in step height of the source and drain of the TFT occurs, degradation of the TFT characteristics can be prevented. In addition, thescanning line 1 can be made on the more flat surface. Therefore, defects, e.g., disconnections and short circuits, caused by poor step coverage can be prevented. - To form the third insulating film 200, the back side exposure technique with a negative type photosensitive resin used for forming the second insulating film can be performed such that the first conductor group is used as a light-shielding mask without modifications. In addition, SiNx or SiO₂ may be used in place of the photosensitive resin. Figs. 6A to 6E show steps to form the third insulating film when SiNx is used. As shown in Fig. 6A corresponding to Fig. 4A, after a
protective film 101 is formed on asubstrate 100, afirst conductor group 102 is formed. Subsequently , as shown in Fig. 6B, after an SiNx film 300 is formed on the first conductor group (Fig. 6B). Anegative photoresist 310 is applied (Fig. 6°C), and back side exposure is performed with an ultraviolet light. Anegative photoresist 310A can be left except for a region on the first conductive film, as shown in Fig. 6D. The SiNx film is removed by dry etching or the like to obtain the structure shown in Fig. 6E. In this case, the photoresist is removed after etching. After this, steps in Figs. 4B to 4E are used to complete the active matrix cell without modifications. - In place of the materials used in the above embodiment, poly-Si conventionally used in an active matrix display may be used to form the
semiconductor layer 103a. If a p-channel TFT is used, a p-type semiconductor is used in place of an n-type semiconductor. In addition, in the above embodiment, SiNx is used to form the first insulatingfilm 103b. However, SiO₂ or the like may be used if a material has excellent insulating properties and can be used to form a TFT gate insulating film. The secondinsulating film 104 must be made of a negative photosensitive resin. However, the type of negative photosensitive resin is not limited to any specific one but can be a commercially available negative photoresist, a rubber- or isoprene-based photoresist, or a high-temperature torelant resist. Any material suitable for the gate electrode, such as Mo or poly-Si may be used to form thesecond conductor group 105. - In the above embodiment, the protective film (SiNx film or the like) is formed on the substrate to prevent impurity contamination from the substrate, and the active matrix cell is formed on the protective film. However, if there is no danger of impurity contamination from a glass substrate, the protective film may be omitted.
- The arrangement shown in Fig. 1 is only an illustrative embodiment of the present invention. Various changes and modifications may be made without departing the spirit and scope of the invention. For example, although the
second conductor group 105 on thedata line 1 made of thefirst conductor group 102 is separated from the two-layered region at a position corresponding to the intersection region, thesecond conductor group 105 may overlap the two-layeredregion 103 at theintersection region 7 if there is not fear of short-circuiting thesecond conductor group 105 with thescanning line 2 made of thesecond conductor group 105. With this structure, the resistance of the data line can be further reduced. In the above embodiment, the two-layeredregion 103A constituting the TFT active region is perfectly separated from the two-layeredregion 103B at the intersection region, as shown in Fig. 1. However, if an unnecessary current is not supplied from thedata line 1 to thepixel electrode 4 during the OFF state of theTFT 3, they need not be perfectly separated but can be partially connected to each other. - According to the present invention as has been described above, since only three masks are used, the active matrix cell can be advantageously arranged and manufactured with excellent reproducibility at a high product yield.
- Furthermore, the data line is made of a two-layered conductor structure, so that the data line resistance can be minimized. Therefore, the display area can be advantageously increased.
- Furthermore, the insulating film is not formed on the pixel electrode, and the film structure of the display portion consists of only the alignment layer and the liquid crystal. Therefore, the design of the display portion can be advantageously facilitated.
Claims (16)
- a first conductor group (102) formed on a transparent substrate (100) and constituting a source (5) and a drain (6) of a field effect thin-film transistor (3), part of a data line (1), and a pixel electrode (4);
- two-layered regions (103A, 103B) formed on said transparent substrate (100) and being formed of a semiconductor film (103a) and a first insulating film (103b) which is formed on said semiconductor film (103a) and an area of said first insulating film (103b), in said two- layered regions (103A,103B) has substantially the same area as that of said semiconductor film (103a);
- a second insulating film (105) contacting a side surface of said two-layered regions (103A,103B), having substantially the same thickness as that of said two-layered regions, and covering a region excluding said two-layered regions and said first conductor group (102); and
- a second conductor group (105) serving as a scanning line (2) and part of said data line (1),
wherein one (103A) of said two-layered regions connects said source (5) and said drain (6), partially overlaps said source and said drain so as to serve as an active region of said thin-film transistor (3), and the other (103B) of said two-layered regions overlaps said data line (1) so as to have an area larger than an area defined by widths of adjacent ones of said data (1) and scanning lines (2) at an intersection region (7) between said data and scanning lines, and a second conductor included in said second conductor group (105) serving as said scanning line (2) partially overlaps said source (5) and said drain (6) therebetween on said two-layered region (103A) serving as the active region of said thin-film transistor so as to have a width larger than a distance between said source (5) and said drain (6), and the other conductors included in said second conductor group (105) are insulated from said scanning line.
wherein said data line (1) has a two-layered structure; said output electrode (5) of said field effect thin-film transistor (3), a lower layer (1) of said two-layered structure of said data line, and said pixel electrode (4) are constituted by a first conductor group (102); said field effect thin-film transistor includes a two-layered region (103A) which partially overlaps said output electrodes (5, 6) apart from each other and serves as an active region of said transistor, said two-layered region (103A) consists of semiconductor (103a) placed on said substrate (100) and first insulator (103b) which has the same area as that of said semiconductor, said two-layered region (103A) being provided with a side surface contacting a second insulating film (104), said second insulating film covering a region excluding said two-layered region (103A) and said first conductor group (102), and the other two-layered region (103B) which has the same structure as that of said two-layered region overlaps said data line (1) so as to have an area larger than an area defined by widths of adjacent ones of said data (1) and scanning lines (2); and said scanning line is constituted by one second conductor group (105), said scanning line including a gate electrode of said transistor (3) which partially overlaps said output electrodes (5, 6) on said two-layered region (103A) serving as the active region of said transistor so as to have a width larger than a distance between said output electrodes (5, 6) and said second conductor group (105), a portion of which serves as part of said data line (1), being insulated from said scanning line (2).
- depositing a first conductive film on a transparent substrate having a high transparency with respect of radiation a wavelength of a negative insulating photosensitive resin, etching said first conductive film in the form of a source and a drain of a field effect thin-film transistor, thereby forming a first conductor group;
- forming a two-layered region consisting of a semiconductor film and a first insulating film, said two-layered region connecting said source and said drain, thereby constituting an active region of said field effect thin-film transistor;
- applying said negative insulating photosensitive resin;
- exposing said photosensitive resin from a back side of said transparent substrate by using said two-layered region and said first conductor group as light-shielding masks, developing said photosensitive resin, and forming a second insulating film of said photosensitive resin so as to contact a side surface of said two-layered region in a region excluding said two-layered region and said first conductor group; and depositing a second conductive film and forming a second conductor group including a gate electrode of said field effect thin-film transistor.
- depositing a first conductive film including an opaque conductive film on a transparent substrate and etching said first conductive film in a form of a source and a drain of a field effect thin-film transistor, part of a data line, and a pixel electrode, thereby forming a first conductor group;
- depositing a semiconductor film and a first insulating film on said semiconductor film, etching said semiconductor film and said insulating film connecting said source and said drain, thereby forming a two-layered region serving as an active region of said thin-film transistor and another two-layered region at an intersection region between said data line and said scanning line having an area larger than an area defined by widths of adjacent ones of said data and scanning lines;
- applying a negative insulating photosensitive resin;
- exposing said photosensitive resin from a back side of said transparent substrate by using said two-layered regions and said first conductor group as light-shielding masks, developing said photosensitive resin, and forming a second insulating film of said photosensitive resin contacting a side surface of said two-layered region in a region excluding said two-layered region and said first conductor group, said second insulating film having substantially the same thickness as that of said two-layered region; and
- depositing a second conductive film and etching said second conductive film in a form of said scanning line including a gate electrode of said thin-film transistor as well as in a form of part of said data line on said data line of said first conductor group, thereby forming a second conductor group.
- forming a pattern on a transparent substrate having a high transparency with respect to an exposure radiation wavelength of a negative type photosensitive resin, said pattern including at least one layer having a lower transparency with respect to the wavelength;
- applying said photosensitive resin;
- exposing said photosensitive resin from a back side of said substrate; and
- developing said photosensitive resin to fill said photosensitive resin in a gap in said pattern in a self-aligned manner.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62192341A JPH0797191B2 (en) | 1987-07-31 | 1987-07-31 | Active matrix cell and manufacturing method thereof |
JP192341/87 | 1987-07-31 | ||
JP62322983A JPH01165127A (en) | 1987-12-22 | 1987-12-22 | Method of flattening surface |
JP322983/87 | 1987-12-22 | ||
JP329956/87 | 1987-12-28 | ||
JP62329956A JPH01173646A (en) | 1987-12-28 | 1987-12-28 | Manufacture of thin-film transistor |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0304657A2 true EP0304657A2 (en) | 1989-03-01 |
EP0304657A3 EP0304657A3 (en) | 1989-07-05 |
EP0304657B1 EP0304657B1 (en) | 1993-10-13 |
Family
ID=27326598
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88112172A Expired - Lifetime EP0304657B1 (en) | 1987-07-31 | 1988-07-27 | Active matrix cell and method of manufacturing the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US4918504A (en) |
EP (1) | EP0304657B1 (en) |
DE (1) | DE3884891T2 (en) |
Cited By (3)
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EP0380311A1 (en) * | 1989-01-27 | 1990-08-01 | Matsushita Electric Industrial Co., Ltd. | Active matrix addressed liquid crystal image display and method for fabricating the same |
EP0484965A3 (en) * | 1990-11-09 | 1993-12-01 | Seiko Epson Corp | Active matrix substrate |
US9917109B2 (en) | 2010-03-12 | 2018-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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EP0217406B1 (en) * | 1985-10-04 | 1992-06-10 | Hosiden Corporation | Thin-film transistor and method of fabricating the same |
US4960719A (en) * | 1988-02-04 | 1990-10-02 | Seikosha Co., Ltd. | Method for producing amorphous silicon thin film transistor array substrate |
GB2220792B (en) * | 1988-07-13 | 1991-12-18 | Seikosha Kk | Silicon thin film transistor and method for producing the same |
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FR2651371B1 (en) * | 1989-08-29 | 1991-10-18 | France Etat | METHOD FOR PRODUCING A DISPLAY SCREEN WITH ACTIVE MATRIX AND INVERSE STRUCTURE. |
US5498573A (en) * | 1989-11-29 | 1996-03-12 | General Electric Company | Method of making multi-layer address lines for amorphous silicon liquid crystal display devices |
JP2999271B2 (en) * | 1990-12-10 | 2000-01-17 | 株式会社半導体エネルギー研究所 | Display device |
DE4242408C2 (en) * | 1991-12-11 | 1998-02-26 | Mitsubishi Electric Corp | Method of connecting a circuit substrate to a semiconductor part |
KR100195269B1 (en) * | 1995-12-22 | 1999-06-15 | 윤종용 | Manufacture method of liquid crystal display device |
US6080606A (en) * | 1996-03-26 | 2000-06-27 | The Trustees Of Princeton University | Electrophotographic patterning of thin film circuits |
KR100269520B1 (en) * | 1997-07-29 | 2000-10-16 | 구본준 | Thin-film transistor, liquid-crystal display and manufacturing method thereof |
US6656779B1 (en) | 1998-10-06 | 2003-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor apparatus having semiconductor circuits made of semiconductor devices, and method of manufacture thereof |
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US7223641B2 (en) * | 2004-03-26 | 2007-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, method for manufacturing the same, liquid crystal television and EL television |
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US20080207077A1 (en) * | 2007-02-26 | 2008-08-28 | 3M Innovative Properties Company | Fabrication of backplanes allowing relaxed alignment tolerance |
US7629206B2 (en) * | 2007-02-26 | 2009-12-08 | 3M Innovative Properties Company | Patterning self-aligned transistors using back surface illumination |
US20080205010A1 (en) * | 2007-02-26 | 2008-08-28 | 3M Innovative Properties Company | Active matrix backplanes allowing relaxed alignment tolerance |
CN101765908A (en) * | 2007-08-01 | 2010-06-30 | 夏普株式会社 | Method for manufacturing semiconductor device, semiconductor device, and exposure apparatus |
JP5717546B2 (en) | 2011-06-01 | 2015-05-13 | 三菱電機株式会社 | Thin film transistor substrate and manufacturing method thereof |
JP2015012048A (en) | 2013-06-27 | 2015-01-19 | 三菱電機株式会社 | Active matrix substrate and method for manufacturing the same |
JP6315966B2 (en) | 2013-12-11 | 2018-04-25 | 三菱電機株式会社 | Active matrix substrate and manufacturing method thereof |
CN109597256A (en) * | 2018-12-29 | 2019-04-09 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
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- 1988-07-27 EP EP88112172A patent/EP0304657B1/en not_active Expired - Lifetime
- 1988-07-27 DE DE88112172T patent/DE3884891T2/en not_active Expired - Fee Related
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0380311A1 (en) * | 1989-01-27 | 1990-08-01 | Matsushita Electric Industrial Co., Ltd. | Active matrix addressed liquid crystal image display and method for fabricating the same |
US5124823A (en) * | 1989-01-27 | 1992-06-23 | Matsushita Electric Industrial Co., Ltd. | Active matrix addressed liquid crystal image display and method for fabricating the same |
US5459092A (en) * | 1989-01-27 | 1995-10-17 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating an active matrix addressed liquid crystal image device |
EP0484965A3 (en) * | 1990-11-09 | 1993-12-01 | Seiko Epson Corp | Active matrix substrate |
US5614730A (en) * | 1990-11-09 | 1997-03-25 | Seiko Epson Corporation | Active matrix substrate |
US9917109B2 (en) | 2010-03-12 | 2018-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
EP0304657B1 (en) | 1993-10-13 |
US4918504A (en) | 1990-04-17 |
DE3884891T2 (en) | 1994-05-05 |
EP0304657A3 (en) | 1989-07-05 |
DE3884891D1 (en) | 1993-11-18 |
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