JPH01173646A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To flatten the surface by a method wherein an insulating film with a high transmission factor is deposited on a wiring part formed on a substrate which is transparent with reference to a photosensitive wavelength of a negative-type photosensitive resin and the negative-type photosensitive resin applied to this insulating film is exposed to light from the back of the substrate so that an interval between wiring parts can be filled with the insulating film. CONSTITUTION:A multilayer film containing a metal film whose transmission factor with reference to a photosensitive wavelength of a negative-type photosensitive resin is low or a similar metal film is deposited on a substrate 10 whose transmission factor with reference to this wavelength is high; after that, wiring parts 11 of a prescribed pattern are formed. Then, an insulating film 12 whose transmission factor with reference to the photosensitive wavelength of the photosensitive resin is high is deposited on the wiring parts 11; the negative- type photosensitive resin 13 whose exposed part is not dissolved by a developing solution is applied to the substrate 10 including the insulating film 12; after that, the resin is exposed, from the back of the substrate, to a beam 14 having the photosensitive wavelength of the photosensitive resin 13. When a developing operation is executed, the wiring parts 11 are transformed into exposure-blocking films; patterns 13a of the negative-type photosensitive resin are left in regions excluding the wiring parts; the insulating film 12 is etched by making use of the patterns 13 as a mask; only the insulating film on the wiring parts 11 is removed; lastly, the patterns 13a are removed. By this setup, an interval between the wiring parts is filled; it is possible to eliminate a stepped part formed by the wiring parts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor formed on a substrate having a high transmittance to a photosensitive wavelength of a photosensitive resin such as glass.

[Conventional technology]

A flat display using liquid crystal as a display medium (Liq
With the aim of improving display quality, an active matrix method in which pixels are driven by active elements such as thin film transistors (TPT) has begun to be used in devices such as LCDs.

The active matrix method has a structure in which X and Y intersecting wirings are formed on a substrate and active elements are provided at the intersections of the wirings. In this active matrix method, display information is written to pixels by sequentially operating X and Y cross wiring, so as the display screen expands, the wiring length increases and wiring resistance increases, making it difficult to write within the specified writing time. A problem arises in that it becomes difficult to write display information to. Therefore, it is essential to increase the wiring film thickness and reduce the wiring resistance.

By the way, as a TPT using an amorphous silicon (A-3I) film as the active layer of an active element, a staggered structure is used in which the source and drain wiring and the gate electrode wiring are located in opposing positions with an A-8T film in between. , the case where the gate electrode wiring is on the substrate side is called bottom gate TFT.
, the case where the source and drain wirings are on the substrate side is called a top gate TPT. Therefore, either the source/drain wiring or the gate electrode wiring, which is the cross wiring of X and Y, becomes a layer placed under the a-8t film. Plasma vapor phase epitaxy (usually used for a-Si film deposition)
In the PCVD (PCVD) method, the film quality at the step part becomes weak and the characteristics are significantly different from those on the flat part, so the a-
It is known that the characteristics of TPT using an 8t film deteriorate significantly. This becomes more prevalent as the height of the step increases. On the other hand, conventionally, the wiring under the A-3I film was made of chromium (Cr), nichrome (NtCr), which can withstand the A-8T film deposition temperature.
) A highly heat-resistant metal material with relatively high resistivity, such as indium tin oxide (ITO), has been used, and has been made as thin as possible. Therefore, it is difficult to simply change the wiring metal or increase the wiring film thickness in order to reduce the resistance.

As a method to solve this problem, for example, JP-A-61-2
As seen in Japanese Patent No. 01468, a method is known in which gaps between wirings are filled with an insulating film to remove steps formed by the wirings and flatten the wiring. Here, after wiring is formed, an insulating film such as polyimide, silicon dioxide, silicon nitride, etc. is coated or deposited while the photosensitive resin used for forming the wiring remains, and the insulating film on the wiring is lifted off together with the photosensitive resin. is used.

[Problem that the invention seeks to solve]

However, with the conventional method of embedding wiring by lift-off, the insulating film deposited on the side of the photosensitive resin makes lift-off difficult, and the insulating film deposited on the side of the photosensitive resin may remain in protrusions. However, there were drawbacks such as a decrease in yield and residual steps due to the protrusions. Also,
In order to improve the lift-off yield, we performed short-time etching by taking advantage of the fact that the insulating film deposited on the sides of the photosensitive resin is thinner and more fragile than the film deposited on flat areas, and the etching rate is faster. There is a method of lifting off later, but in this case, the quality of the insulating film deposited on the side of the wiring is fragile, so grooves tend to form between the wiring and the buried insulating film, making it difficult to completely bury the wiring. was there.

Furthermore, wiring can be made of a multilayer film consisting of a transparent conductive film that can be used as a pixel electrode and a metal film to reduce resistance, and
Multilayer films containing n-type amorphous silicon (n”a-8i) to form source-drain junctions are often required, but these films can be etched independently using different etching methods or etchants. I have no choice but to process it.
Due to side etching, it is inevitable that the lower layer film becomes smaller than the upper layer film. In this case, if the insulating film is deposited with the thick photosensitive resin remaining, cracks will occur in the deposited insulating film with the side-etched portion as a nucleus due to the shadow effect, leaving grooves after lift-off.

In view of the above points, the present invention has been made to solve such problems.In a thin film transistor manufactured by forming an active layer on the wiring, the wiring interval is filled with an insulating film and the surface is flattened. This provides a method to do so.

[Failure to solve the problem]

The present invention is based on the fact that substrates such as glass have high transmittance not only to visible light but also to wavelengths at which photosensitive resins are sensitive, usually ultraviolet light, and it is possible to expose photosensitive resins from the back side. If the wiring has low transmittance for the photosensitive wavelength of the photosensitive resin and the insulating film deposited on the wiring has high transmittance, the wiring can be exposed from the back of the board using the photosensitive resin formed on the insulating film. This method utilizes the fact that it can be exposed as a blocking area, and its outline will be explained with reference to FIG. 1.

FIG. 1 is a process sectional view illustrating a method of burying the wiring gap with an insulating film, which is the basic concept of the present invention.

First, in FIG. 1(a), on a substrate 10 having a high transmittance to the photosensitive wavelength of the negative photosensitive resin, a wiring metal film having a low transmittance to the photosensitive wavelength of the negative photosensitive resin or a negative type After depositing a multilayer film including a wiring metal film having low transmission relative to the photosensitive wavelength of the photosensitive resin, a predetermined pattern of wiring 11 is formed using a normal photoetching process. Next, as shown in FIG. 1(b), an insulating film 12 having a high transmittance for the wavelength at which the photosensitive resin is sensitive is deposited on the wiring 11. Next, as shown in FIG. 1(c), after coating the substrate 10 including the insulating film 12 with a negative photosensitive adhesive 13 that prevents the exposed portion from dissolving in a developer, a film is applied from the back side of the substrate. Exposure is performed with light 14 having a wavelength to which the negative photosensitive resin 13 is sensitive. After that, when a development process is performed, as shown in FIG. 1(d), since the wiring 11 has a low transmittance to the photosensitive wavelength, an exposure blocking film is formed, and a negative photosensitive resin is applied to the area other than the wiring area. A 13m pattern remains. Thereafter, as shown in FIG. 1(a), by etching the insulating film 12 using the negative photosensitive resin pattern 13a as an etching mask, only the insulating film on the wiring 11 is removed. Finally, by removing the photosensitive resin pattern 13a, a structure in which the wiring 11 in a predetermined pattern is embedded in the insulating film 12a can be formed, as shown in FIG. 1(f).

[Effect]

As described above, according to the present invention, an insulating film with high transmittance is deposited on wiring formed on a substrate that is transparent to the photosensitive wavelength of a negative photosensitive resin such as glass, and By exposing the coated negative photosensitive resin from the back side of the substrate, a photosensitive resin pattern is formed in areas other than the wiring in a self-aligned manner, and this photosensitive resin pattern is used as an etching mask to etch the insulating film. Can be etched.

This makes it possible to fill in the gaps between the interconnects and reduce the level differences created by the interconnects, making it possible to easily select the interconnect film thickness in accordance with the required interconnect resistance value.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

Example 1; FIG. 2 is a process cross-sectional view showing an example of the method for manufacturing a thin film transistor according to the present invention.
The case where FTK is applied is shown. In FIG. 2, the transparent substrate 20 is barium borosilicate glass (Corning 705
9) A M film with a thickness of 1000 A was deposited on this substrate 20 to form a gate electrode wiring 21 (second
Figure (a)). Then, on top of this, an insulating film 22 having a high transmittance for the photosensitive wavelength is formed with a film thickness of 1000 Å equal to the wiring film thickness.
2(b)), and then CB
After applying a negative photosensitive resin 23 made of R-M2O3 (manufactured by Nippon Gosei Rubber Co., Ltd.) to a thickness of approximately 1.5 μm, the back surface of the substrate 20 was exposed to ultraviolet light 24 as light at a photosensitive wavelength. 2 (C)] At this time, different levels of exposure amount were set. After that, when a development process was performed, the MO film of the gate electrode wiring 21 acted as an exposure blocking film against the ultraviolet light 24, and the gate electrode wiring 21 23 m of exposed photosensitive resin was left in areas other than the top (Figure 2 (d))
. When the surface of the substrate was observed under an optical microscope at this stage, it was found that the overlap trays of the photosensitive resin tabs 23 & on the gate electrode wiring 11 in the exposure blocking region were formed differently depending on the exposure amount.

Next, the SiNx film 22 was processed by a reactive ion etching method using CF4 gas using the photosensitive resin button 23a as an etching mask (FIG. 2(e)). Note that the SiNxg after this processing is indicated by the symbol 22m. When this cross section was observed with a scanning microscope R, it was found that 5iNx11122ali
Depending on the overlap amount of the photosensitive resin button 23&,
The amount of overlap of the Mo film on the gate electrode wiring 21 was different.

Furthermore, when the amount of overlap of the photosensitive resin tabs 23m was small, there was no SiNx film on the gate electrode wiring 21 of the MO, resulting in a so-called negative overlap. This is because the photosensitive resin was also etched during etching of 5iNxl122, and the MO gate electrode wiring 2 was generated due to light diffraction.
This is because the photosensitive resin overlapping 1 was removed. After this, a film thickness of 20
A SiNx film of 00A and an a-8t film 26 of JJ100OA, which will become the active layer, were successively deposited (FIG. 2(f)).

Next, the A-8i film 26 was processed so that only the TPT portion remained 7, and finally the source and drain wiring 27 was formed to fabricate a bottom gate type A-8i TFT (second
Figure (g)).

When we measured the characteristics of the a-8i TFT fabricated in this way, we found that when the SiNx film 22 overlaps the gate electrode wiring a21, when the gate electrode wiring 21 is not buried with an insulating film, and when the SiNx film 22 overlaps the gate electrode wiring a21, It was found that the variation in device characteristics was smaller than when the gate electrode wiring did not overlap with the gate electrode wiring. This is because the a-Si film 26, which is the active layer, does not cross over a steep step.
This is because it is formed on a generally flat surface.

Embodiment 2; FIG. 3 is a process sectional view showing another embodiment of the present invention;
Here, we show the case where it is applied to TPT (Top Game).

In FIG. 3, a barium borosilicate glass (Corning 7059) substrate is used as a transparent substrate 30, and an M film with a thickness of 1000 Å is formed on this substrate 30.

The film 311 is made of n-type amorphous silicon (n
"a-8t) After successively depositing the two layer groups of membrane 312,
A predetermined source and drain wiring pattern is formed using a normal photosensitive resin through a photo-etching process, and the MO film 31 is
1 and n'' a-8i 11Ji 312 were sequentially etched to form wiring patterns, that is, source and drain wirings 31 (FIG. 3 (Todoroki)).

Next, after removing the photosensitive resin, a SiNx film having a thickness of 1500 Å, which is the same as the wiring metal layer, was deposited as an insulating film 32 having high transmittance for the photosensitive wavelength (see FIG. 3(b)).
). Next, a negative photosensitive resin 33 made of Photony Figure 3 (C)). At this time, different levels of exposure were set. After that, when a development process is performed, the MO peritoneum 11 of the source and drain wiring 31 acts as an exposure blocking film against the ultraviolet light 34, and after development, the pattern of the photosensitive resin exposed on the area other than the source and drain wiring 31 is removed. 33 & remained (Fig. 3(d)). When the substrate surface was observed under an optical microscope at this stage, it was found that the photosensitive resin pattern 33a was formed with different amounts of overlap of the exposure blocking region on the source and drain wirings 31 depending on the exposure amount.

Next, using this photosensitive resin pattern 33a as an etching mask, 5iNxF1832 was processed by reactive ion etching using CF4 gas (FIG. 3(e)).

However, the SiN4 film after this processing is indicated by the symbol 32m.

When this cross section was observed under a scanning microscope, SSiNx1il1
32 was formed with different amounts of overlap on the source and drain wirings 31 depending on the amount of overlap of the photosensitive resin pattern 33a. Moreover, if the amount of overlap of the photosensitive resin pattern 33& is small, 5iNxp! : There was no overlap, and there was a so-called negative overlap. This is because the photosensitive resin was also etched during etching of the SiNx film 32, and the photosensitive resin overlapping the north and drain wirings 31 caused by light diffraction was removed.

After this, the a-8i film 35 with a thickness of 1000A becomes the active layer.
was deposited, and the a-8i film was processed so that only the TPT portion remained (Fig. 3(f)). Next, the gate insulating film 36
As shown in FIG. 3(g), a SiNx film with a thickness of 2000 Å was deposited. Finally, a gate electrode wiring 37 was formed to fabricate a top gate type a-3i TFT (Figure 3).

When we measured the percentage of the a-8t TFT manufactured in this way, we found that at the level where the SiNx film 32 overlaps the source and drain wiring 31, when the source and drain wiring is not buried with an insulating film, and when the 5i
It has been found that variations in device characteristics are smaller than when Nxj4 does not overlap the source and drain wirings. This is the a-Si film 35 which is the active layer.
This is because it is formed on a generally flat surface without going over any steep steps.

Embodiment 3: This embodiment relates to a top-gauge TPT, and the difference from the above-mentioned embodiment 2 is that the source and drain wirings include a transparent conductor that becomes a pixel electrode. To explain the differences from Example 2 above, in this example, indium tin oxide C with a thickness of 500A was deposited on a barium borosilicate glass (Corning 7059) substrate.
ITO), a three-layer membrane of the peritoneum was successively deposited. Then,
After forming a predetermined source and drain wiring pattern using an ordinary photosensitive resin using a photo process, the ITo film, 9Mo film, and H''aSi film were sequentially etched to form wiring. Next, only the portion that would become the pixel electrode was etched. The n''a-8t film and M□ film were removed. The subsequent steps are the same as those of the second embodiment shown in FIG. 3(c) and thereafter. As a result, the TPT characteristics were also similar to those of Example 2 described above.

As explained above in the examples, according to the present invention,
It is desirable that the insulating film after etching overlaps the gate electrode wiring or the source and drain wiring, that is, the wiring. Therefore, when exposing a negative photosensitive resin by back exposure, it is necessary that the pattern of the photosensitive resin overlap the wiring with a sufficient film thickness. Since this overlap region is formed by diffraction of light, the amount of overlap does not increase excessively even if a sufficient amount of exposure is given, and a shape that satisfies the required conditions can be easily obtained.

Further, for etching the insulating film, it is desirable to use dry etching in which side etching does not occur and the photosensitive resin is etched at the same time. This is because the photosensitive resin at the boundary between the insulating film and the wiring is thin, so when the insulating film is etched, the photosensitive resin is also etched away, and the insulating film at the boundary between the insulating film and the wiring is automatically reshaped and unnecessary. This is to prevent protrusions from forming.

Further, as shown in Example 2.3 above, the wiring may be a multilayer film including one film having a low transmittance for the wavelength at which the photosensitive resin is sensitive. Here, a Mo film was used as a film with low transmittance, but it is obvious that a gold film of (It;) can also be used.

Further, in the present invention, it is sufficient that the negative photosensitive resin is exposed and remains on the area other than the wiring, and the absolute value of the transmittance of the substrate or the insulating film itself does not matter. Therefore, as an insulating film, in addition to silicon nitride (SiNx) mentioned in the example, 5i
O1, SiO, Tag 05, etc. can be used.

Further, there are no special restrictions on the negative photosensitive resin, and it is obvious that commercially available negative photosensitive resins can be applied.

Furthermore, the TFT structure mentioned in this example is just one example, and a film with high transmittance for the photosensitive wavelength is interposed on the substrate, and n-type impurities such as phosphorus (P) are used instead of n''a-SiO. It is obvious that modifications can be made within the scope of the invention, such as using a metal film containing the same to form a source/drain junction.

〔Effect of the invention〕

As explained above, according to the present invention, in a thin film transistor fabricated by forming an active layer on the wiring, it is possible to bury the interval between the wirings with an insulating film to eliminate the level difference in the wiring and flatten the surface. Therefore, even if the wiring film thickness is increased to reduce the wiring resistance, a good TPT% property can be obtained. Therefore, it has the advantage of eliminating problems caused by wiring resistance in large scale active mask IJ type flat displays, and has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a process illustrating the basic concept of the present invention, which is a method of filling the wiring gaps with an H film, FIG. 2 is a cross-sectional view of a process showing an embodiment of the present invention, and FIG. It is a process cross-sectional view which shows another Example. 10, 20, 30...transparent substrate, 11...Φ
Straight line, 12.12m, 22.22m, 32°32a
---Insulating film, 13, 23.33Φ...Negative photosensitive resin, 13a, 23a, 33m-φ...Bang of negative photosensitive resin, 14...Photosensitivity of negative photosensitive resin Wavelength of light, 21.370φ diameter/gate electrode wiring, 24.
34...Ultraviolet light, 25.36...Gate insulation,
Trace, 26.35・φ・Fist amorphous silicon (a-9
i) Film (?Y5 layer), 27.31...9.Source and drain wiring, 311.Write...Mo film, 3121
1e-IIn type amorphous silicon (H”a Si
)M.

Claims (9)

[Claims] (1) A substrate with high transmittance for the photosensitive wavelength of a negative photosensitive resin, a gate wiring provided on the substrate, a gate insulating film provided above the gate wiring, and the gate insulating film In a thin film transistor comprising source and drain wiring provided on the top, the gate electrode wiring is composed of a film having a low transmittance for the photosensitive wavelength or a multilayer film including a film having a low transmittance for the photosensitive wavelength, and depositing an insulating film having high transmittance to the photosensitive wavelength on the gate electrode wiring to a thickness approximately equal to that of the gate electrode wiring;
Next, a negative photosensitive resin is applied, and after exposing the negative photosensitive resin from the back side of the substrate, a pattern of the negative photosensitive resin is formed in an area excluding the gate electrode wiring area through a development process. A method for manufacturing a thin film transistor, characterized in that the insulating film is etched using the insulating film as an etching mask, and the gate electrode wiring is embedded in the insulating film. (2) When exposing from the back side of a negative photosensitive resin substrate, the edge of the pattern of the photosensitive resin created by the development process overlaps the gate electrode wiring, and the edge of the insulating film after etching is also applied to the gate electrode. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the thin film transistor is overlapped with the electrode wiring. (3) The thin film transistor manufacturing method according to claim 1 or 2, wherein the insulating film is etched by dry etching. (4) The method for manufacturing a thin film transistor according to any one of claims 1 to 3, wherein the active layer is made of an amorphous silicon film. (5) A substrate having high transmittance for the photosensitive wavelength of a negative photosensitive resin, source and drain wiring provided on the substrate, an active layer provided above the source and drain wiring, and a gate insulating film provided on the active layer;
In a thin film transistor comprising a gate electrode provided on the gate insulating film, the source and drain wirings are composed of a film having low transmittance to the photosensitive wavelength or a multilayer film including a film having low transmittance to the photosensitive wavelength. Then, an insulating film having high transmittance for the photosensitive wavelength is deposited on the source and drain wirings to a thickness approximately equal to that of the source and drain wirings, and then a negative photosensitive resin is applied to the substrate. After exposing the negative photosensitive resin to light from the back side, the insulating film is etched using a pattern of the negative photosensitive resin formed in an area excluding the source and drain wiring areas by a development process as an etching mask. . A thin film transistor manufacturing method, characterized in that the source and drain wirings are buried with the insulating film. (6) During exposure from the back side of the negative photosensitive resin substrate, the edges of the pattern of the photosensitive resin created by the development process overlap the source and drain wiring,
6. The method of manufacturing a thin film transistor according to claim 5, wherein the ends of the insulating film after etching are also overlapped with the source and drain wirings. (7) The thin film transistor manufacturing method according to claim 5 or 6, wherein the insulating film is etched by dry etching. (8) The method for manufacturing a thin film transistor according to any one of claims 5 to 7, wherein the source and drain wirings are multilayer films including a transparent conductor film. (9) The method for manufacturing a thin film transistor according to any one of claims 5 to 8, wherein the active layer is made of an amorphous silicon film.