JPS61182266A - Thin-film transistor device and manufacture thereof - Google Patents
Thin-film transistor device and manufacture thereofInfo
- Publication number
- JPS61182266A JPS61182266A JP60022913A JP2291385A JPS61182266A JP S61182266 A JPS61182266 A JP S61182266A JP 60022913 A JP60022913 A JP 60022913A JP 2291385 A JP2291385 A JP 2291385A JP S61182266 A JPS61182266 A JP S61182266A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- electrode
- insulating film
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000010408 film Substances 0.000 claims abstract description 130
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 230000001681 protective effect Effects 0.000 claims abstract 6
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000003860 storage Methods 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 3
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
Landscapes
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、非晶質シリコン（α−５４）や多結晶シリコ
ン（Ｐ−ｓ＜）等の半導体薄膜を用いた絶縁ゲート型薄
膜トランジスタ（Ｔ Ｐ Ｔ）装置で特に半導体薄膜が
極めて薄い構造と、その容易な製造方法に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an insulated gate thin film transistor (T In particular, the present invention relates to a structure in which a semiconductor thin film is extremely thin in a PT) device and an easy manufacturing method thereof.
絶縁基板上にソース、ドレイン電極を設け、半導体薄膜
とゲート絶縁膜と第２導電膜を連続堆積した後ゲート電
極を第２導電膜で形成し、表面保護用絶縁、嗅を堆積後
との絶縁膜とゲート絶縁膜と半導体薄膜の不要部を一括
除去するＴＦＴの製造工程と、そ詐によってできる’Ｉ
”ＦＴ構造を提示している。マスク工程が８回でも製造
可能で、かつ極めて薄い半導体薄膜を用いるのに適した
構造、製造方法でおる。Source and drain electrodes are provided on the insulating substrate, and after sequentially depositing a semiconductor thin film, a gate insulating film, and a second conductive film, a gate electrode is formed with the second conductive film, and insulation for surface protection and insulation after deposition are performed. The TFT manufacturing process involves removing unnecessary parts of the film, gate insulating film, and semiconductor thin film all at once, and the 'I' created by this process.
``We are proposing an FT structure.It can be manufactured even with eight mask steps, and the structure and manufacturing method are suitable for using extremely thin semiconductor thin films.
半導体薄膜特にα−Ｂｔｆ用いた’１”ＦＴは低温で大
面積に製作できるため、液晶表示装置やイメージセンサ
等に応用されつつある。ａ−日（ＴＰＴは従来ゲート電
極を最下層に形成する逆スタガー構造が主に用いらｎて
きたが、製造工程が多いという問題があった。−万％
１９８４年８月４ ｔｈ工％ｔｅｒｎａｔｉｏｎａＬ
ＤｉａｐＬａｙ Ｒｅ５ｅａτｃｈ ０ｏｎｆｅｒｅ
ｎａｅ （パリ〕で発表さ３７２ＯＮＥＴのＴＰＴは、
マスク数２枚で製造できるため注目を浴びている。その
構造例の平面図を第２図０）に示す。第２図Ｃｂ）は第
２図翰のＢ、−Ｂｌ線に沿った断面図である。ガラス基
板１上に、■Ｔｏ等の透明導電膜１２ 、１３と、十α
−８（［３２，３３でドレイン電極２とソース電極８を
形成する。その上にα−８（膜４、ゲート電極用金属（
Ａｔ）を連続堆積する。その後ゲート電１極６形成用パ
ターンでその下のゲート絶縁膜５及びα−Ｓイ膜４さら
にｎ十α−日ｉ膜３２ 、３３を除去する。その結果
Ｔ１１’Ｔ１００．画素電極１３１ ドレイン（データ
）配線１２から成る液晶表示用基板が完成する。この構
造は、マスク回数２回という非常に簡単な製造工程で実
現できるといった利点を有している。しかし下記の問題
点も有して岬５−
いる。ゲート電極６端部とα−８４８４端部の間の絶縁
距離は、ゲート絶縁膜５の厚みしかなくゲート、ソース
、ゲート、ドレイン間耐圧が低い。Semiconductor thin films, especially '1'' FTs using α-Btf, can be manufactured in large areas at low temperatures and are being applied to liquid crystal display devices, image sensors, etc. The inverted stagger structure has been mainly used, but it has the problem of requiring many manufacturing steps.-10,000%
August 4, 1984
DiapLay Re5eaτch 0onfere
The 372ONET TPT announced at nae (Paris) is
It is attracting attention because it can be manufactured with just two masks. A plan view of an example of the structure is shown in FIG. 20). FIG. 2Cb) is a sectional view taken along line B and -Bl of FIG. On the glass substrate 1, ■ transparent conductive films 12 and 13 such as To, and
-8 ([32, 33 to form drain electrode 2 and source electrode 8. On top of that, α-8 (film 4, gate electrode metal (
At) is continuously deposited. After that, the gate insulating film 5, the α-Si film 4, and the n+α-Si films 32 and 33 are removed using the pattern for forming the gate electrode 1 electrode 6. the result
T11'T100. A liquid crystal display substrate consisting of pixel electrode 131 and drain (data) wiring 12 is completed. This structure has the advantage that it can be realized by a very simple manufacturing process that requires only two masks. However, it also has the following problems. The insulation distance between the end of the gate electrode 6 and the end of the α-8484 is only the thickness of the gate insulating film 5, and the withstand voltage between the gate and source is low.
ドレイン配線１２は工Ｔｏから成るため抵抗が大きく、
液晶表示装置の大面積化が困難である。表面保護用絶縁
膜がないためＴＰＴ特性が経時変化しやすいなどが挙げ
らｊＬる。Since the drain wiring 12 is made of To, its resistance is large.
It is difficult to increase the area of a liquid crystal display device. Because there is no insulating film for surface protection, TPT characteristics tend to change over time.
本発明は従来技術の叙上の問題点ヲ鑑みてなさｎ１第１
の目的はドレイン配線を低抵抗化して大面積化可能なＴ
ＰＴ構造を、第２の目的は配線間耐圧の高い構造を、第
３の目的は表面保護用絶縁膜を有し信頼性の高いＴＦＴ
を提供するものである。また、こｒｔ、’ｉ−実現する
ための最適な簡単な製造方法全提供する。総じて、高歩
留り、高信頼性、低コストで大面積化が容易なＴＩｌ’
Ｔの構造と製造方法を提供するものである。The present invention has been made in view of the problems described in the prior art.
The purpose of this is to reduce the resistance of the drain wiring to enable a larger area.
The second purpose is to create a structure with high inter-wiring breakdown voltage, and the third purpose is to create a highly reliable TFT with a surface protection insulating film.
It provides: We also provide an optimal and simple manufacturing method for realizing this invention. Overall, TIl' has high yield, high reliability, low cost, and is easy to expand to a large area.
The present invention provides the structure and manufacturing method of T.
本発明によるＴＩ！′Ｔは、絶縁基板上に形成さｎ次ソ
ース及びドレイン電極と、該両電極に両端を、Ａ−
接した半導体薄膜と、その上のゲート絶縁膜及びゲート
電極と、さらにその上の表面保護用絶縁膜から成り、表
面保護用絶縁膜とゲート絶縁膜と半導体薄膜はほぼ同一
形状の島状領域として設け、ゲート電極は前記島状領域
の側面端部エリ内側で、かつゲート電極延在部もゲート
絶縁膜及び半導体薄膜の上部で表面保護用絶縁膜の下部
に設けらｎている。そのため、基本的に８回のマスク工
程で製造可能な構造である。また、ソース及びドレイン
電極及びその配線に透明導電膜、金属、低抵抗半導体薄
膜のいずｎかまたはそｎらの多層膜が用いらｎｌこｔら
の導電膜は表面保護用絶縁膜、ゲート絶縁膜、半導体薄
膜で被うことができる。TI according to the invention! 'T is an n-order source and drain electrode formed on an insulating substrate, a semiconductor thin film whose both ends are in A- contact with both electrodes, a gate insulating film and a gate electrode thereon, and a surface protection film thereon. The surface protection insulating film, the gate insulating film, and the semiconductor thin film are provided as island-like regions having almost the same shape, and the gate electrode is located inside the side edge area of the island-like region and within the gate electrode extension part. Also provided above the gate insulating film and the semiconductor thin film and below the surface protection insulating film. Therefore, the structure can basically be manufactured by eight mask steps. In addition, a transparent conductive film, a metal, a low-resistance semiconductor thin film, or a multilayer film thereof is used for the source and drain electrodes and their wiring. It can be covered with an insulating film or a semiconductor thin film.
前述の構造から明らかな様に、ドレイン電極（とその配
線）は金属膜を含むことができ、かつ工程的に除去する
必要がないので、配線抵抗は極めて低い。ゲート電極端
部と半導体薄膜端部はゲート絶縁膜の厚みの他に平面的
距離を保てるので絶縁耐圧は充分高い。本ＴＰＴ構造は
遮光構造を有していないが、半導体薄障を充分薄くする
。例えば５００八以下にすることにより光感度を実用上
問題なく少なくできる。各画素やＴＰＴ間のクロストー
クは半導体膜膜の高抵抗性、厚さのりすいことの他に平
面的寸法に工って充分防止できる。As is clear from the above structure, the drain electrode (and its wiring) can include a metal film and does not need to be removed in the process, so the wiring resistance is extremely low. In addition to the thickness of the gate insulating film, a distance in plan can be maintained between the end of the gate electrode and the end of the semiconductor thin film, so that the dielectric strength voltage is sufficiently high. Although this TPT structure does not have a light shielding structure, it makes the semiconductor thin barrier sufficiently thin. For example, by setting it to 5008 or less, the photosensitivity can be reduced without causing any practical problems. Crosstalk between each pixel or TPT can be sufficiently prevented by making the semiconductor film highly resistive, thin, and planarly dimensioned.
（ロ）実施例１ 単位画素部 （第１図）第１図（ロ
）は本発明によるＴ？Ｔｉ用いた液晶表示用単位画素の
平面図であり、第１図の）は第１図＠のＡ ＋ ＡＩ線
に沿った断面図である。ガラス、石英等の絶縁基板１上
に透明導電膜（例えば工Ｔｏ） １２ 、１３ ＃０デ
、Ｍｏ、Ｗ、等の金属やその硅化物から成る金属膜２２
、９３．低抵抗半導体薄膜（例えば九十α−日（膜〕
３２ 、３３が多層で第１導電膜として堆積１＆ドレイ
ン電極２とソース８を形成する。その上に、半導体薄膜
（例えばα−Ｓ（膜）４、ゲート絶Ｒ膜６、さらに第２
導電膜から成るゲート電極６が設けらｎる。(b) Example 1 Unit pixel section (Fig. 1) Fig. 1 (b) shows the T? according to the present invention. FIG. 1 is a plan view of a unit pixel for liquid crystal display using Ti, and () in FIG. 1 is a sectional view taken along the line A + AI in FIG. 1. On an insulating substrate 1 made of glass, quartz, etc., a transparent conductive film (for example, #0) is formed. A metal film 22 made of a metal such as Mo, W, etc. or its silicide is formed.
, 93. Low resistance semiconductor thin film (e.g. 90 α-days (film)
32 and 33 are multilayered and form a first conductive film, a deposit 1, a drain electrode 2, and a source 8. On top of that, a semiconductor thin film (for example, α-S (film) 4, a gate isolation R film 6, and a second
A gate electrode 6 made of a conductive film is provided.
ゲート電極６は半導体膜Ｒ４’Ａびゲート絶ＭＭ５上に
設けらｎｌその延在部（ゲート配線部〕も同様である。The gate electrode 6 is provided on the semiconductor film R4'A and the gate electrode MM5, and the same applies to its extended portion (gate wiring portion).
最上層には表面保護用絶縁膜７が堆積さｎｌ例えばソー
ス電極８の一部である画素電極用透明導電膜１３上の絶
縁膜７、ゲート絶縁膜５、半導体薄膜４、低抵抗半導体
薄膜３３、金属膜２３がほぼ同一形状に除去さｎている
。その結果残さｔた絶縁膜７、ゲート絶縁膜５、半導体
薄膜４から成る島状領域１０の端部工り内側にゲート電
極６がある。第１図の単位画素の例では、隣りの行のゲ
ート電極６Ｉと画素電極１３０間に信号電荷蓄積容量１
１０が形成さｎ、ゲート電極６１／ゲート絶縁膜５／半
導体薄膜４／低抵抗半導体薄＋１４３３ ／金属膜’１
．３７透明導電膜１３から成る構造を有している（ｂ）
実施例２゜単位画素部及びドレイン端子部〔第３図
及び第４図〕
第３図及び第４図には、そｎぞｎ単位画素部及びドレイ
ン端子部に本発明を適用した製造工程に沿った断面図を
示す。第３図に）は、基板１上に第１導電膜２０ヲ堆積
し選択エッチにエリ、行電極であるドレイン電極２と各
画素のソース電極８を形成した状態を示す。ドレイン電
極端子部は第４図に）に示した。第１導電膜加は、下か
ら透明導電膜−Ｑ＝
１２ 、１３ 、 Ｏγ、Ｍｏ、Ｗ、Ｔ７等の金属Ｍ？
２，２３、低抵抗半導体膜［３２，３３から成る多層膜
音用いている。金属膜２２ 、２３は必ずしも必要ない
が、配線抵抗減少に有効である。第３図の）では、半導
体膜膜４、ゲート絶縁膜５、第２導電膜１６を連続的に
堆積した断面である。このとき、ドレイン端子部では半
導体薄膜４、ゲート絶縁膜５の堆積時に金属マスク等で
フタをし、第２導電膜１６堆積時にマスクを除去する（
第４図の））。半導体薄膜４、ゲート絶縁膜５は例えば
プラズマＯＶＤや光０■Ｄ等で連続的にａ −Ｂｉ＜Ｈ
またはａ −８ｊ（Ｆ、 Ｂ１０ｗまたは町Ｎｚと堆積
さｎる。この堆積前に、逆スパッターや水素処理等で第
１導電［２０の表面を清浄にすることが有効である。第
２導電膜１６は、外部取り出しに有効なムｔ、ム１Ｌ、
Ｎｉ等が少なく共最上層にあることが望ましい。第２導
電膜１６を多層膜とするときには、低抵抗半導体膜や高
融点金属を最下層にすることが有効である。第３図（６
）は、列配線としてのゲート電極６を第２導電ＩＪ１１
６を用いて形成し、その彼我面保護用絶縁膜７ｔ−堆積
した状態を示す。端子部では、やはり第２導電膜１６で
端子電極２６ヲゲート電極６と分離して形成する（第４
図（Ｇ））、絶縁膜７として、Ｓイ０のやｓｉＮ。A surface protection insulating film 7 is deposited on the top layer, for example, the insulating film 7 on the pixel electrode transparent conductive film 13 which is part of the source electrode 8, the gate insulating film 5, the semiconductor thin film 4, and the low resistance semiconductor thin film 33. , the metal film 23 is removed in substantially the same shape. As a result, a gate electrode 6 is located inside the end portion of the island region 10 consisting of the insulating film 7, the gate insulating film 5, and the semiconductor thin film 4 that remain. In the example of the unit pixel in FIG. 1, the signal charge storage capacitance 1
10 is formed, gate electrode 61/gate insulating film 5/semiconductor thin film 4/low resistance semiconductor thin film +1433/metal film'1
．． It has a structure consisting of 37 transparent conductive films 13 (b)
Example 2 Unit pixel section and drain terminal section [Figures 3 and 4] Figures 3 and 4 show the manufacturing process in which the present invention is applied to the unit pixel section and the drain terminal section, respectively. A cross-sectional view along the line is shown. FIG. 3) shows a state in which a first conductive film 20 is deposited on a substrate 1 and selectively etched to form a drain electrode 2 serving as a row electrode and a source electrode 8 for each pixel. The drain electrode terminal portion is shown in Fig. 4). The first conductive film is a transparent conductive film from the bottom - Q=12, 13, metal M such as Oγ, Mo, W, T7, etc.
A multilayer film consisting of 2, 23 and a low resistance semiconductor film [32, 33 is used. Although the metal films 22 and 23 are not necessarily necessary, they are effective in reducing wiring resistance. 3) is a cross section in which the semiconductor film 4, the gate insulating film 5, and the second conductive film 16 are successively deposited. At this time, the drain terminal portion is covered with a metal mask or the like when the semiconductor thin film 4 and gate insulating film 5 are deposited, and the mask is removed when the second conductive film 16 is deposited (
)) in Figure 4. The semiconductor thin film 4 and the gate insulating film 5 are continuously formed by, for example, plasma OVD or light 0D.
Or a-8j (F, B10w or Machi Nz) is deposited. Before this deposition, it is effective to clean the surface of the first conductive film by reverse sputtering, hydrogen treatment, etc. The second conductive film 16 are Mt, M1L, and M1L that are effective for external extraction.
It is desirable that Ni and the like be present in a small amount in the uppermost layer. When the second conductive film 16 is a multilayer film, it is effective to use a low resistance semiconductor film or a high melting point metal as the bottom layer. Figure 3 (6
), the gate electrode 6 as a column wiring is connected to the second conductive IJ11.
6, and shows a state in which an insulating film 7t for protecting the outer surface is deposited. In the terminal portion, the terminal electrode 26 is formed separately from the gate electrode 6 by the second conductive film 16 (the fourth
(G)), the insulating film 7 is made of Si0 or SiN.
の他にポリイミド等が用いらｎる。第３図（イ）では、
絶縁、嗅７、ゲート絶縁膜５、半導体薄膜４を一括エッ
チして島状領域〕０を設け、場らに露出した低抵抗半導
体薄膜３３、金属膜２３を除去し、透明導電膜１３を残
し画素電極とする。一方、端子部では絶縁膜７を除去し
、端子電極２６全露出する（第４図（カ］。勿論端子部
では第４図の）での説明と同様１マスクを用いた絶縁膜
７の堆積も可能である。In addition, polyimide and the like can be used. In Figure 3 (a),
The insulation film 7, the gate insulating film 5, and the semiconductor thin film 4 are etched all at once to form island-like regions]0, and the exposed low resistance semiconductor thin film 33 and metal film 23 are removed, leaving the transparent conductive film 13. Use as pixel electrode. On the other hand, in the terminal part, the insulating film 7 is removed and the terminal electrode 26 is completely exposed (Fig. 4 (f). Of course, in the terminal part, the insulating film 7 is deposited using one mask as described in Fig. 4). is also possible.
（ｃ）実施例８ 単位画素部 （第５図〕第５図には、
本発明の単位画素部の平面図を示す。絶縁膜７、ゲート
絶縁膜５、半導体膜１嗅４、第１導電膜加の一部（金属
膜２２’、２３、低抵抗半導体薄膜３２．３３）から成
る島状領域１０は、・画素電極ｊ３上の一部の蓄積容量
１１０とＴ Ｆ Ｔ ＩＱＱ及びゲート電極配線の部分
に形成さｎている。即ち、不要な半導体薄膜４を除去し
た例である。(c) Example 8 Unit pixel section (Fig. 5) In Fig. 5,
FIG. 3 shows a plan view of a unit pixel section of the present invention. The island region 10 consisting of the insulating film 7, the gate insulating film 5, the semiconductor film 1, and a part of the first conductive film (metal films 22', 23, low resistance semiconductor thin film 32, 33) is a pixel electrode. It is formed in a part of the storage capacitor 110, TFT IQQ, and gate electrode wiring on j3. That is, this is an example in which unnecessary semiconductor thin film 4 is removed.
また、島状領域１０のバターニングは、表面側から（ソ
ース〕電極２やドレイン端子電極部やゲート端子部等を
通常のボジレジストヲ用いたマスク工程で行ない、再び
裏面から薄い半導体膜４を通して露光することに工って
不要な半導体薄膜４を除去できる。In addition, the patterning of the island-like region 10 is performed from the front side (source) electrode 2, drain terminal electrode part, gate terminal part, etc. by a mask process using a normal body resist, and then exposed again from the back side through the thin semiconductor film 4. In particular, unnecessary semiconductor thin film 4 can be removed.
（中実施例４． 単位画素部 （第６図）第６図には製
造方法の他の実施例を示す。第６図り）は、ドレイン。(Middle Embodiment 4. Unit pixel section (Fig. 6) Fig. 6 shows another embodiment of the manufacturing method. Fig. 6) is a drain.
ソース電極２．８’ｅまず金属膜２２ 、２３と透明導
電膜１２ 、１３で形成した断面である。第６図の）は
、第１導電膜の一部である低抵抗半導体膜３０を堆積し
、ポジレジスト８を塗布し裏面からの露光、現像を行な
ったものである。実線８は現像直後、点線１８は例えば
１５０℃以上でベークしレジスト８を流動変形させた状
態を示す。こＩｆ”ＬＫ工り低抵抗半導体薄膜３０ヲ選
択エッチすると、金属膜２２ 、２３、透明導電Ｍ １
２ 、１３の端部側面を被った形状に半導体薄膜３０を
残せる。第６図＜（＋）は、半導体薄膜４、ゲート絶Ｒ
膜５を堆積し、ゲート電極６（蓄積容量１１０を形成す
る他桁のゲート電極６１）を形成した状態でおる。第６
図Ｇ）は、ＴＦＴ部１００と蓄積容量部１１０全除き、
最下層の透明導電膜１３が露出するまで一括エッチして
完成した状態を示す。Source electrode 2.8'e First is a cross section formed by metal films 22 and 23 and transparent conductive films 12 and 13. In FIG. 6), a low-resistance semiconductor film 30, which is a part of the first conductive film, is deposited, a positive resist 8 is applied, and exposure and development are performed from the back side. A solid line 8 indicates a state immediately after development, and a dotted line 18 indicates a state in which the resist 8 is fluidized and deformed by baking at, for example, 150° C. or higher. If the LK processed low resistance semiconductor thin film 30 is selectively etched, the metal films 22, 23 and the transparent conductive film M1 are etched.
The semiconductor thin film 30 can be left in a shape covering the end side surfaces of 2 and 13. Figure 6 <(+) indicates semiconductor thin film 4, gate disconnection R
A film 5 is deposited, and a gate electrode 6 (a gate electrode 61 of another digit forming a storage capacitor 110) is formed. 6th
In Figure G), the TFT section 100 and storage capacitor section 110 are all excluded.
A completed state is shown in which the transparent conductive film 13 at the bottom layer is etched all at once until it is exposed.
本例では、低抵抗半導体膜Ｍ３０のバターニングをセル
ファラインで行なえ、かつ同薄膜３０で金属ｊｊ＠２２
．２３等と半導体薄膜４との亘接接触を避けらｎる。こ
のことで、ＴＮＴの逆方向リークを減少できる。In this example, the low-resistance semiconductor film M30 can be patterned by self-line, and the thin film 30 can be patterned with metal jj@22.
．． 23 etc. and the semiconductor thin film 4 can be avoided. This can reduce reverse leakage of TNT.
本発明に、ｃｎば（ｒ）ドレイン配線部の金属、Ｉｌｌ
２２ ｆ：除去する必要がないので低抵抗化が図しる
。（Ｉｔ）。In the present invention, the metal of the cn(r) drain wiring part, the metal of the drain wiring part, Ill
22f: Since there is no need to remove it, the resistance can be lowered. (It).
ゲート電極６を独立にバターニングするので耐圧できる
。（［［＋） ：表面保護絶縁膜７の存在で信頼性が高
い、（ロ）１以上を８回のマスク工程で製造できる等の
利点がおる。また、半導体膜＠４を極めて薄くしても、
この薄膜４をストッパーにしたコンタクトホール形成と
いった工程は不必要なので、遮光不要の超薄膜のＴＰＴ
が容易に実現できる利点もある。Since the gate electrode 6 is patterned independently, it can withstand voltage. ([[+): There are advantages such as high reliability due to the presence of the surface protection insulating film 7, and (b) 1 or more can be manufactured in 8 mask steps. Moreover, even if the semiconductor film @4 is made extremely thin,
Since the process of forming a contact hole using this thin film 4 as a stopper is unnecessary, the ultra-thin TPT film does not require light shielding.
There are also advantages that can be easily achieved.
本発明を主に液晶表示装置を例に述べてきたが、他のＴ
ＰＴ装置例えばＴＰＴ集積回路、イメージセンサ−１Ｔ
ＦＴｇ用いた撮像や表示装置等にも適用できる。主に、
半導体薄膜４としてα−町を例に述べたが、ｐ、−ｓ（
、ビーム了二−ルサｎた薄膜結晶、他の半導体材料につ
いても同様に本発明は適用できる。Although the present invention has been mainly described using a liquid crystal display device as an example, other T.
PT device such as TPT integrated circuit, image sensor-1T
It can also be applied to imaging and display devices using FTg. mainly,
Although α-town has been described as an example of the semiconductor thin film 4, p, -s(
The present invention is similarly applicable to thin film crystals, beam crystals, and other semiconductor materials.
本発明にエリ、ＴＩｌ’Ｔ装置の低コスト化、大面化、
高信頼性が得られるので、ＴＰＴの応用範囲がさらに拡
げることができる。The present invention has the advantage of reducing the cost and increasing the size of the TIl'T device.
Since high reliability can be obtained, the range of applications of TPT can be further expanded.
【図面の簡単な説明】
第１図０）は本発明によるＴＰＴ単位画素の断面図、第
１図の）は第１図に）のＡ、−Ａ Ｉ線に沿った断面図
である。第２図に）は従来のＴＰＴ単位画素の平面図、
第２図の）は第２図＠）の］１３．Ｂｌ線に沿った断面
図、第３図（ω〜ａ）及び第４図（ハ）〜■はそｎぞｎ
本発明の製造工程に沿つｆｃＴ Ｆ Ｔ単位画素部とド
レイン端子部の断面図、第５図は本発明の他の実施例の
平面図、第６図０）〜■は本発明の他の実施例による製
造工程順の断面図である。
ム１４−４
１０．基板 ２０．ドレイン電極 ８０．ソース電極
４．。半導体薄膜 ５１．ゲート絶縁膜６、。ゲート電
極 ７゜、底面保護用絶縁膜１０ 、。島状領域 １２
、１３゜、透明導電膜 ２２ 、 ’２３、。金属膜
３２，３３．、低抵抗半導体薄膜 １６゜、第２導電
膜 ２００．第１導電膜 ２６゜、ドレイン電極端子。
以上
り・１５−・
も ｋ
０ １１′BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (0) is a cross-sectional view of a TPT unit pixel according to the present invention, and (0) in FIG. 1 is a cross-sectional view taken along lines A and -AI in FIG. Figure 2) is a plan view of a conventional TPT unit pixel.
) in Figure 2 is in Figure 2 @)] 13. Cross-sectional views along the Bl line, Figures 3 (ω~a) and Figures 4 (c)~■ are not included.
A cross-sectional view of the fcT F T unit pixel part and the drain terminal part along the manufacturing process of the present invention, FIG. FIG. 3 is a cross-sectional view of the manufacturing process according to the example. M14-4 10. Substrate 20. Drain electrode 80. source electrode
4. . Semiconductor thin film 51. Gate insulating film 6. Gate electrode 7°, bottom protection insulating film 10. Island area 12
, 13°, transparent conductive film 22, '23,. Metal film 32, 33. , low resistance semiconductor thin film 16°, second conductive film 200. First conductive film 26°, drain electrode terminal. Above, 15-, also k 0 11'
Claims (7)
たソース電極及びドレイン電極と、該両電極に両端を接
して形成された半導体薄膜と、該薄膜上に形成されたゲ
ート絶縁膜と、該絶縁膜上に設けられたゲート電極と、
ゲート電極上に設けられた表面保護用絶縁膜とから成る
薄膜トランジスタにおいて、 前記表面保護用絶縁膜とゲート絶縁膜と半導体薄膜とは
前記ソース及びドレイン電極の少なく共一部と平面的に
重畳する島状領域として設けられ、前記ゲート電極は前
記島状領域の側面端部より内側でかつゲート電極延在部
も前記ゲート絶縁膜及び半導体薄膜の上部に及び前記表
面保護用絶縁膜の下部に形成されたことを特徴とする薄
膜トランジスタ装置。(1) An insulating substrate, a source electrode and a drain electrode formed on the substrate at a distance from each other, a semiconductor thin film formed with both ends in contact with the electrodes, and a gate insulating film formed on the thin film. and a gate electrode provided on the insulating film.
In a thin film transistor comprising a surface protection insulating film provided on a gate electrode, the surface protection insulating film, the gate insulating film, and the semiconductor thin film are islands that overlap in plan with at least common parts of the source and drain electrodes. The gate electrode is provided as a shaped region, and the gate electrode is formed inside the side edge of the island region, and the gate electrode extension portion is also formed on the gate insulating film and the semiconductor thin film and on the bottom of the surface protection insulating film. A thin film transistor device characterized by:
金属膜もしくは低抵抗半導体薄膜の少なく共一方とから
成ることを特徴とする特許請求の範囲第１項記載の薄膜
トランジスタ装置。(2) The source and drain electrodes include a transparent conductive film;
2. The thin film transistor device according to claim 1, wherein the thin film transistor device comprises at least one of a metal film and a low resistance semiconductor thin film.
導電膜以外の端部の少なく共一部は、前記島状領域の端
部の一部とほぼ一致していることを特徴とする特許請求
の範囲第２項記載の薄膜トランジスタ装置。(3) A claim characterized in that at least a common portion of the end portion of the source electrode or the drain electrode other than the transparent conductive film substantially coincides with a part of the end portion of the island-like region. 2. The thin film transistor device according to item 2.
とを特徴とする特許請求の範囲第１項から第３項いずれ
か記載の薄膜トランジスタ装置。(4) The thin film transistor device according to any one of claims 1 to 3, wherein the semiconductor thin film has a thickness of 500 Å or less.
ら成るソース電極とドレイン電極を選択的に形成する第
１工程 （ｂ）半導体薄膜、ゲート絶縁膜、第２導電膜を順次連
続して堆積する第２工程 （ｃ）前記ソース及びドレイン電極の少なく共一部と平
面的に重畳する様に、前記第２導電膜を選択除去してゲ
ート電極となす第３工程 （ｄ）表面保護用絶縁膜を堆積する第４工程（ｅ）前記
表面保護用絶縁膜とゲート絶縁膜と半導体薄膜の不要部
を少なく共除去しほぼ同一形状の島状領域とする第５工
程 とから成る薄膜トランジスタ装置の製造方法。(5) (a) First step of selectively forming a source electrode and a drain electrode consisting of a first conductive film spaced apart from each other on an insulating substrate (b) Sequentially forming a semiconductor thin film, a gate insulating film, and a second conductive film (c) a second step of depositing the second conductive film to form a gate electrode; (d) a third step of selectively removing the second conductive film so as to planarly overlap at least a common portion of the source and drain electrodes to form a gate electrode; A thin film transistor comprising a fourth step of depositing a protective insulating film (e) and a fifth step of removing unnecessary portions of the surface protective insulating film, the gate insulating film, and the semiconductor thin film to form island-like regions having approximately the same shape. Method of manufacturing the device.
と、金属もしくは低抵抗半導体薄膜の少なく共一方とか
ら成る多層膜であり、前記第５工程において島状領域の
形成によつて露出する第１導電膜のうちの金属膜もしく
は低抵抗半導体薄膜もしくは金属膜と低抵抗半導体薄膜
の両方を除去することを特徴とする特許請求の範囲第５
項記載の薄膜トランジスタ装置の製造方法。(6) In the first step, the first conductive film is a multilayer film consisting of a transparent conductive film and at least one of a metal or a low resistance semiconductor thin film, and in the fifth step, the first conductive film is formed by forming an island-like region. Claim 5, characterized in that the metal film, the low resistance semiconductor thin film, or both the metal film and the low resistance semiconductor thin film of the exposed first conductive film are removed.
A method for manufacturing a thin film transistor device according to section 1.
イン電極の延在部の一部にマスクをして前記半導体薄膜
とゲート絶縁膜を堆積し、前記マスクを除去した後に第
２導電膜を堆積することを特徴とする特許請求の範囲第
５項または第６項記載の薄膜トランジスタ装置の製造方
法。(7) In the second step, the semiconductor thin film and gate insulating film are deposited using a mask on a part of the extension of the source electrode or drain electrode, and after removing the mask, a second conductive film is deposited. A method for manufacturing a thin film transistor device according to claim 5 or 6, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60022913A JPH0654782B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing thin film transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60022913A JPH0654782B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing thin film transistor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61182266A true JPS61182266A (en) | 1986-08-14 |
| JPH0654782B2 JPH0654782B2 (en) | 1994-07-20 |
Family
ID=12095875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60022913A Expired - Lifetime JPH0654782B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing thin film transistor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0654782B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63172469A (en) * | 1987-01-12 | 1988-07-16 | Fujitsu Ltd | Thin film transistor |
| EP0304657A2 (en) * | 1987-07-31 | 1989-03-01 | Nippon Telegraph And Telephone Corporation | Active matrix cell and method of manufacturing the same |
| JPH01173646A (en) * | 1987-12-28 | 1989-07-10 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin-film transistor |
| US4907040A (en) * | 1986-09-17 | 1990-03-06 | Konishiroku Photo Industry Co., Ltd. | Thin film Schottky barrier device |
| US5879973A (en) * | 1992-08-07 | 1999-03-09 | Fujitsu Limited | Method for fabricating thin-film transistor |
| US5898187A (en) * | 1995-09-12 | 1999-04-27 | Lg Electronics Inc. | Thin film transistor |
| JP2006058676A (en) * | 2004-08-20 | 2006-03-02 | Semiconductor Energy Lab Co Ltd | Display device, its manufacturing method, and television apparatus |
| WO2011152233A1 (en) * | 2010-06-04 | 2011-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2012015502A (en) * | 2010-06-04 | 2012-01-19 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
| JPS5715469A (en) * | 1980-07-02 | 1982-01-26 | Matsushita Electric Ind Co Ltd | Thin film transistor for transmission type display panel and manufacture thereof |
| JPS5828870A (en) * | 1981-08-12 | 1983-02-19 | Toshiba Corp | Thin film semiconductor device |
-
1985
- 1985-02-08 JP JP60022913A patent/JPH0654782B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
| JPS5715469A (en) * | 1980-07-02 | 1982-01-26 | Matsushita Electric Ind Co Ltd | Thin film transistor for transmission type display panel and manufacture thereof |
| JPS5828870A (en) * | 1981-08-12 | 1983-02-19 | Toshiba Corp | Thin film semiconductor device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4907040A (en) * | 1986-09-17 | 1990-03-06 | Konishiroku Photo Industry Co., Ltd. | Thin film Schottky barrier device |
| JPS63172469A (en) * | 1987-01-12 | 1988-07-16 | Fujitsu Ltd | Thin film transistor |
| EP0304657A2 (en) * | 1987-07-31 | 1989-03-01 | Nippon Telegraph And Telephone Corporation | Active matrix cell and method of manufacturing the same |
| JPH01173646A (en) * | 1987-12-28 | 1989-07-10 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin-film transistor |
| US6338990B1 (en) | 1992-08-07 | 2002-01-15 | Fujitsu Limited | Method for fabricating thin-film transistor |
| US5879973A (en) * | 1992-08-07 | 1999-03-09 | Fujitsu Limited | Method for fabricating thin-film transistor |
| US5898187A (en) * | 1995-09-12 | 1999-04-27 | Lg Electronics Inc. | Thin film transistor |
| JP2006058676A (en) * | 2004-08-20 | 2006-03-02 | Semiconductor Energy Lab Co Ltd | Display device, its manufacturing method, and television apparatus |
| WO2011152233A1 (en) * | 2010-06-04 | 2011-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2012015502A (en) * | 2010-06-04 | 2012-01-19 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US8884283B2 (en) | 2010-06-04 | 2014-11-11 | Semiconductor Energy Laboratory Co., Ltd | Memory semiconductor device having aligned side surfaces |
| US9064884B2 (en) | 2010-06-04 | 2015-06-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having aligned side surfaces |
| US9461067B2 (en) | 2010-06-04 | 2016-10-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US10074663B2 (en) | 2010-06-04 | 2018-09-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0654782B2 (en) | 1994-07-20 |
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