EP0298988A1 - Arrangement for communicating a program from a host computer to a target computer - Google Patents
Arrangement for communicating a program from a host computer to a target computerInfo
- Publication number
- EP0298988A1 EP0298988A1 EP19870902846 EP87902846A EP0298988A1 EP 0298988 A1 EP0298988 A1 EP 0298988A1 EP 19870902846 EP19870902846 EP 19870902846 EP 87902846 A EP87902846 A EP 87902846A EP 0298988 A1 EP0298988 A1 EP 0298988A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- microcomputer
- program
- board
- equipment
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
Definitions
- the present invention relates to an arrangement for eliminating the need of connecting and utilizing a separate emulator between a host computer and a first microcomputer in connection with developing in the host computer a program intended for the first microcomputer. After programming the host computer the program is communicated to the first microcomputer, whereby a fault location is to be carried out in the communicated program.
- test overhead the quality of not inappropriately loading the program during the fault location therein
- a well-known separate emulator has the configuration of a double-process system, in which the system is run with one processor and supervised and tested with the second microcomputer.
- What can thereby be considered characterizing for the new arrangement is that it comprises a multiprocessor bus to which the first microcomputer is connected or connectable and that there is applied on a board an equipment provided with a second microcomputer and executing the fault location, the equipment by inserting the board in a used board holder being connectable with said bus so that the program communicated in the first microprocessor is fault locationable by means of the second microcomputer while running the first microcomputer.
- said equipment in the board should comprise a function for detecting the function course of the first microcomputer so that setting of break points in the program of the first microcomputer can take place.
- Said break points should, in a way known per se, consist of such entries in the program where the software performance characteristics is not being affected during the run.
- the second microcomputer should be arranged to set physical addresses corresponding to the various parts of the program in the hardware of the first microcomputer.
- ADVANTAGES Due to the invention an established multiprocessor bus system can be utilized. Examples of such systems are the commercially available systems "MULTIBUS" and "VME".
- the fault location equipment applied on the board is easily connectable to the bus system, like the first microcomputer, and when running the first microcomputer its program developed in the host computer can be fault located by means of the fault location executing equipment on the board.
- the last-mentioned equipment can be designed in a way known per se with a well-known hardware and a well-known program.
- Fig. 1 in a skeleton diagram form discloses the connecting in connection with programming in a host computer a program for a target machine
- Fig. 2 in a skeleton diagram form discloses the machine equipment in accordance with the invention, used in connection with the programming
- Fig. 3 in a skeleton diagram form discloses the connection to a multiprocessor bus system of the microcomputer, the program of which is to be fault located and the fault location equipment included on the board characteristic of the invention.
- a bigger computer e.g. a computer of the type VAX
- a target computer 2 has the form of or comprises a first microcomputer 3.
- the target computer and the microcomputer, respectively, can consist of units known per se.
- Developing a program for the microcomputer 3 is carried out by programming in the computer 1 and the developed program is communicated via a connection 4, 4' to the first microcomputer 3 where it is to be tested with regard to faults. It is essential that the fault location in the program of the first microcomputer can be carried out during running the program in the first microcomputer so that the fault location is not experienced as affecting the run of the program. So far, there has for this purpose been utilized a separate emulator 5, which in a known embodiment comprises two microcomputers 6 and 7. The fault location is carried out in a way known per se and will therefore not be described more closely here. In accordance with the invention and Fig. 2, it should be possible to carry out a programming and a fault location despite the lack of the separate emulator 5.
- the bigger computer 1 1 is connected to the target computer 2' and the first microcomputer 3', respectively, via the connection 4", correspondingly.
- a special board 8 with equipment for the fault location function is included in the target computer 2' .
- Said equipment is represented by a second microcomputer 9.
- the fault location equipment comprises the hard ware and the program necessary for carrying out the fault location during running the first microcomputer 3' without the performance characteristics of the program of the first microcomputer being affected inappropriately.
- a multiprocessor bus connection should be used.
- a connection is designated 10.
- the connection can consist of a bus connection known per se, e.g. of the type "MULTIBUS", "VME", etc.
- the first microcomputer 3" is connected to the bus connection 10. This connection can be done in a way known per se, e.g. by inserting a board 3a (see Fig. 2) in a board holder in a way known per se.
- the second microcomputer 9' is correspondingly connected to the connection by its board 8 being correspondingly inserted and connected.
- the equipment on the board 8 comprises hardware and a program for detecting the function course of the first microcomputer and for setting break points in the program of the first microcomputer. This function and detection can be carried out in a way known per se.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Multi Processors (AREA)
Abstract
L'agencement consiste à développer dans un ordinateur central (1, 1') un programme destiné à un premier micro-ordinateur (3, 3', 3''). Le programme développé est transmis au premier micro-ordinateur et on doit procéder à une localisation des défauts dans le programme communiqué pendant la marche simultanée du premier micro-ordinateur. Ce dernier est connecté à un bus de multiprocesseur (10). Un second micro-ordinateur (9, 9') est mis sous tension sur un module (8) constituant un matériel de localisation de défauts. Ledit matériel est raccordé au branchement du bus du multiprocesseur par introduction du module dans un porte-module en service. Le second micro-ordinateur peut être utilisé pour tester le programme en cours d'exécution dans le premier micro-ordinateur.The arrangement consists in developing in a central computer (1, 1 ') a program intended for a first microcomputer (3, 3', 3 ''). The developed program is transmitted to the first microcomputer and it is necessary to locate faults in the program communicated during the simultaneous operation of the first microcomputer. The latter is connected to a multiprocessor bus (10). A second microcomputer (9, 9 ') is powered up on a module (8) constituting fault location equipment. Said equipment is connected to the bus connection of the multiprocessor by introducing the module into a module holder in service. The second microcomputer can be used to test the program running in the first microcomputer.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE8601979A SE456781B (en) | 1986-04-29 | 1986-04-29 | DEVICE FOR TRANSFERING A PROGRAM FROM A VALUATION COMPUTER TO A TARGET COMPUTER AND TROUBLESHOOTING IN THE TRANSFERED PROGRAM |
SE8601979 | 1986-04-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0298988A1 true EP0298988A1 (en) | 1989-01-18 |
Family
ID=20364383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19870902846 Withdrawn EP0298988A1 (en) | 1986-04-29 | 1987-04-27 | Arrangement for communicating a program from a host computer to a target computer |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0298988A1 (en) |
JP (2) | JPH01502369A (en) |
SE (1) | SE456781B (en) |
WO (1) | WO1987006738A1 (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4167781A (en) * | 1976-10-12 | 1979-09-11 | Fairchild Camera And Instrument Corporation | Microprocessor system having a single central processing unit shared by a plurality of subsystems each having a memory |
US4428044A (en) * | 1979-09-20 | 1984-01-24 | Bell Telephone Laboratories, Incorporated | Peripheral unit controller |
EP0062978A3 (en) * | 1981-04-06 | 1982-12-22 | Secretary of State for Industry in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland | Apparatus for assisting fault-finding in data processing systems |
JPS5981750A (en) * | 1982-06-24 | 1984-05-11 | Fuji Electric Co Ltd | Multi-processor system |
-
1986
- 1986-04-29 SE SE8601979A patent/SE456781B/en not_active IP Right Cessation
-
1987
- 1987-04-27 EP EP19870902846 patent/EP0298988A1/en not_active Withdrawn
- 1987-04-27 JP JP50290287A patent/JPH01502369A/en active Pending
- 1987-04-27 WO PCT/SE1987/000215 patent/WO1987006738A1/en not_active Application Discontinuation
-
1996
- 1996-05-13 JP JP005121U patent/JPH081629U/en active Pending
Non-Patent Citations (1)
Title |
---|
See references of WO8706738A1 * |
Also Published As
Publication number | Publication date |
---|---|
SE8601979D0 (en) | 1986-04-29 |
JPH081629U (en) | 1996-11-29 |
WO1987006738A1 (en) | 1987-11-05 |
JPH01502369A (en) | 1989-08-17 |
SE456781B (en) | 1988-10-31 |
SE8601979L (en) | 1987-10-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19881021 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH DE FR GB IT LI LU NL SE |
|
17Q | First examination report despatched |
Effective date: 19900626 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19920317 |
|
APAF | Appeal reference modified |
Free format text: ORIGINAL CODE: EPIDOSCREFNE |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: CONRADI, BENGT |