JPS6426944A - Debugging device for computer system - Google Patents

Debugging device for computer system

Info

Publication number
JPS6426944A
JPS6426944A JP62182301A JP18230187A JPS6426944A JP S6426944 A JPS6426944 A JP S6426944A JP 62182301 A JP62182301 A JP 62182301A JP 18230187 A JP18230187 A JP 18230187A JP S6426944 A JPS6426944 A JP S6426944A
Authority
JP
Japan
Prior art keywords
cpu
interruptions
cpus
produced
cards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62182301A
Other languages
Japanese (ja)
Inventor
Tokuo Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62182301A priority Critical patent/JPS6426944A/en
Publication of JPS6426944A publication Critical patent/JPS6426944A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To ensure the effective debug of a computer system consisting of plural CPUs by using the emulator control cards to monitor the factors produced by the CPUs and applying the interruptions to the optional number of CPUs. CONSTITUTION:The emulator control cards 5 and 5a receive the detection signals of the events produced by its own CPU as well as the detection signals of those events received via a bus 12 and apply the interruptions to a pod target CPU 3 or CPU 3a which are controlled directly by both cards 5 and 5a themselves. Thus the CPU 3 and CPU 3a carry out the monitor programs and inform their states set right before the interruptions are applied to a host processor 10. Thus it is possible to use an event produced by a certain CPU to control quickly another CPU so that the effective debug is attained.
JP62182301A 1987-07-23 1987-07-23 Debugging device for computer system Pending JPS6426944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182301A JPS6426944A (en) 1987-07-23 1987-07-23 Debugging device for computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182301A JPS6426944A (en) 1987-07-23 1987-07-23 Debugging device for computer system

Publications (1)

Publication Number Publication Date
JPS6426944A true JPS6426944A (en) 1989-01-30

Family

ID=16115894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182301A Pending JPS6426944A (en) 1987-07-23 1987-07-23 Debugging device for computer system

Country Status (1)

Country Link
JP (1) JPS6426944A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292182U (en) * 1989-01-09 1990-07-23
JPH0625640U (en) * 1992-09-04 1994-04-08 品川商工株式会社 Tie

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292182U (en) * 1989-01-09 1990-07-23
JPH0625640U (en) * 1992-09-04 1994-04-08 品川商工株式会社 Tie

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