EP0265448A1 - Dispositif convertisseur analogique/numerique permettant de quantifier des signaux de tension de transmittance - Google Patents
Dispositif convertisseur analogique/numerique permettant de quantifier des signaux de tension de transmittanceInfo
- Publication number
- EP0265448A1 EP0265448A1 EP87901978A EP87901978A EP0265448A1 EP 0265448 A1 EP0265448 A1 EP 0265448A1 EP 87901978 A EP87901978 A EP 87901978A EP 87901978 A EP87901978 A EP 87901978A EP 0265448 A1 EP0265448 A1 EP 0265448A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- analog
- signal
- digital
- converter
- transmittance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
Definitions
- the present invention relates to analog/digital converter apparatus for converting analog signals representing transmittance into digital signals.
- Background Art Solid-state image sensors generally have a linear or area organization. A sensor will often have a row of sensor elements (usually photodiodes or photocapacitors) and one or more CCD shift registers. The elements sample light from an image and integrate (accumulate) charge representative of the intensity of such light. After this integration, the charge is transferred to an output CCD shift register. The charge is shifted out of the shift register and converted by a floating diffusion connected, to an MOS transistor into a voltage signal. The voltage signal is then amplified and digitized by an analog/digital converter.
- Area image sensors are used to scan photographic negatives to produce high resolution digital images. These systems measure the amount of light (transmittance) passing through the pixels of a film negative. It is advantageous that this be accomplished quite rapidly (at video rates) and with high accuracy.
- the transmittance voltage signal can vary over a wide voltage range. This places a number of severe constraints on the analog/digital converter. The converter must be able to rapidly quantize the voltage signal over this wide voltage range. Further, the transmittance signal must be converted into a density space before being delivered to a high speed printer. As is well known, density (D) is proportional to -LOG 10 (T), where T represents transmittance. For the sake of explanation, let us differentiate the function —log 10 (T). Assuming small quantizing steps we have approximately the relationship where T is the transmittance, ⁇ T is a transmittance quantizing step and ⁇ D is a density quantizing step. A quantizing step is the range between adjacent quantizing levels.
- a flash analog/digital converter is a parallel encoder. Briefly, turning to Fig. 1, a schematic of a flash converter is shown. It consists of a resistive voltage divider ladder having a plurality of resistors R. Comparators 12 are connected to such ladder. The digital output is provided by the circuitry 14. Encoder and latch circuitry 14 is connected to the comparators 12. A clock signal ⁇ is applied as an input to the comparators and circuitry 14.. The number of comparators and resistors R equals the number of quantization levels. A reference voltage is applied to the resistive ladder. Changes in this voltage change the quantizing steps of the converter. The maximum amplitude of the signal which can be accurately converted into a digital signal is determined by the reference voltage. As shown, the reference voltage is scaled by the resistors R and a different voltage level is applied to each comparator.
- the analog input voltage to a comparator exceeds the voltage applied from the resistive ladder, then a high output is produced not only by that comparator but by all the other comparators below its level.
- the outputs of the comparators are connected to circuitry 14.
- the encoder in circuitry 14 encodes the output into a binary code which is delivered for storage to a latch.
- the latch not only provides the output digital signal but also it provides an overflow signal. When the overflow signal is activated, it indicates that the input analog signal has exceeded the maximum quantizing level of the converter. In such a situation, the converter is said to be saturated.
- the reference voltage can vary only over a narrow range. This narrow range is not sufficient to change each quantizing step by a sufficient amount to correspond to changes in the analog transmittance voltage signal so as to provide proper output density.
- Fig. 1 illustrates in schematic form a conventional prior art flash analog/digital converter
- Fig. 2 shows in block diagram form, the elements of a system for digitizing the output signals from an area sensor which receives light which passes through a film negative and for arranging such digitized signals spacially to form a digitized image in the frame store of a memory plane
- Fig. 3 shows the quantization levels and digital codes for the converters 18a and 18b shown in Fig. 2;
- Figs. 4 and 5 show different arrangements of flash analog/digital converters which can be used in the system of Fig. 2.
- a solid-state area image sensor 15 with more than for example a million picture elements (pixels) receives light which passes through a photographic negative (not shown). (It will be understood that a linear sensor can also be used.) The light which passes through the negative represents transmittance. The elements convert the incoming light into charge. This charge is accumulated in either a photodiode or photocapacitor and represents the transmittance of the light which has passed through the negative. After the charge is accumulated, is transferred to a horizontal shift register 15a which operates in a well known manner. The charge is shifted in the register 15a in the direction shown by the arrow past a floating diffusion 15b.
- the floating diffusion 15b is coupled to an MOS transistor (not shown) which provides a voltage level representative of the accumulated charge which passes by the floating diffusion.
- MOS transistor not shown
- the architecture of sensor 15 can be for example interline-transfer or frame-transfer as is well known to those skilled in the art.
- the transmittance voltage signal from the diffusion 15b is provided to amplifiers 16a and 16b, respectively.
- Amplifiers 16a has a gain of 8 and amplifier 16b has a unitary gain.
- the output voltage signals from amplifiers 16a and 16b are respectively provided to identical flash analog/digital converters 18a and 18b. Each of these converters 18a and 18b receives the identical reference voltage.
- each of these flash analog/digital converters is applied to a logic circuit 22 which determines whether the digital output from converter 18a or converter 18b is to represent the transmittance and adds logic zeros to selected bit positions of the selected converter digital output signal.
- the logic gate 22 delivers the selected digital signal which represents a digital pixel, to a buffer 23.
- the buffer 23 causes each digital pixel to be stored in a particular location of a memory plane of a frame store 24.
- the numerical value of each digital pixel represents the transmittance of a pixel of a negative.
- a sequencer 26 provides the necessary clock signals to the converters 18a and 18b and control signals to the other logic elements. After a digital image is formed in the memory plane of frame store 24, it is delivered to a printer 28.
- the printer 28 will be understood to include electronics such as a digital image processor which processes the digital image so that the printer will produce an output print which is more suitable for viewing than if processing had not taken place.
- the processor may function in accordance with image enhancing algorithms and tone scale enhancing algorithms. It must of course, as noted above, convert the transmittance digital signal into a logarithmic scale which more accurately represents density space.
- An example of a printer which can be used in response to these enhanced digital pixels is a laser printer such as disclosed for example, in commonly assigned U.S. Patent Application Serial No. 619,454, entitled "Light Beam Intensity Controlling Apparatus," filed June 11, 1984 in the names of Baldwin et al.
- Converter 18a measures the input signal with a maximum quantizing level of 1/8 V M .
- Converter 18b measures the input signal with a maximum quantizing level of V M , where V M is the maximum possible voltage of the input transmittance voltage signal.
- each A/D converter 18a and 18b provides a nine-bit word representing 512 quantization levels. If its input signal level exceeds the level 1/8 V M , then converter 18a is saturated and provides an overflow signal. In response to this overflow signal, the logic 22 selects the output of the converter 18b.
- the converters 18a and 18b are identical and have 512 quantizing levels and each receives the identical input reference voltage.
- a quantizing step is:
- a quantizing step is:
- the output of a logic 22 is a 12-bit digital word. If the analog input voltage provided to the amplifiers 16a and 16b is less than 1/8 V M , then the converter 18a will not provide an overflow bit and the logic 22 will select the output of the converter 18a to represent the transmittance. Since logic 22 provides a 12-bit word, it adds three logic zero bits to the highest order bit positions as set forth in Table 1.
- logic 22 adds three logic zeros to the least significant bit positions of the 12-bit signal as set forth in Table 2.
- amplifier 16a and 16b are still provided. These amplifiers have the same gain as their corresponding amplifiers in Fig. 2.
- Amplifiers 16a and 16b are selectively adapted to be connected to a 9-bit flash analog/digital converter 18.
- a comparator 30 When the input voltage signal is greater than 1/8 V M , a comparator 30 provides an output signal which actuates a drive circuit that drives a switch 32 (shown schematically) to couple the output of amplifier 16b to the analog/digital converter 18b.
- Logic 22a is similar to logic 22 of Fig. 2 in that it is responsive to the output of the comparator 30 and the analog/digital converter 18.
- Logic 22b provides a 12-bit word output.
- flash analog/digital converters 18a', 18b' and 18c' These are 8-bit word output converters.
- Three gain control amplifiers are provided 16a', 16b' and 16c'.
- Amplifier 16a' has a gain of 16
- amplifier 16b' has a gain of 4
- amplifier 16c' has a gain of 1.
- Analog/digital converters 18a' and 18b' provide overflow signals to the logic 22b. These overflow signals provide the information necessary for logic 22b to select the appropriate analog/digital converter.
- the number of quantizing levels and the specific transmission voltage at which quantizing steps are to be changed to provide a desired quality of image density can be determined experimentally.
- Very high speed A/D converters which use flash A/D converters can rapidly convert analog signals representing transmittance into digital signals.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Convertisseur analogique/numérique utilisant des convertisseurs rapides anologiques/numériques pour convertir les signaux des tensions de transmission d'entrée en des signaux numériques présentant différents pas de quantification.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US84341086A | 1986-03-24 | 1986-03-24 | |
US843410 | 1986-03-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0265448A1 true EP0265448A1 (fr) | 1988-05-04 |
Family
ID=25289893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP87901978A Withdrawn EP0265448A1 (fr) | 1986-03-24 | 1987-03-09 | Dispositif convertisseur analogique/numerique permettant de quantifier des signaux de tension de transmittance |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0265448A1 (fr) |
WO (1) | WO1987006080A2 (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006851A (en) * | 1988-07-18 | 1991-04-09 | Matsushita Electric Industrial Co., Ltd. | Analog-to-digital converting system |
DE3935617A1 (de) * | 1989-10-26 | 1991-05-02 | Bruker Analytische Messtechnik | Infrarot-fouriertransformations-spektrometer |
US5164726A (en) * | 1991-06-12 | 1992-11-17 | Eastman Kodak Company | Self calibrating dual range a/d converter |
US5600317A (en) * | 1994-06-14 | 1997-02-04 | Stage Tec Entwicklungsgesellschaft Fur Professionelle Audiotechnik Mbh | Apparatus for the conversion of analog audio signals to a digital data stream |
DE19502047C2 (de) * | 1995-01-12 | 1996-12-05 | Stage Tec Gmbh | Verfahren zur Analog-Digital-Wandlung von Signalen |
US5479119A (en) * | 1994-11-23 | 1995-12-26 | Analog Devices, Inc. | High speed active overvoltage detection and protection for overvoltage sensitive circuits |
US6333707B1 (en) * | 1998-02-19 | 2001-12-25 | Nortel Networks Limited | Dynamic range extension of wideband receiver |
US7365665B2 (en) | 2005-12-30 | 2008-04-29 | Bookham Technology Plc | Photodiode digitizer with fast gain switching |
GB2433851A (en) * | 2006-02-01 | 2007-07-04 | Bookham Technology Plc | Optical receiver which selects between a digital signal produced by a high gain path and a digital signal produced by a low gain path |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE345023B (fr) * | 1970-06-01 | 1972-05-08 | Saab Scania Ab | |
IE38230B1 (en) * | 1972-09-15 | 1978-01-18 | Ind Des Telecommunications Com | Improvements in digital coders |
FR2236315A1 (en) * | 1973-07-06 | 1975-01-31 | Coulter W | Circuit for splitting measuring range of pulse amplitude processing un - uses analogue digital converter with lower amplitude acceptance range feeding logic |
US4129864A (en) * | 1976-03-03 | 1978-12-12 | The United States Of America As Represented By The Secretary Of Commerce | High speed, wide dynamic range analog-to-digital conversion |
DE3128306A1 (de) * | 1981-07-17 | 1983-02-03 | Krautkrämer, GmbH, 5000 Köln | Schaltungsvorrichtung zur digitalisierung und extremwertermittlung analoger signale |
-
1987
- 1987-03-09 EP EP87901978A patent/EP0265448A1/fr not_active Withdrawn
- 1987-03-09 WO PCT/US1987/000453 patent/WO1987006080A2/fr unknown
Non-Patent Citations (1)
Title |
---|
See references of WO8706080A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO1987006080A3 (fr) | 1988-03-24 |
WO1987006080A2 (fr) | 1987-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6538593B2 (en) | Method and apparatus for converting a low dynamic range analog signal to a large dynamic range floating-point digital representation | |
US8896738B2 (en) | Solid-state image pickup device and signal processing method therefor | |
US6831689B2 (en) | Optical imager using a method for adaptive real-time expanding of the dynamic range | |
JP5711975B2 (ja) | 改善されたダイナミックレンジを有するイメージング配列 | |
EP0495055A1 (fr) | Convertisseur analogique-numerique de type adaptatif a double gamme dynamique | |
US5355164A (en) | Method and apparatus of correction image read signals by removing the influence of dark current therefrom | |
JPS6038988A (ja) | 固体撮像素子を用いた静止画像撮像装置 | |
US5521640A (en) | Color image array scanner with high resolution monochrome mode | |
EP0265448A1 (fr) | Dispositif convertisseur analogique/numerique permettant de quantifier des signaux de tension de transmittance | |
US4862286A (en) | Image reading apparatus which adjusts image signals to improve signal balance | |
US4723174A (en) | Picture image processor | |
US5191445A (en) | Image reader | |
EP0349027B1 (fr) | Détermination d'une portion d'image d'un dispositif de prise d'image à l'état solide | |
US5955725A (en) | Digitizing CCD array system | |
KR100801655B1 (ko) | 디지털 화소 센서 리드아웃에서의 화소 재배열 회로 및 방법 | |
US6353401B1 (en) | Optical sensor array with zone-programmable gain and offset | |
US5894527A (en) | Selectively outputting image information of differing amplifications | |
JPS6135751B2 (fr) | ||
JPH05183143A (ja) | 多素子光センサ装置 | |
JPH06311441A (ja) | 固体撮像装置 | |
JP2650969B2 (ja) | デジタルテレビジョンカメラ装置 | |
US7301678B2 (en) | Image reading device and gain setting method in image reading device | |
JPH066674A (ja) | 撮像装置 | |
JPS6135753B2 (fr) | ||
SU1758901A1 (ru) | Устройство дл коррекции сигналов полутонового изображени фотоэлектронного преобразовател |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IT |
|
D17D | Deferred search report published (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19871229 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: MILCH, JAMES, ROGER |