EP0238841B1 - Multiprocesseur de commande protégé contre les erreurs et à grande disponibilité, dans un système de commutation, et méthode pour l'exploitation de configuration de la mémoire de cette commande centrale - Google Patents
Multiprocesseur de commande protégé contre les erreurs et à grande disponibilité, dans un système de commutation, et méthode pour l'exploitation de configuration de la mémoire de cette commande centrale Download PDFInfo
- Publication number
- EP0238841B1 EP0238841B1 EP87102239A EP87102239A EP0238841B1 EP 0238841 B1 EP0238841 B1 EP 0238841B1 EP 87102239 A EP87102239 A EP 87102239A EP 87102239 A EP87102239 A EP 87102239A EP 0238841 B1 EP0238841 B1 EP 0238841B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- mb3b
- memory block
- mb3a
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/54558—Redundancy, stand-by
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
Definitions
- the invention relates to a further development of the special multiprocessor central control unit defined in the preamble of claim 1 and the further development of a memory configuration method optimized for this.
- the invention is based on the German patent application DE-A-33 34 773 out.
- the EDC code error protection of a memory block described there can be particularly reliable, for example according to the German patent application DE-A-33 19 710 be carried out by also capturing the address of the memory location with the EDC code.
- Such a central control unit is said to be extremely fault tolerant, i.e. Errors that occur should be recognized as quickly as possible and defective or sufficiently suspect organs of the central memory should be eliminated as quickly as possible before the error results in further errors that could impair the operation of the switching system. Therefore, in this central control unit, the control units of the memory blocks - normally also the bus system and the central processors - are each doubled and error-protected for themselves - apart from a certain tolerable slip - are operated in microsynchronous parallel.
- Such a central control unit should have an extremely high availability, that is to say it should be at most for a few seconds or minutes a year uninterrupted operation - have any serious malfunctions.
- the central main memory of the central control unit should therefore never trigger a complete breakdown of the switching operation. Even in the event of failure and disconnection of one - often also diverse - the organs of the central memory, the switching operation should therefore be able to be maintained as fault-tolerant as possible.
- the invention thus controls the central memory of the switching system particularly quickly and particularly fault-tolerant, i.e. extremely reliably, by means of duplicate memory configuration processors which can be formed, for example, by means of commercially available 8-bit or, for example, also 32-bit processor chips and which special circuit and special operation work particularly quickly and above all reliably.
- duplicate memory configuration processors which can be formed, for example, by means of commercially available 8-bit or, for example, also 32-bit processor chips and which special circuit and special operation work particularly quickly and above all reliably.
- one of the one or more of the central processors of the central control unit is generally no longer required for the memory configuration and, accordingly, the central bus system is no longer burdened by access to the central memory for the configuration of this central memory.
- the central processors can then fully devote themselves to their own tasks and are therefore even more than previously available for their own tasks.
- the availability of the bus system, and of the entire central control unit in general is further increased.
- Claim 2 describes measures that allow the memory configuration, including the refresh, to be carried out fully automatically, even in the event of faults in the operation of a memory block.
- the central control unit example shown in this figure corresponds very largely to the figure and the description of the German patent application already mentioned above DE-A-33 34 773, Incidentally, the central control unit example, which - with emphasis on other tasks or aspects of this central control unit - in the other German patent applications DE-A-33 34 792, DE-A-33 34 765, DE-A-33 34 766, DE-A-33 34 797, DE-A-33 34 796, and DE-A-33 19 710 is described. Therefore, the structure and the mode of operation of the central control unit example shown in the figure of the present document need no longer be explained in detail. Instead, it is sufficient to deal only with the special peculiarities of the structure according to the invention and the memory configuration method optimized therefor.
- the central control unit shown in the figure of the present document has, as a special feature in the central main memory CMY, above all the memory configuration processor pair SpP0 / SpP1 which is operated extremely fail-safe.
- its processors each have their own processor EDC circuits EDC0 / EDC1 and additionally their own processor comparator circuit VP for comparing the machine commands and / or the data of the two memory configuration processors.
- this figure also has four pairs of memory blocks MB0a / MB0b .... MB3a / MB3b in the central main memory CMY, the memory control units of which - apart from a possibly tolerated certain slip - are operated in microsynchronous parallel.
- these memory blocks are extremely error-protected by means of memory EDC circuits M: EDC0a / M: EDC0b ; M: EDC3a / M: EDC3b operated, in addition - despite any EDC corrections - the addresses and / or the information to be written and / or the information read are compared with each other by means of memory comparator circuits V0 ... V3.
- the figure thus shows a particularly highly error-protected, highly available multiprocessor central control unit of a switching system - e.g. of a telephone switching system - with four error-protected in normal operating times - apart from a possibly tolerated certain slippage - pairs of memory blocks MB0a / MB0b ... MB3a / MB3b operated in parallel, each consisting of a first (a) and a second (b) Block of memory exist.
- These memory block pairs MB are connected to the central, also doubled, - apart from the possibly tolerated slip - error-protected microsynchronously operated bus system B: CMY0 / B: CMY1 and form the main components of the central main memory CMY.
- central processors BP0, BP1, CP0 .... CP9, IOC0, IOC1 .... processing different current switching orders are connected in parallel to the bus system B: CMY, these central processors BP, CP, IOC also being used are doubled in themselves and are error-protected - also here, apart from a possible tolerated certain slippage - to be operated in a microsynchronous parallel.
- At least a large number of the central processors BP, CP, IOC has, for example because of deliberate limitation of the memory addresses that can be sent by the processor in question, normally to only a part of the memory locations of the central memory CMY, that is to say only to one of the memory sections in each of the two memory blocks of at least one of the memory block pairs, eg MB3a / MB3b, for a read and / or write operation, access, normally identical information being stored in the relevant addressable memory sections of the two memory blocks of a pair of memory blocks.
- the information stored in the second memory block MB3b is gradually re-loaded using a - for example in the memory configuration processor pair SpP0 / SpP1 or in the bus system B: CMY0 / B: CMY1 - corrected address generator.
- the reloading is achieved by reading from the first memory block MB3a of this memory block pair MB3a / MB3b and by writing the information read from the first memory block MB3a into this second memory block MB3b, provided that the second memory block MB3b then again works correctly, during this reloading of the second memory block while a simultaneous write operation of the first memory block MB3a, the same information written in the first memory block MB3a is immediately written into the second memory block MB3b at the same address.
- the memory-specific, micro-synchronously operated memory configuration processor pair SpP0 / SpP1 which is used for automatic memory configuration, is therefore directly connected to the central main memory CMY and maybe also physically there - to reduce the signal propagation times on the lines - and therefore acts directly instead of via it central bus system B: CMY0 / B: CMY1 on the central main memory CMY and there above all directly on the control of the memory blocks MB0a .... MB3b. Accordingly, the central bus system B: CMY0 / B: CMY1 and the central processors BP, CP, IOC are relieved of memory configuration tasks.
- the operation of the memory configuration processor pair SpP0 / SpP1 is also checked for itself by means of its own processor EDC circuit EDCO, EDC1 or processor parity bit circuit and, in addition, despite this own EDC code or parity bit check, additionally by means of the processor's own processor Comparator circuit VP continuously checked.
- This memory-specific error-protected memory configuration processor pair Sp0 / SpP1 - or a large number of such memory-specific pairs - increases the reliability of the operation of the central main memory extremely because of its extremely error-protected operation.
- This memory configuration processor pair SpP0 / SpP1 — or the memory configuration processor pairs — preferably controls the timely execution of all refresh cycles for the central memory blocks MB, at least as long as the pair in question operates according to its own checks.
- this pair controls, directly or indirectly, the checks and corrections of the stored information read during a refresh cycle, preferably by means of the memory EDC circuits M: EDC0a .... M: EDC3b, during the refresh cycle. Above all, it controls as soon as one of the memory EDC circuits, e.g.
- M EDC3b
- CMY0 / B CMY1
- CMY1 the separation of this memory block MB3b from the bus system B
- CMY0 / B CMY1
- the subsequent special operation for reloading attempts to reload this separated memory block MB3b.
- the successful completion of the reloading it controls the switching on of the relevant memory block MB3b to the bus system B: CMY0 / B: CMY1 and the transition to the microsynchronous parallel operation of both memory blocks of the relevant memory block pair MB3a / MB3b, i.e. the transition to normal operating time.
- EDC or comparator circuits V / VP is facilitated, for example, by the fact that at least one of the memory configuration processors SpP0 / SpP1 in a separate register or perhaps also in a special memory area used as a register, e.g.
- an alarm can be triggered, for example in such a way that the organ in question, - for example the relevant memory block pair MBx, now finally separated from the central bus system B: CMY0 / B: CMY1, or internally in the central memory from its storage environment, and if possible immediately - preferably again with the help of the memory configuration processor pair - by a replacement organ, - for example, by a spare pair of memory blocks, is replaced, and - if this was a replacement memory block pair, it is reloaded if possible and as required.
- the central main memory CMY operated according to the invention can continue to remain fully available - often without any significant loss: after one of the processor EDC circuits, e.g. EDC1, ascertained multiple errors in the relevant memory configuration processor SpP, which it can no longer easily correct, can namely the associated memory configuration processor, e.g. SpP1, are switched off and the other memory configuration processor SpP0 alone takes over the memory configuration.
- EDC circuits e.g. EDC1
- the associated memory configuration processor e.g. SpP1
- the relevant memory configuration processor pair SpP0 / SpP1 can also be switched off and immediately replaced fully effectively by switching on a replacement processor pair . Even after a determination by a processor comparator circuit VP - e.g. despite correction by an associated processor EDC circuit, e.g. EDC1, occurring errors, the entire associated memory configuration processor pair SpP0 / SpP1 can be switched off and immediately replaced effectively by switching on a replacement memory configuration processor pair. In this case, this control of the replacement can also have been initiated by the memory configuration processor pair itself, which is separated in this case.
Claims (9)
- Unité de commande centrale à multiprocesseur, protégée contre les erreurs et présentant une grande disponibilité, d'un système de commutation -par exemple d'un système de commutation téléphonique-, dans laquelle* une mémoire centrale principale (CMY) est doublée et# comporte pour préciser, un ou plusieurs couples (MB3a/MB3b) de blocs de mémoire fonctionnant en parallèle d'une manière en soi microsynchrone pendant des durées de fonctionnement normales -indépendamment d'un certain glissement éventuellement toléré-,# et comporte donc au moins un premier bloc de mémoire (MB3a) et un second bloc de mémoire (MB3b) fonctionnant en parallèle, d'une manière microsynchrone, avec le premier bloc de mémoire (MB3a) -indépendamment d'un glissement éventuellement toléré,* la mémoire principale centrale (CMY), c'est-à-dire le couple (MB0a/MB0b) du bloc de mémoire ou les couples (MB0a/MB0b, ... MB3a/MB3b) de blocs de mémoire ainsi que la multiplicité des processeurs centraux (BP0, BP1, CP0, ... CP9, IOC0, IOC1, ...), qui traitent des ordres instantanés de commutation respectivement différents, sont raccordés en parallèle à un système de bus central (B:CMY0, B:CMY1),* les informations mémorisées en parallèle dans les blocs de chaque couple (par exemple MB3a/MB3b) de blocs de mémoire, sont mémorisées en soi dans chaque bloc de mémoire, en étant protégées contre les erreurs, selon un code EDC, par des circuits EDC de mémoire (M:EDC0a...M:EDC3b) associés individuellement aux différents blocs de mémoire,* au moins un nombre élevé des processeurs centraux (BP0... IOC1...) ont accès à respectivement au moins l'une des sections de mémoire -qui mémorisent normalement des informations identiques- dans chacun des deux blocs de mémoire d'au moins l'un des couples de blocs de mémoire (par exemple MB3a/MB3b) pour une opération de lecture/d'enregistrement, et* pendant les durées de fonctionnement particulier d'un couple de blocs de mémoire (par exemple MB3a/MB3b,caractérisé par le fait que# c'est-à-dire après qu'une erreur multiple déterminée par l'un des circuits EDC de mémoire (par exemple M:EDC3b) et qui n'est plus corrigible par ce circuit EDC, dans un bloc de mémoire dénommé second bloc de mémoire (par exemple MB3b) d'un tel couple de blocs de mémoire (MB3a/MB3b),- le second bloc de mémoire (MB3b) est déconnecté du système de bus (B:CMY0/B:CMY1) au moyen d'une configuration automatique de mémoire, et ensuite l'autre bloc de mémoire, à savoir le premier bloc de mémoire (MB3a), de ce couple de blocs de mémoire (MB3a/MB3b) exécute seul l'opération de lecture/d'enregistrement avec les processeurs centraux considérés (BP0...IOC1),- pendant l'état de déconnexion, les informations mémorisées dans le second bloc de mémoire (MB3b) sont corrigées petit à petit par# un essai de nouveau chargement réalisé à l'aide d'un générateur d'adresses et exécuté d'une manière entièrement automatique éventuellement déjà juste après la déconnexion du second bloc de mémoire (MB3b), mais automatiquement au moins au plus tard après une réparation du second bloc de mémoire (MB3b) après une impulsion de déclenchement,# à savoir par lecture à partir du premier bloc de mémoire (MB3a) de chaque couple de blocs de mémoire (MB3a/MB3b) et par enregistrement des informations, lues à partir du premier bloc de mémoire (MB3b) dans ce second bloc de mémoire (MB3b), dans la mesure où alors le second bloc de mémoire (MB3b) travaille à nouveau sans erreur,- auquel cas, lorsque pendant ce nouveau chargement, exécuté petit-à-petit, du second bloc de mémoire (MB3b), une opération d'enregistrement du premier bloc de mémoire (MB3b) est simultanément exécutée d'une manière intercalée, la même information, qui est enregistrée dans le premier bloc de mémoire (MB3b), est enregistrée immédiatement à la même adresse également dans le second bloc de mémoire (MB3b),* pour la configuration automatique de la mémoire, au moins un seul couple de processeurs de configurations de mémoire (SpP0/SpP1), qui est propre à la mémoire et fonctionne respectivement en parallèle d'une manière microsynchrone - également indépendamment d'un certain glissement éventuellement toléré-,- et dont le fonctionnement est également contrôlé en soi à l'aide d'un circuit particulier à code EDC du processeur ou à bit de parité du processeur (EDC0, EDC1), et- dont le fonctionnement est contrôlé en permanence, en dépit de ce contrôle particulier du code EDC ou du bit de parité, à l'aide d'un# circuit comparateur de processeurs (VP) qui compare les instructions machine individuelles et/ou les résultats de traitement individuels des processeurs associés de configuration de mémoire (SpP0/SpP1),est raccordé directement à la mémoire centrale principale (CMY), sans passer par l'intermédiaire du système de bus central (B:CMY0/B:CMY1).
- Procédé de fonctionnement de configuration de mémoire pour une unité de commande centrale suivant la revendication 1, caractérisé par le fait que* chaque fois que le couple considéré de processeurs de configuration de mémoire (SpP0/SpP1) -ou les couples de processeurs de configuration de mémoire- travaille parfaitement et conformément à ses contrôles propres (VP, EDC0/EDC1), ce couple de processeurs de configuration de mémoire- déclenche les cycles de régénération des blocs de mémoire (MB0a...MB0b),- permet et/ou exécute, pendant les cycles de régénération, des contrôles et des corrections des informations mémorisées lues pendant le cycle de régénération, à l'aide du code EDC (M:EDC0a...M:EDC3b),- après une erreur multiple déterminée par l'un des circuits EDC de mémoire (par exemple M:EDC3b) d'un bloc de mémoire (alors MB3b) et qui ne peut plus être corrigée par ce circuit, dans le bloc de mémoire considéré (MB3b), déconnecte ce bloc de mémoire (MB3b) du système de bus (B:CMY0/B:CMY1) et déclenche et/ou exécute le fonctionnement particulier pour des essais de nouveaux chargements pour réaliser le nouveau chargement de ce bloc de mémoire déconnecté (MB3b), et- à la fin du nouveau chargement du bloc de mémoire considéré (MB3b), raccorde à nouveau ledit bloc de mémoire au système de bus (B:CMY0/B:CMY1) et déclenche et/ou exécute le fonctionnement en parallèle microsynchrone des deux blocs de mémoire du couple considéré de blocs de mémoire (MB3a/MB3b), c'est-à-dire le passage à la durée de fonctionnement normale.
- Procédé suivant la revendication 2, caractérisé par le fait que* au moins l'un des processeurs de configuration de mémoire (SpP0/SpP1) consigne dans une zone particulière de mémoire (par exemple dans MB0a/MB0b) respectivement une indication concernant- l'erreur sur laquelle est basée la déconnexion par rapport au système de bus (B:CMY0/B:CMY1),- ainsi que le bloc de mémoire déconnecté (MB3b) ,- éventuellement également, d'une manière plus ou moins précise, l'adresse à laquelle l'erreur considérée a été déterminée.
- Procédé suivant la revendication 2 ou 3, caractérisé par le fait que pendant les durées de fonctionnement normal, au moins lors de la lecture ou de la régénération,* les informations mémorisées dans les deux blocs de mémoire d'un couple de blocs de mémoire (par exemple MB3a/MB3b) sont comparées de façon supplémentaire entre elles dans un circuit comparateur de mémoire (V0...V3), en dépit du contrôle EDC exécuté lors de la lecture et/ou de la régénération, et* en cas d'inégalité entre les informations comparées, l'opération considérée dans la mémoire, c'est-à-dire par exemple la lecture, est répétée.
- Procédé suivant la revendication 4, caractérisé par le fait qu'après une apparition réitérée de l'inégalité* le couple considéré de processeurs de configuration de mémoire (SpP0/SpP1) déclenche une alarme, par exemple le couple considéré de blocs de mémoire est déconnecté du système de bus central (B:CMY0/B:CMY1) et est remplacé par un couple de blocs de mémoire de remplacement.
- Procédé suivant l'une des revendications 2 à 5, caractérisé par le fait qu'après une erreur qui est déterminée par l'un des circuits EDC de processeurs (par exemple EDC1) ou par le circuit de bit de parité des processeurs et qui ne peut plus être corrigée par ce circuit* le processeur associé de configuration de mémoire (par exemple SpP1) est déconnecté, et* d'autres processeurs de configuration de mémoire (SpP0) du couple considéré de processeurs de configuration de mémoire (SpP0/SpP1) prend en charge à lui-seul la configuration de mémoire.
- Procédé suivant l'une des revendications 2 à 5, caractérisé par le fait qu'après une erreur qui est déterminée par l'un des circuits EDC des processeurs (par exemple EDC1) ou par un circuit de bits de parité des processeurs et ne peut plus être corrigé par le circuit,* le couple considéré de processeurs de configuration de mémoire (SpP0/SpP1) est déconnecté et est remplacé par le branchement d'un couple de processeurs de configuration de mémoire de remplacement.
- Procédé suivant l'une des revendications 2 à 7, caractérisé par le fait qu'après la détermination d'une erreur par un circuit comparateur à processeurs (VP)- éventuellement en dépit d'une correction par un circuit EDC de processeurs (par exemple EDC1) qui fait partie de ce couple de processeurs de configuration de mémoire (SpP0/SpP1),* le couple associé de processeurs de configuration de mémoire (SpP0/SpP1) est déconnecté (par exemple au moyen de Sc) et est remplacé au moyen du branchement d'un couple de processeurs de configuration de mémoire de remplacement.
- Procédé suivant l'une des revendications 2 à 8, caractérisé par le fait que* le couple considéré de processeurs de configuration de mémoire (SpP0/SpP1) déclenche et/ou exécute en supplément, pendant des intervalles de temps, l'appel et l'élaboration d'un programme particulier de contrôle, mémorisé dans une zone particulière de mémoire (par exemple dans MB0a/MB0b) pour un test de circuits utilisés pour l'identification d'erreurs,- par exemple pour un test des circuits EDC de mémoire (M:EDC) et/ou des circuits EDC de processeurs (EDC0/EDC1) et/ou des circuits comparateurs de mémoire (V0...V3) et/ou du circuit comparateur de processeurs (VP).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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AT87102239T ATE69346T1 (de) | 1986-03-12 | 1987-02-17 | Fehlergesicherte, hochverfuegbare multiprozessor- zentralsteuereinheit eines vermittlungssystemes und verfahren zum speicherkonfigurationsbetrieb dieser zentralsteuereinheit. |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3608245 | 1986-03-12 | ||
DE3608245 | 1986-03-12 | ||
DE3625036 | 1986-07-24 | ||
DE3625036 | 1986-07-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0238841A1 EP0238841A1 (fr) | 1987-09-30 |
EP0238841B1 true EP0238841B1 (fr) | 1991-11-06 |
Family
ID=25841898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP87102239A Expired - Lifetime EP0238841B1 (fr) | 1986-03-12 | 1987-02-17 | Multiprocesseur de commande protégé contre les erreurs et à grande disponibilité, dans un système de commutation, et méthode pour l'exploitation de configuration de la mémoire de cette commande centrale |
Country Status (11)
Country | Link |
---|---|
US (1) | US4860333A (fr) |
EP (1) | EP0238841B1 (fr) |
CN (1) | CN1016828B (fr) |
AR (1) | AR245831A1 (fr) |
AT (1) | ATE69346T1 (fr) |
BR (1) | BR8701107A (fr) |
DE (1) | DE3774309D1 (fr) |
DK (1) | DK166702B1 (fr) |
FI (1) | FI89443C (fr) |
GR (1) | GR3003729T3 (fr) |
PT (1) | PT84445B (fr) |
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US7039771B1 (en) | 2003-03-10 | 2006-05-02 | Marvell International Ltd. | Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers |
US7064915B1 (en) | 2003-03-10 | 2006-06-20 | Marvell International Ltd. | Method and system for collecting servo field data from programmable devices in embedded disk controllers |
US7526691B1 (en) | 2003-10-15 | 2009-04-28 | Marvell International Ltd. | System and method for using TAP controllers |
US7139150B2 (en) * | 2004-02-10 | 2006-11-21 | Marvell International Ltd. | Method and system for head position control in embedded disk drive controllers |
US7120084B2 (en) | 2004-06-14 | 2006-10-10 | Marvell International Ltd. | Integrated memory controller |
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US7802026B2 (en) * | 2004-11-15 | 2010-09-21 | Marvell International Ltd. | Method and system for processing frames in storage controllers |
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JP5014899B2 (ja) * | 2007-07-02 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | 再構成可能デバイス |
US9847105B2 (en) * | 2016-02-01 | 2017-12-19 | Samsung Electric Co., Ltd. | Memory package, memory module including the same, and operation method of memory package |
CN108153648B (zh) * | 2017-12-27 | 2021-04-20 | 西安奇维科技有限公司 | 一种实现灵活调度的多冗余计算机的方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2232256A5 (fr) * | 1973-05-29 | 1974-12-27 | Labo Cent Telecommunicat | |
US3882455A (en) * | 1973-09-14 | 1975-05-06 | Gte Automatic Electric Lab Inc | Configuration control circuit for control and maintenance complex of digital communications system |
IT1111606B (it) * | 1978-03-03 | 1986-01-13 | Cselt Centro Studi Lab Telecom | Sistema elaborativo modulare multiconfigurabile integrato con un sistema di preelaborazione |
US4371754A (en) * | 1980-11-19 | 1983-02-01 | Rockwell International Corporation | Automatic fault recovery system for a multiple processor telecommunications switching control |
DE3334773A1 (de) * | 1983-09-26 | 1984-11-08 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum betrieb eines in normalbetriebszeit parallel betriebenen speicherblockpaares |
-
1987
- 1987-02-17 DE DE8787102239T patent/DE3774309D1/de not_active Expired - Fee Related
- 1987-02-17 AT AT87102239T patent/ATE69346T1/de not_active IP Right Cessation
- 1987-02-17 EP EP87102239A patent/EP0238841B1/fr not_active Expired - Lifetime
- 1987-03-04 AR AR87306914A patent/AR245831A1/es active
- 1987-03-11 US US07/024,749 patent/US4860333A/en not_active Expired - Fee Related
- 1987-03-11 BR BR8701107A patent/BR8701107A/pt not_active IP Right Cessation
- 1987-03-11 PT PT84445A patent/PT84445B/pt not_active IP Right Cessation
- 1987-03-11 DK DK124587A patent/DK166702B1/da not_active IP Right Cessation
- 1987-03-11 FI FI871059A patent/FI89443C/fi not_active IP Right Cessation
- 1987-03-12 CN CN87101839A patent/CN1016828B/zh not_active Expired
-
1992
- 1992-02-06 GR GR910401544T patent/GR3003729T3/el unknown
Also Published As
Publication number | Publication date |
---|---|
BR8701107A (pt) | 1987-12-29 |
DK166702B1 (da) | 1993-06-28 |
FI89443C (fi) | 1993-09-27 |
PT84445B (pt) | 1989-10-04 |
ATE69346T1 (de) | 1991-11-15 |
FI871059A (fi) | 1987-09-13 |
PT84445A (de) | 1987-04-01 |
GR3003729T3 (fr) | 1993-03-16 |
US4860333A (en) | 1989-08-22 |
FI89443B (fi) | 1993-06-15 |
FI871059A0 (fi) | 1987-03-11 |
CN1016828B (zh) | 1992-05-27 |
DK124587A (da) | 1987-09-13 |
DE3774309D1 (de) | 1991-12-12 |
DK124587D0 (da) | 1987-03-11 |
AR245831A1 (es) | 1994-02-28 |
EP0238841A1 (fr) | 1987-09-30 |
CN87101839A (zh) | 1987-12-02 |
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