EP0227691A1 - Procede et appareil de generation d'images-ecran multicolores - Google Patents

Procede et appareil de generation d'images-ecran multicolores

Info

Publication number
EP0227691A1
EP0227691A1 EP86901655A EP86901655A EP0227691A1 EP 0227691 A1 EP0227691 A1 EP 0227691A1 EP 86901655 A EP86901655 A EP 86901655A EP 86901655 A EP86901655 A EP 86901655A EP 0227691 A1 EP0227691 A1 EP 0227691A1
Authority
EP
European Patent Office
Prior art keywords
color
color component
data bits
digital
corresponding pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86901655A
Other languages
German (de)
English (en)
Inventor
Kiran R. Mundkur
Phillip E. Mummah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US1985/001160 external-priority patent/WO1986000455A1/fr
Application filed by Individual filed Critical Individual
Publication of EP0227691A1 publication Critical patent/EP0227691A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/28—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using colour tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • This invention relates generally to multi-color display systems, and more particularly to devices and methods for increasing the number of simultaneously displayable shades of color in raster scanned digital color displays.
  • the method of simultaneously displayable improved color generation described herein is most directly applicable to computer generated color graphics, the concept can also be applied to other video display equipment.
  • Computer controlled color raster graphics systems can be classified into analog and digital graphics systems.
  • analog color graphics systems raster information stored in video memory is converted from digital to analog voltages using Digital-to-Analog Converters (DAC's) to drive analog color monitors.
  • DAC's Digital-to-Analog Converters
  • digital color graphics systems the raster information stored in video memory is digitally transmitted to a digital color monitor.
  • Analog systems use different levels of voltages on the analog monitor color guns to generate different shades of color on the monitor screen.
  • the analog input voltages to the analog monitors are typically between zero and seven-tenths of a volt. By varying the input voltage between 0 and 0.7 volts for each gun, different shades of color can -be obtained on the analog monitor screen. Hence, theoretically, an infinite number of colors can be obtained on an analog monitor.
  • digital color graphics systems only two levels of voltages are recognized, namely the low and high levels. Hence, if a digital color monitor has "m" color inpu.ts, then only 2 M color combinations are possible.
  • Digital color graphics systems do not suffer from color bleeding and voltage drifting.
  • Digital color monitors have digital video amplifiers that detect only two logical levels. Thus, they are easier to design and are cheaper. Digital switching circuits can generate signals with short rise and fall times, hence bleeding is significantly reduced. And consequently. sharper pictures can be obtained. Moreover, the lines transmitting digital video signals from a board to the monitor are less sensitive to noise because the two logic levels are wide apart.
  • digital color graphics systems have a limitations in color generation. This is because only sixteen colors can be generated in a four color control input digital monitor .
  • dithering Another method used to generate more colors is called dithering. This method involves using every adjacent pixel pair on the monitor screen to represent one dot on the picture. These pixels are then dithered by alternating their colors for every picture from (typically every l/60th of a second) . This continuous alternation for every picture frame causes a blending effect to produce a unique resultant color. However, this technique requires an additional level of hardware or firmware to take care of the alternations. Also, dithering produces a resultant loss of the picture resolution and a flickering of the image. The technique can be used to generate up to a maximum of 136 colors on a digital monitor.
  • W. Matzen discloses a color display system in which a CRT screen is also coated with phosphors having different detection beam energy activation levels for each color.
  • the accelerating high voltage of the tube is amplitude switched in accordance wi h the particular color signal which is intensity modulating the beam.
  • Urich in U.S. Patent No. 4,214,277 notes the "half tone" technique of representing a continuous tone image by the use of only black and white levels so that the eye perceives a grey image. He achieves this by digitally subdividing analog monitor picture elements into a matrix of black and white sub-elements .
  • Kurahashi , et al . in U.S. Patent No. 4,383,256 controls the excitation period of individual LED displays in accordance with image signal amplitudes in order to produce half tone images.
  • Bell, et al. in U.S. Patent No. 4,467,322, disclose a method of generating different shades of color for the background and the cursor on a digital color monitor.
  • the method consists of using a type of pulse width modulation to produce an intermediate shade for each of the three primary color guns of a digital color monitor. It uses a "hard-wired" technique including resistor-capacitor circuit for varying the partial width pulse. Since "hard-wired" circuits can only be manually changed, this metho _ limits itself to producing a maximum of 3 simultaneously displayable background and cursor color shades per gun on a digital color monitor. Temperature changes will alter the timing parameters of the circuit disclosed, causing changes in the shade of the intermediate color.
  • the method in general , is incapable of generating more than twenty-seven simultaneous colors on a Red, Green,
  • RGB Red (RGB) digital color monitor. It allows only manual control of the intermediate shade of each guns of a digital monitor and the shade of the intermediate color for each gun will have the same intensity.
  • Brown et al . in their U.S. Patent No. 3,725,578, disclose a "half tone process" for digital video receivers by using constant amplitude, variable duty cycle pulses.
  • the technique relates to duty cycle variation of a Nyquist period which is a function of the transmission signal bandwidth.
  • the technique also deals only with producing half-tones in monochromatic digital color displays.
  • Monochromatic displays do not have a grid inbetween the electron gun and the screen, and thus, a fixed dot period on the screen is not defined.
  • the patent does not deal with multiple color generation in digital color monitors and is strictly related to video receivers, as opposed to computer graphics display devices.
  • a large number of colors e.g., as many as 262,144 colors
  • Another objective of the present invention is to provide a new method of controlling the overall intensity of a color generated in raster scanned digital color display devices by means of parallel pulse width modulation of the intensity control line.
  • a further object of this invention is to provide apparatus for practicing this new method and which may be simply added to existing digital color graphics systems by means of replacement cards or piggy-back cards, or may be integrated on a chip or hybrid, or programmed on a programmable chip.
  • Still another object of this invention is to provide apparatus for practicing this new method which may be simply integrated into existing module structures for incorporation in newly built systems.
  • the time that each pixel on a screen is excited by individual primary color guns in a digital color monitor is independently varied so as to produce a variety of new color shades.
  • the intensity control line, if present on the monitor, is also controlled in a similar manner to vary the overall intensity of the color of a pixel on the screen.
  • the intensity of any primary color in a pixel is proportional to the energy imparted to the pixel by the sweeping electron beam.
  • This energy can be varied in a digital system by controlling the amount of time that the pixel is excited by the electron beam.
  • the resultant energy of all the three beams on a pixel can be inclusively varied by controlling the time that the intensity control input to a monitor is turned on in a pixel period.
  • the luminance of a pixel is dependent upon the ratio of the amount of time that the pixel is excited by the electron beam to the a ount of time that the pixel is not excited for given pixel period. If this ratio is varied by using parallel pulse width modulation, it is possible to select and simultaneously display a large number of colors on the screen. By reducing the time that a pixel is excited in a pixel period, a darker shade of color is perceived by the eye.
  • the parallel pulse widths can be generated so that they have successively widening pulse widths within a given pixel period. When so used, linear color shade control for each electron gun may be obtained in approximate accordance with the following relationship in which "i" is the resultant intensity luminance for each color on the screen.
  • the total energy imparted to a color pixel on the screen by the color guns is the sum of the energies imparted by all of the color guns on that pixel.
  • This energy shows up in the form of visible light and can be further varied by changing the ratio of the time that each pixel is displayed at full intensity to the time that it is displayed at reduced intensity. hence, if "n" different intensities can be obtained on the intensity line (the I line) of a digital color monitor, having "m" color input lines, then:
  • Apparatus to implement the above concept may be easily added to or integrated with existing controller circuitry.
  • additional coded color input data lines are required to select one of the several available pulse width modulation signals.. .
  • the parallel pulse width modulation signals can be generated by using either a high frequency clock which is a multiple of the dot clock and digital sequential/combination logic, or by using the dot clock with combinatorial logic, or by using the dot clock parallel pulse width modulated signals ("n" lines) are connected to mutiplexing circuits so as to select one of the "n" lines for each color and intensity line of the digital color monitor. These multiplexed signals will drive any digital color monitor to generate n ' colors.
  • the same technique can be applied to other digital display devices such as flat panel color displays, single gun color monitors and other color display devices.
  • Fig. 1 is a block diagram of a conventional arrangement of a digital color graphics systems (prior art) ;
  • Fig. 2 is a block diagram of another conventional arrangement of a digital 1 color graphics system with dual ported memory (prior ' art) ;
  • Fig. 3 presents tabular data of colors available with the conventional arrangement of Figs. 1 and 2;
  • Fig. 4 is a timing diagram showing the relative signal states for a particular color signal (prior art) ;
  • Fig. 5 is a partially broken isometric perspective view illustrating a conventional shadow mask CRT and showing in exploded detail the relationship between gun, mask and screen areas;
  • Fig. 6 is a pictorial isometric close up of a color electron beam traversing a single pixel in a conventional arrangement at full brightness;
  • Fig. 7 presents the beam signal state with time associated with Fig. 6;
  • Fig. 8 is a pictorial isometric close up of a
  • Fig. 9 presents the beam signal state with time associated with Fig. 8;
  • Fig. 10 is a block diagram of a first embodiment of a digital color graphics system in accordance with this invention.
  • Fig. 11 is a block diagram of a second emodiment of a digital color graphics system in accordance with this invention.
  • Fig. 12 is a detailed block diagram of an embodiment of the parallel pulse width modulation generation and multiplexing circuit associated with Figs. 10 and 11;
  • Fig. 13 is a circuit diagram of a possible implementation of the pulse width modulation circuit, using a high frequency crystal, in accordance with the concept of this invention
  • Fig. 14 is a timing diagram showing relative signal states when multiple color shades are produced in accordance with the concept of this invention.
  • Fig. 15 is a circuit diagram of another possible implementation of the pulse width modulation circuit, using digital delays, in accordance with the concept of this invention.
  • Fig. 16 is a circuit diagram of another possible implementation of the pulse width modulation circuit, using hybrid digital delay lines, in accordance with the concept of this invention.
  • Fig. 17 illustrates a possible organization of Video memory in any of the above embodiments.
  • Fig. 1 is a block diagram of a conventional arrangement for a digital color graphics systems which is presented for later comparison.
  • the Central Processing Unit 1, (CPU) under control of program memory 2 is shown in communication with a video controller 4.
  • the video controller 4 communicates with the video screen memory 3, which contains the information to be displayed on the screen of the digital color monitor 11.
  • the video controller also receives updated information from the CPU 1 for the video screen memory 3.
  • the video controller 4 issues serial color information on the Red, Green and Blue (RGB) lines of the monitor 11, and vertical and horizontal synchronization information on lines V and H respectively.
  • the dot clock generator 9 provides dot clock pulses of a particular frequency " to the video controller and clock pulses of a lesser frequency to the CPU 1.
  • the RGB lines convey serial information at the dot clock frequency to the monitor 11.
  • the frequency of the dot clock determines the number of pixels that can traversed as the beam makes a scan across the screen. During each cycle of the dot clock, a new color may be defined on the RGB lines.
  • RGB lines going to the monitor 11 are digital lines, only two sets of logical values of voltages can be transferred on each line. This limits the three RGB lines to transfer up to a
  • Fig. 2 is a block diagram of another conventional arrangement for a digital color graphics system.
  • Both CPU 21 and video controller 24 have shared access to dual ported video memory (aldo called reaster memory) 23, which is used for screen refresh updating. Shared control is implemented by the multiplexer 26 on the address lines.
  • the display controller 24 controls synchronization of both data output from raster memory 23 to buffer 27 and data output from synchronization circuit 30- (also called as the sync circuit) to the video display device 31. Reading out from video memory 23 is performed between initiation of sync pulses by the controller 24.
  • the address multiplexers 26 and the data buffers 27 are switched by the CPU signals.
  • Data output from the buffer 27b is converted from parallel to serial at the converter 28 and is shifted serially out at the rate of the dot clock frequency.
  • a new color is defined by the states of the four digital lines Red, Green, Blue, and Intensity (RGBI).
  • RGBBI Red, Green, Blue, and Intensity
  • Fig. 3 presents a tabulation of the total colors available on an RGB digital color monitor.
  • Fig. 4 illustrates a timing diagram showing relative signal states for an arbitary primary color in an RGBI digital monitor.
  • the time periods Tl through T5 are pixel periods.
  • the Red signal is arbitraily altered from low to high for both low and high states of the Intensity signal. Maximum luminance occurs at periods T2 and T4 with both the color and intensity bits at a logical one. With the Intensity line low and the Red signal high, as at T5, a lower brightness, or darker shade of Red color is obtained .
  • Fig. 5 is an isometric perspective view of a typical shadow mask cathode ray tube (CRT), with perspective a partial section of the mask and screen broken away and exploded for improved viewing.
  • Electron beams 43 are generated from each of three individual color guns 42 in the neck of the tube.
  • the shadow mask 44 a thin perforated metal electrode is placed close to the screen and aligned with it such that each hole 47 in the mask coincides with a triad of three phospor dots on the screen 45, one for each primary color dot 46.
  • Gun alignments are such that the electron beams 43 converge to a point 48 at the center of the shadow mask' aperture and then diverges so that each beam falls incident on the respective primary color dot.
  • Beam sweeping is accomplished by means of an external deflection yoke 49 consisting of conventional line and field scanning coils.
  • the electron beams are activated by the digital video amplifiers which receive signals from the digital color graphics circuit.
  • FIG. 6 A pictorial isometric close up of a pixel window 46 being swept by the electron beam 43 in accordance with the prior art methods is shown in Fig. 6.
  • the electron beam 43 is excited for the entire pixel period as shown at 51 in Fig. 7.
  • the dark cross hatched area 50 indicates maximum phospor excitation and luminance. It is assumed that the digital amplifier (not shown) driving the electron beam is operating at full bias voltage as a result of the Intensity line being high.
  • Fig. 8 shows a similar view of a beam sweep, but under the conditions of change in the beam intensity during the pixel period, as taught by this invention.
  • pulse width modulation is shown at 52.
  • the color signal is at a logical high for approximately one third of the pixel period (pixel window) and low for two thirds of the period.
  • the Intensity line signal is assumed to be high for this pixel period.
  • Fig. 10 shows a block diagram of one embodiment of a digital color graphics system arranged in accordance with the principles of this invention. General similarity of the system elements with those of Fig. 1 will be noted. Hardware changes to accomplish the improvements of the present invention are denoted by brackets [ ] .
  • An addition of a parallel pulse width modulation (PWM) generator selector circuit [10] is made, and the dot clock generator 9 of Fig. 1 is changed to generate a high frequency clock [109] in Fig. 10.
  • the parallel PWM generator selector circuit [110] receives data lines from a parallel to serial converter [108].
  • the converter [108] receives parallel color pixel information from the video screen memory 103 to be displayed on the screen.
  • the parallel PWM generator selector circuit [110] is driven by a high frequency clock in this configuration ) from the dot clock generator [109].
  • he circuit [110] also receives additional control information from the video controller 104.
  • the clock driving the circuit [110] is synchronized with the dot clock, and in this embodiment, is a "K" times multiple of the dot clock.
  • the multiple "K” is dependent on the number of shades of color required per gun. "For the particular emodiment' of parallel PWM circuit described, the number of shades of color per color line are (2K + 1) . . ⁇
  • Fig. 11 shows a block diagram of another emodiment of a digital color graphics systems in accordance with the principles of this invention.
  • General similarity of the system elements with those- of Fig. 2 will be noted' As before, ! hardware changes to accomplish the improvements are denoted by brackets [ ].
  • the changes made to the system of Fig. 2 are primarily in the sync circuit module 30.
  • the circuit module in Fig. 11 is changed to be the parallel' PWM generator, selector and sync circuit [210] .
  • This module [210] receives serial color information from the parallel to serial converter 208 or from a pale.tte selector memory. Palette selector memory is ' used sometimes in place of the parallel to serial converter 208 if not all colors generated are to be simultaneously displayed.
  • the module [210] receives blanking and video attributes information from the video controller 204.
  • the dot clock generator [209] generates the dot clock for the circuit modules 204 and 208. It also generates the high frequency clock for the novel circuit [209] of this invention.
  • the dot clock and the high frequency clock is "K" times the dot clock so as to produce (2K + 1) shades of color per digital color input line to the digital monitor.
  • Fig. 12 shows a block diagram of one implementation of control circuitry in accordance with the principles of this invention.
  • This circuit corresponds to the circuit module [110] of Fig. 10 and [210] of Fig. 11.
  • Fig. 12 consists of the PWM data latch 312, the parallel PWM signal generation circuit 314, the PWM signal selection circuits 316 through 322 for each color control selection circuits 316 through 322 for each color control input to the digital monitor, and the PWM signal line drivers (LD) , 324, 326, 228, 330.
  • the novel circuit also incorporates the video attributes signals such as "display enable", "cursor enable”, which are logically combined to form the "sync input” signal.
  • video attributes signals such as "display enable”, "cursor enable", which are logically combined to form the "sync input” signal.
  • the novel circuit also includes the high frequency clock circuit [309] which drives the parallel PWM generator circuit [310].
  • the dot clock instead of the high frequency clock to generate the parallel PWM signals.
  • the dot clock is generated from the circuit 314 instead of the dot clock generator [309].
  • the sync input is logically combined with the selected parallel PWM signals at the drivers LD.
  • the line driver outputs are connected to the inputs of the digital color monitor (not shown) , via RGBI lines 12.
  • the specific embodiment of Fig. 12 is shown for the four RGBI lines 12. However, the same circuit may be expanded and used with six input or other configuration digital color monitors.
  • the " code PWM data in the PWM latch 312 comes from the parallel to serial converters discussed earlier.
  • Fig. 13 is a detailed digital circuit diagram of a possible implementation of the parallel PWM circuit, using a high frequency clock.
  • a four times dot clock has been, chosen to be the high frequency clock.
  • the clock generator 430 generates a high frequency, digital clock signal which is split into the inverting and non-inverting clocks by the inventor 433. These two clocks drive a state machine 429 consisting of two 74AS164 shift registers 331 and 432, and " the NAND gate 334.
  • the state machine produces a parallel train of varying duty cycle pulses (the parallel PWM signals) , all having a repetition rate equal to one fourth the high frequency clock.
  • the repetition rate of the parallel PWM signals is equal to the dot clock repetition rate.
  • the six parallel PWM signals have duty cycles of 25%, 37.5%, 50%, 67.5%, 75% and 87.5% respectively.
  • These parallel pulses are fed to four 8-by-l multiplexers, 335 through 338.
  • the multiplexers function as the parallel PWM selectors.
  • the 0% and 100% duty cycle pulses are produced by connecting the respective multiplexer inputs 444 and 446 to logical low (GND) and high (Vcc) levels.
  • the pulse width of desired duty cycle is selected for each pixel period by the select lines 448 provided by the PWM latch (latch not shown) . These select lines address the four 8-by-l multiplexers.
  • the selected PWM signal from each multiplexer is then conditioned by the "sync" in-put line for cursor and display-enable conditions at the line drivers 439 through 442.
  • the outputs of these line drivers are the pulse width modulated RGBI signals 12.
  • These PWM RGBI lines 12 drive a digital color monitor to produce 8 shades per color control line or 4096 simultaneously displayable colors for this implementation.
  • the described circuit uses commercial 74AS Series parts. However, the circuit can be implemented by using any available circuit technology and parts.
  • the circuit could be implemented on a custom or semi-custom chip or chip-set. It could also be. implemented on a programmable chip or on a hybrid .
  • the circuit shown in Fig. 13 can produce many more colors with slight modifications. It can also be used to drive different digital color monitors with different digital color inputs and picture resolutions. As the picture resolution of the monitor gets higher, the high frequency clock frequency reaches very high limits. In order to avoid this, an alternate solution is discussed using the dot clock and digital delay lines in place of the high frequency clock and the shift registers.
  • Fig. 14 is a timing diagram in which, the relative signal states are given in comparison with Fig. 4.
  • the high frequency clock is assumed to be 2 times the dot clock for the implementation in Fig. 13.
  • the pixel excitation intensities will vary in steps of 25% increments. Five shades are possible per color line, thus generating a total 625 simultaneously displayable colors for an RGBI digital monitor.
  • Fig . 15 shows a detailed circuit diagram of an implementation of the parallel PWM circuit, using digital delay lines and the dot clock.
  • the dot clock 509 drives the digital delay device 544.
  • the digital delay device 544 has 3 equally spaced delay taps at the outputs D0, Dl and D2, and complementary delay taps at the outputs /D0, /Dl and D2.
  • These six outputs are logically combined with the dot clock at gates 545 through 549 to produce the required parallel PWM signals. These pulses have the same period as the dot clock and have varying duty cycles ' ith varying width pulses.
  • the PWM signals drive the digital color monitor to produce up to 4096 simultaneously displayable colors.
  • digital delay devices are available in hybrid forms so as to include a "p"-by-l multiplexer circuit and a digital delay element with "p" taps. Such digital delay devices can be conveniently used, one for each color control line, to implement the novel circuit taught by this invention.
  • Fig. 16 shows a detailed circuit diagram of an implementation of a parallel PWM circuit, using hybrid digital delay devices.
  • the hybrid digital delays 650 through 635 have four lines each for selecting one of sixteen possible delayed outputs at the output "delta D" .
  • the delay devices are connected to the dot clock at the CK -input.
  • the gates 662 through 669 and the 2-by-l multiplexers outputs "1Y". Depending on the value of the desired color, the digital delay devices for each video color control line will generate one-of-16 possible delayed clock outputs.
  • the delayed dot clock output is then gated out to generate the appropriate PWM signal at the Yl output of the multiplexers 654 through 657.
  • the gates 658 through 661 are used to provide the zero intensity signal (blank) to the outputs.
  • the select lines are up dated for every pixel on the video screen.
  • the PWM outputs from the multiplexers are gated with the "sync" input signal at 670 before, to drive the RGBI digital video lines.
  • the particular implementation shown in Fig. 16 can generate up to 1.048 million simul aneously displayable colors on a digital RGBI color monitor.
  • the circuit of Fig. 16 is only a specific implementation in accordance with the teachings of this invention It could be easily expanded to generate more colors on different digital monitors and used on monitors with different color input lines (eg. the six input color digital monitor) .
  • the example in Fig. 16 uses a 14 megaHertz dot clock for a monitor with a 640-by 200 screen resolution. However, the same technique could be used to generate more colors on a different resolution screen with a different dot clock.
  • Fig. 17 illustrates a possible organization of Video memory. It consists of the dioplayable memory 100 and the palette memory or palette register 101. The two memories are connected together such that the data from memory 100 addresses the palette memory 101. However, the CPU can communicate 101. However, the CPU can communicate (read/write) with either memory.
  • the displayable memory 100 is 'X' bits wide and can address 2 locations in palette memory 101 which is 'y' bits wide.
  • Y is grater that x.
  • the palette memory 101 outputs data corresponding to the color intensity of each primary color to be
  • video memory does not need to be configured as described above, allowing all colors to be displayed simultaneously.
  • Prior art shows that video memory can be divided into displayable memory and palette memory.
  • the displayable memory points to palette memory which has more bits per word than the displayable memory.
  • the palette memory then is used to select the desired colors.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Un procédé et un appareil sont utilisés pour générer des tons multiples de couleurs pouvant être affichés en même temps sur l'écran de dispositifs d'affichage numérique en couleurs à balayage du canevas, tels que des moniteurs en couleurs de type rouge-vert-bleu commandés par des ordinateurs numériques. En utilisant un système graphique numérique conventionnel en couleurs (Fig. 1), on réduit sélectivement le temps d'excitation de la substance luminescente d'un élément individuel d'image sur l'écran d'un moniteur (111) en couleurs de façon à rendre plus foncé le ton d'une couleur par rapport au ton obtenu par une période complète d'excitation de cet élément d'image. Une modulation parallèle de la durée d'impulsion (110) s'applique à chaque ligne de commande de la couleur et de commande de l'intensité pour obtenir, en "temps réel", cette excitation réduite. Deux modes de réalisation sont décrits, utilisant soit une horloge de haute fréquence (109) soit des lignes numériques d'affichage (Fig. 15). Dans le premier cas, pour une cadence de points multipliée par "K" et pour "C" lignes d'entrée d'un moniteur numérique en couleurs, (2K+1) (c+1) couleurs sont logiquement possibles et peuvent être affichées simultanément sur l'écran (211). Dans le deuxième mode de réalisation, pour "p" entrées à retard temporel uniforme des lignes numériques de retard, (p+2) (c+1) couleurs sont logiquement possibles et peuvent être affichées simultanément sur l'écran.
EP86901655A 1985-06-18 1986-02-18 Procede et appareil de generation d'images-ecran multicolores Withdrawn EP0227691A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
PCT/US1985/001160 WO1986000455A1 (fr) 1984-06-20 1985-06-18 Procede et dispositif de production d'affichages multicolores
JP1160/85 1985-06-18
US81164585A 1985-12-19 1985-12-19
US811645 1997-03-05

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EP0227691A1 true EP0227691A1 (fr) 1987-07-08

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JP (1) JPS63502054A (fr)
AU (1) AU5456386A (fr)
WO (1) WO1986007650A1 (fr)

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AU5456386A (en) 1987-01-13
JPS63502054A (ja) 1988-08-11
WO1986007650A1 (fr) 1986-12-31

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