EP0224639B1 - Procédé pour contrôler l'accès à la mémoire d'une carte à circuit intégré et dispositif mettant en oeuvre ledit procédé - Google Patents

Procédé pour contrôler l'accès à la mémoire d'une carte à circuit intégré et dispositif mettant en oeuvre ledit procédé Download PDF

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Publication number
EP0224639B1
EP0224639B1 EP86108602A EP86108602A EP0224639B1 EP 0224639 B1 EP0224639 B1 EP 0224639B1 EP 86108602 A EP86108602 A EP 86108602A EP 86108602 A EP86108602 A EP 86108602A EP 0224639 B1 EP0224639 B1 EP 0224639B1
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EP
European Patent Office
Prior art keywords
code
memory
data
area
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP86108602A
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German (de)
English (en)
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EP0224639A1 (fr
Inventor
Hartmut Dr. Phys. Schrenk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT86108602T priority Critical patent/ATE65632T1/de
Publication of EP0224639A1 publication Critical patent/EP0224639A1/fr
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Publication of EP0224639B1 publication Critical patent/EP0224639B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Definitions

  • the invention relates to a method for controlling memory access on a chip card and an arrangement for carrying out the method, as described in the preambles of claims 1 and 7.
  • the cards used in this case have a non-volatile electrical data memory as an essential element, which can be accessed via electrical node clocks on the card surface.
  • a computing unit accesses the memory content each time it is used, which is changed if necessary.
  • Cards of this type are used in security and access systems, in accounting or registration systems and in debit or credit systems.
  • In order to ensure the widespread use and frequent use of the cards there are operators of such systems which issue a large number of cards and which offer a wide-ranging network of reading devices and computing systems. To rule out misuse of the data, however, high Security requirements are placed on the card systems. Carrier cards in particular, the distribution of which cannot always be controlled, must be protected against unauthorized use.
  • the card is identified within a terminal using a card-related code which is stored on the card and in the terminal.
  • a card-related code which is stored on the card and in the terminal.
  • access is enabled or prevented. If a card-related secret code is stored in the same number in a large number of cards and terminals, there is a risk that this secret code will also become known to an unauthorized person, who could thus install even valid cards or terminals without authorization.
  • Protection by means of a card-related code therefore fails if the data becomes known, for example, through betrayal.
  • a safeguard against this, however, is to limit the validity period of circulating cards.
  • this restriction requires regular issuance of new cards and is therefore difficult and difficult to handle.
  • EP-A1-0 127 809 a monolithically integrable circuit arrangement is described, consisting of a memory with non-volatile, electrically writable and erasable memory cells, a control circuit for reading, writing and erasing partial areas of the memory and a control unit which via the control circuit makes access to a part of the memory addresses dependent on an input operation with a data comparison between stored reference data and code data input from outside, the control unit is designed so that it has a comparator unit for performing comparison operations between a plurality of code data and reference data, that the address space of the memory area containing the reference data is divided into a plurality of first subsets, each defined by a first selection logic, with several addresses each, and that the address lines defining the first subsets are connected to an address control unit, from which a first enable signal can be tapped if at least one address from each first subset has been selected in the course of the comparison operations.
  • the user inputs one or more individual code words via a data input unit to a computer system for transmission to the circuit arrangement.
  • a circuit arrangement can be built into a card which can be coupled to a data input unit.
  • the user enters one or more code words via a data input unit to a computer system for forwarding to the circuit arrangement.
  • the memory space of the non-volatile memory can be controlled via a line decoder and a block decoder.
  • the block decoder defines a first subset of addresses within the address space. The address lines corresponding to these first subsets are led to the address control unit via a first selection logic. The function of the selection logic can also be taken over by the block decoder.
  • the address lines leading from the row decoder to the memory are also connected to the address control unit via a further selection logic.
  • the address space of the memory can be subdivided into second partial areas which overlap the block subdivision via this second subset of the address lines.
  • the storage operation can be subdivided into a user data store and a code data store, which in turn are divided into blocks.
  • the code data area can be used to hold the reference data. Its memory content can therefore not be read out via the register.
  • there is access to the user data memory for example to write to or to delete, can only be carried out after a successful comparison operation, at the end of which the second enable signal must be generated.
  • the circuit arrangement is impressed with which first and second subsets of the address lines have to be selected during an enable operation. If at least one address has been selected for a data comparison in each of the first subsets of address lines in the course of a release operation, and / or if addressing is also carried out in a predetermined sequence, a first release signal can be tapped from the addressing control unit, which together with the output signal the error register is fed to a logic unit. Irrespective of this, an error register is set for each comparison that results in a deviation between the reference data word and the code word.
  • the linking unit If the access conditions to the address space of the memory have been met and if the comparison unit has determined that all code data and reference data match, the linking unit generates the release signal. This can be linked with control signals that cause reading, writing or deleting the user data area in an access protection.
  • the invention is based on the object of specifying a method and an arrangement of the type mentioned above, which prevent misuse with the card-related secret data used for identification or authentication protect and limit the validity period of the secret code without restricting the circulation of cards.
  • the invention is based on the fact that the card chip has logic and a control memory which enables a change in the card-related secret data used for identification or authentication in the chip, which are referred to below as the first code.
  • the first code For this purpose, several of these first codes are programmed in a main memory on the chip.
  • the activation of an address of the main memory in order to program a first code is protected by a second code. If this second secret code is activated, the relevant address of the main memory must be automatically blocked against reading and instead the action on a comparator logic must be released.
  • the second code is to be used as a system secret, neither on the card nor on a terminal nor by the cardholder, but only in a headquarters environment that is well protected against fraud.
  • first codes are pre-programmed as a precaution when the chip cards are issued, using the second code.
  • the other precautionary codes prepared as a precaution are not subject to fraud risk as long as they are not used in the terminal. If the validity period of a code has expired, the current first code can easily be replaced in the terminals. In practice, the number of these terminals is comparatively small. After changing over to a changed first code, it can also be used in all circulating chip cards and, when reused in any terminal, block an invalid first code simply by writing to the control memory or by deleting it. This reduces the risk that the owners of chip cards can be harmed by unauthorized manipulation of terminals via expired and therefore no longer secret first code words.
  • the figure shows a memory arrangement with a logic unit for securing access.
  • the arrangement of the figure has a memory arrangement 1, a row decoder 2, a comparator 4, a data register 3 and a logic unit 5.
  • the memory arrangement 1 is composed of a main memory 11 with a large number n of memory locations which can be addressed word by word, a control memory 13, the memory locations of which are assigned to the memory locations of the main memory 13 and can be addressed together via n address lines A, and a further independent area (second code area) 14) together.
  • the main memory 11 is divided into a user area 15 and a first code area 16 depending on the programming state of the control memory 13. In the example shown, this has memory locations with addresses A1, A2 to AK.
  • the addresses of the user memory 15 are A (K + 1) to An.
  • the data register 3 for input and output of data in the memory arrangement is for the word length of the main memory 11 and the second code area 14 and additionally for the width of the control memory 13 designed. With a word length of m bits for the main memory 11 and 2 bits for the control memory 13, it must therefore take up m + 2 bits. Between the data register 3 and the common input-output of the main memory 11 and the second code area 14 is the m-bit wide data comparator 4 for comparing a memory content with a register content.
  • the control logic 5 - in the example shown here - consists of two flip-flops 6 and AND and NOR gates. It generates an enable signal F1, which controls the write-read and erase access to the main memory 11. Another enable signal F2 controls the writing of a control bit B2 in the control memory 13.
  • first code which is already deactivated, is stored in the first memory location (address A1) of the first code area.
  • the second memory location contains a first code that is currently used for the user memory accesses.
  • further first codes are stored in the remaining memory locations (address AK), which are not yet needed during the current memory accesses, but which are available in the second memory location if the code is deactivated.
  • the number of such precautionary stored first codes depends on how often a code change can be expected.
  • the comparator signal K will be logic 1 after a comparison with the current first code stored under the address A2.
  • the control bits B1, B2 via a NOR gate 17 and, on the other hand, via the address lines A on a NOR gate 20 and then also via the NOR gate 17. If all of these conditions exist, the control signal T1 is also present to logic 1 and the enable flip-flop 6 is set via an AND gate 22.
  • the Q output of the enable flip-flop is linked to the output of the NOR gate via a NOR gate 18 and the enable signal F1 assumes a log.1 level.
  • the release signal F1 is not generated and access to the user memory 15 is not released.
  • control bit B1 assumes the log.0 state.
  • the deactivation can also be carried out directly by deleting (state log. 1) the control bit B2 in the control memory 13 together with the first code word which has become invalid. In this case, deletion must be possible without using the second code, while the deactivation of a code word by control bit B1 can also be made dependent on the application of the second code.
  • a control memory 13 written with a first code is only deleted together with the associated first code that has become invalid. This prevents unauthorized deactivation of preprogrammed first code words from making them readable.
  • the two enable flip-flops 6, 7 are reset when the arrangement is switched on via a reset signal POR.
  • the main memory 11 is either a user memory 15 or a first code area 16.
  • the control bit B2 1.
  • the control bit B2 0 by writing using the code in the second code area 14.
  • There are deactivated first codes, which are identified by the control bit B1 0, and which are only converted back to a user area by deletion (status log.1).

Claims (8)

  1. Procédé pour contrôler un accès en mémoire, au niveau d'une zone d'utilisateur et d'une première zone de code (15,16) d'une mémoire principale (11) d'une carte à puce, selon lequel une procédure interne d'autorisation avec une comparaison de données d'un premier code tiré de la première zone de code (16) et d'un mot de données est exécutée à partir d'un terminal,
    caractérisé par le fait
    que les adresses (A) de la mémoire principale (11) et d'une mémoire de contrôle (13) sont couplées entre elles de façon fixe,
    que plusieurs emplacements de la mémoire principale (11) sont marqués, en tant que premières zones de code (16), respectivement au moyen d'un bit de contrôle (B2) dans la mémoire de contrôle (13),
    qu'un premier code mémorisé dans l'emplacement associé de la première zone de code (16) est marqué comme activé ou désactivé respectivement au moyen d'un autre bit de contrôle (B1) dans la mémoire de contrôle (13),
    que, dans le cas d'une procédure d'autorisation, un signal d'autorisation (F1) est produit uniquement lorsqu'un emplacement de la mémoire est adressé avec un premier code activé et qu'il existe une coïncidence entre ce contenu de la mémoire et le mot de données introduit par le terminal, et
    que le premier signal d'autorisation (F1) n'est pas produit lorsqu'un mot de code désactivé est adressé et/ou lorsque le premier code considéré ne coïncide pas avec le mot de données.
  2. Procédé suivant la revendication 1, caractérisé par le fait qu'un second signal d'autorisation (F2) est produit uniquement lorsqu'un second code mémorisé dans une seconde zone de code (14) est adressé et qu'il existe une coïncidence entre le second code et un mot de données introduit de l'extérieur et qu'une programmation de la mémoire de contrôle (13) pour une conversion -au moins partielle- de la zone d'utilisateur (15) en une première zone de code (16) peut être exécutée uniquement après la production du second signal d'autorisation (F2).
  3. Procédé suivant la revendication 2, caractérisé par le fait que des premières données de code activées sont désactivées, bloquées ou effacées sans l'utilisation des secondes données de code.
  4. Procédé suivant l'une des revendications précédentes, caractérisé par le fait que, pour la désactivation de premières données de code, au moins un second bit (B) est inscrit dans la mémoire de contrôle (13).
  5. Procédé suivant l'une des revendications précédentes, caractérisé par le fait que des premières zones de mémoire, couplées du point de vue des adresses, dans la première zone de code (16) et dans la mémoire de contrôle (13), sont effacées simultanément.
  6. Procédé suivant l'une des revendications précédentes, caractérisé par le fait que pour réactiver un emplacement de mémoire de la première zone de code (16) en tant que zone d'utilisateur (15), les bits inscrits dans la mémoire de contrôle (13) sont effacés en commun avec les premières données de code devenues invalides.
  7. Dispositif pour la mise en oeuvre du procédé suivant la revendication 1, comportant une première zone de code (16) dans un dispositif à mémoire (1) comportant plusieurs emplacements de mémoire pour la réception de plusieurs premières données de code, et dans un dispositif (4) servant à comparer les premières données de code à un mot de données introduit de l'extérieur, caractérisé par une mémoire de contrôle (13), dont les emplacements de mémoire sont couplés, du point de vue des adresses, aux emplacements de mémoire de la première zone de code (16), et par une logique d'autorisation (5), sur le côté sortie de laquelle un signal d'autorisation (F1) peut être prélevé au moins uniquement lorsque, en raison du contenu de la mémoire de contrôle (13), les données de code contenues dans la zone de code associée (16) sont caractérisées comme étant "activées", et que la comparaison entre les premières données de code et un mot de données introduit de l'extérieur est couronnée de succès.
  8. dispositif suivant la revendication 7, caractérisé par une seconde zone de code (14), qui est indépendante, du point de vue de son adresse, des autres zones de mémoire et sert à recevoir des secondes données de code, et par une logique d'autorisation (5), sur le côté sortie de laquelle un autre signal d'autorisation (F2) peut être prélevé pour l'accès de programmation à la mémoire de contrôle (13), uniquement après une comparaison, exécutée avec un résultat positif, entre les secondes données de code et un mot de donnée introduit de l'extérieur.
EP86108602A 1985-07-08 1986-06-24 Procédé pour contrôler l'accès à la mémoire d'une carte à circuit intégré et dispositif mettant en oeuvre ledit procédé Expired - Lifetime EP0224639B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT86108602T ATE65632T1 (de) 1985-07-08 1986-06-24 Verfahren zum kontrollieren eines speicherzugriffs auf einer chipkarte und anordnung zur durchfuehrung des verfahrens.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3524371 1985-07-08
DE3524371 1985-07-08

Publications (2)

Publication Number Publication Date
EP0224639A1 EP0224639A1 (fr) 1987-06-10
EP0224639B1 true EP0224639B1 (fr) 1991-07-24

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ID=6275238

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Application Number Title Priority Date Filing Date
EP86108602A Expired - Lifetime EP0224639B1 (fr) 1985-07-08 1986-06-24 Procédé pour contrôler l'accès à la mémoire d'une carte à circuit intégré et dispositif mettant en oeuvre ledit procédé

Country Status (5)

Country Link
US (1) US4819204A (fr)
EP (1) EP0224639B1 (fr)
JP (1) JPS6210745A (fr)
AT (1) ATE65632T1 (fr)
DE (1) DE3680476D1 (fr)

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ES2051780T3 (es) * 1987-03-04 1994-07-01 Siemens Nixdorf Inf Syst Disposicion de circuito para asegurar el acceso a un sistema de proceso de datos con la ayuda de una tarjeta de chips.
EP0281059B1 (fr) * 1987-03-04 1993-12-01 Siemens Nixdorf Informationssysteme Aktiengesellschaft Système pour l'échange de données avec plusieurs terminaux d'utilisation comportant chacun un dispositif de lecture de cartes à circuit intégré
JPS63293664A (ja) * 1987-05-27 1988-11-30 Sharp Corp 電子機器
US5497462A (en) * 1988-07-20 1996-03-05 Siemens Aktiengesellschaft Method and circuit for protecting circuit configurations having an electrically programmable non-volatile memory
JPH0388052A (ja) * 1989-08-31 1991-04-12 Toshiba Corp 機密保護処理方式
KR940005696B1 (ko) * 1991-11-25 1994-06-22 현대전자산업 주식회사 보안성 있는 롬(rom)소자
DE4229863A1 (de) * 1992-09-07 1994-03-10 Nat Rejectors Gmbh Mobiler Datenträger und Datenaustauschvorrichtung dafür
US5753899A (en) * 1993-10-06 1998-05-19 Gomm; R. Greg Cash alternative transaction system
US5650761A (en) * 1993-10-06 1997-07-22 Gomm; R. Greg Cash alternative transaction system
NL9301880A (nl) * 1993-11-02 1995-06-01 Robert Eric Hertzberger Werkwijze en inrichting voor de opslag van gegevens in het bijzonder pincodes.
JPH07160592A (ja) * 1993-12-03 1995-06-23 Rohm Co Ltd 半導体メモリ装置
US5442704A (en) * 1994-01-14 1995-08-15 Bull Nh Information Systems Inc. Secure memory card with programmed controlled security access control
DE4435251A1 (de) * 1994-10-04 1996-04-11 Ibm Mehrstufige Zugriffssteuerung auf Datenträgerkarten
JP4678084B2 (ja) * 2000-09-29 2011-04-27 ソニー株式会社 メモリ装置およびメモリアクセス制限方法
US6732306B2 (en) * 2000-12-26 2004-05-04 Intel Corporation Special programming mode with hashing
US6834323B2 (en) 2000-12-26 2004-12-21 Intel Corporation Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US7007131B2 (en) * 2000-12-27 2006-02-28 Intel Corporation Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US6996721B2 (en) * 2001-03-27 2006-02-07 Micron Technology, Inc. Flash device security method utilizing a check register

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Also Published As

Publication number Publication date
DE3680476D1 (de) 1991-08-29
JPS6210745A (ja) 1987-01-19
EP0224639A1 (fr) 1987-06-10
ATE65632T1 (de) 1991-08-15
US4819204A (en) 1989-04-04

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