EP0217607A2 - Schwellwertregelschaltung für eine Videosignalschnittstelle und damit ausgerüstetes Aufzeichnungsgerät - Google Patents

Schwellwertregelschaltung für eine Videosignalschnittstelle und damit ausgerüstetes Aufzeichnungsgerät Download PDF

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Publication number
EP0217607A2
EP0217607A2 EP86307227A EP86307227A EP0217607A2 EP 0217607 A2 EP0217607 A2 EP 0217607A2 EP 86307227 A EP86307227 A EP 86307227A EP 86307227 A EP86307227 A EP 86307227A EP 0217607 A2 EP0217607 A2 EP 0217607A2
Authority
EP
European Patent Office
Prior art keywords
threshold value
voltage
signal
luminance signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86307227A
Other languages
English (en)
French (fr)
Other versions
EP0217607A3 (de
Inventor
Fumihiro Tanaka
Kenichi Matsushima
Yoshio Shimada
Kaneo Yamaguchi
Shinya Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of EP0217607A2 publication Critical patent/EP0217607A2/de
Publication of EP0217607A3 publication Critical patent/EP0217607A3/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits
    • H04N1/403—Discrimination between the two tones in the picture signal of a two-tone original

Definitions

  • This invention relates to threshold value setting circuits for video signal interfaces and in particular, although not so restricted, to recording apparatus for receiving video signals for displaying image data on display devices as input data and printing and recording an image.
  • the video signal level varies from model to model and variation exists even in the same model. Accordingly, adjustment by use of a measuring instrument is necessary whenever the apparatus is connected to a graphic terminal.
  • a threshold value suitable for the display image must be set.
  • the present invention seeks to provide a threshold value setting circuit for high frequency and various level video signals.
  • a threshold value setting circuit for a video signal interface characterised by comprising: a voltage comparator for receiving a luminance signal and converting said luminance signal to a logic signal; a discrimination circuit for discriminating the output of said voltage comparator, and a digital-analog conversion circuit which sets the threshold value of said voltage comparator to an arbitrary value, the arrangement being such that, in operation, the output of said voltage comparatorforthe set threshold value is discriminated, the setting of said reference voltage is sequentially changed in accordance with the result of discrimination, and a threshold value which is in agreement with a peak voltage of said luminance signal is determined in order to measure the signal voltage of said luminance signal.
  • the reference voltage is finely changed while watching the state of the discrimination circuit in order to find out a point at which the peak value of the luminance signal is in agreement with the reference voltage.
  • the set value of the reference voltage represents the voltage value of the luminance signal and when a predetermined ratio such as 0.5 is multiplied with this set data, an optimum threshold voltage can be set.
  • the video signal interface has a luminance signal input terminal 1 connected to a positive input of a voltage comparator 2.
  • the output of a digital-­10analog (D/A) converter 3 is connected to the negative input of the voltage comparator 2.
  • the output voltage of the D/A converter 3 can be set arbitrarily under control of a CPU circuit 5. If this D/A converter 3 has a resolution of 8 bits and a maximum output voltage of about 2.5V, the resolution is about 10mV and this covers the range of ordinary video signal voltages from 0.5 to 2.0V and can set the voltage sufficiently finely.
  • the output of the voltage comparator 2 is fed to a discrimination circuit 4 which discriminates the logic levels of the signal, and is written into an image data memory 7 through a data sampling circuit 6 where it is stored as print data.
  • the discrimination circuit 4 can comprise, for example, an R-S flip-flop circuit as shown in Figure 2.
  • the output of the voltage comparator 2 is connected to a SET input of the flip-flop while the reset signal from the CPU circuit 5 is applied to its RESET input.
  • the state of the output Q of this flip-flop can be read by the CPU circuit 5.
  • the threshold voltage can be made to correspond to the signal voltage.
  • setting of the least significant bit may be either "1” or "0", and the error due to this setting is sufficiently small so that there is no need to judge the result of setting.
  • the set value thus obtained can be handled as such as the voltage of the luminance signal.
  • a video signal is not an ideal pulse signal. It has a predetermined rise time and fall time and both are generally equal to each other. Accordingly, a signal having the same width as that of an ideal pulse can be taken out by setting the threshold value to the 50% level of the voltage of the luminance signal.
  • the threshold setting circuit described above is shown in Figure 5 incorporated in a recording apparatus 60.
  • a video signal 51 is sent to the recording apparatus 60 from a display device 50.
  • the recording apparatus has a front end circuit which provides a luminance signal 61 to a voltage comparator 64.
  • a logic signal 68 is fed from the voltage comparator to a data sampling circuit 62 and a threshold value setting circuit 65 which produces a threshold value 67 to the voltage comparator 64.
  • a sampling clock generation circuit 63 receives a sync signal from the front end circuit 61.
  • a sampling clock is fed to the data sampling circuit 62 to drive an image data memory 69 which, in turn, controls a printer block 71.
  • a CPU circuit 70 controls the threshold value setting circuit 65, the sampling clock generation circuit 63, the data sampling circuit 62, the image data memory 69 and the printer block 71.
  • the threshold value setting circuit according to the present invention and described above can easily set an optimum level for video signals of all levels and can set a threshold value of a predetermined level for the highest luminance level even for video signals representing multiple tone wedges. Therefore, reproducibility with respect to variance is high and the present invention can be connected to a plurality of terminals by use of a multiplexer.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Picture Signal Circuits (AREA)
  • Manipulation Of Pulses (AREA)
EP86307227A 1985-10-01 1986-09-19 Schwellwertregelschaltung für eine Videosignalschnittstelle und damit ausgerüstetes Aufzeichnungsgerät Withdrawn EP0217607A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP15023185U JPS6258963U (de) 1985-10-01 1985-10-01
JP150231/85U 1985-10-01

Publications (2)

Publication Number Publication Date
EP0217607A2 true EP0217607A2 (de) 1987-04-08
EP0217607A3 EP0217607A3 (de) 1988-09-21

Family

ID=15492413

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86307227A Withdrawn EP0217607A3 (de) 1985-10-01 1986-09-19 Schwellwertregelschaltung für eine Videosignalschnittstelle und damit ausgerüstetes Aufzeichnungsgerät

Country Status (2)

Country Link
EP (1) EP0217607A3 (de)
JP (1) JPS6258963U (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377282A (en) * 1991-09-19 1994-12-27 International Business Machines Corporation Optical inspection system utilizing dynamic analog-to-digital thresholding

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3999083A (en) * 1975-03-31 1976-12-21 The United States Of America As Represented By The Secretary Of The Navy Automatic threshold circuit
JPS56153883A (en) * 1980-04-28 1981-11-28 Ricoh Co Ltd Picture processing method
JPS57208770A (en) * 1981-06-19 1982-12-21 Hitachi Ltd Dc level automatic compensating circuit for analog signal repetitively including reference level signal
JPS5817778A (ja) * 1981-07-24 1983-02-02 Fuji Xerox Co Ltd ２値化方式
JPS59207785A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd 自動閾値設定回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377282A (en) * 1991-09-19 1994-12-27 International Business Machines Corporation Optical inspection system utilizing dynamic analog-to-digital thresholding

Also Published As

Publication number Publication date
JPS6258963U (de) 1987-04-11
EP0217607A3 (de) 1988-09-21

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Inventor name: WATANABE, SHINYA