EP0197762A2

EP0197762A2 - MOS capacitor and method of manufacturing the same

Info

Publication number: EP0197762A2
Application number: EP86302450A
Authority: EP
Inventors: Seiji Ueda
Original assignee: Matsushita Electronics Corp
Current assignee: Panasonic Holdings Corp
Priority date: 1985-04-03
Filing date: 1986-04-02
Publication date: 1986-10-15
Also published as: JPS61229349A; JP2604705B2; EP0197762A3; US4797719A; EP0197762B1; DE3679698D1

Abstract

@ A MOS capacitor of the structure of a trench-shaped capacitor is manufactured, first, by forming a first trench (19) in a semiconductor substrate (16) of one conductivity type, and the trench is filled with an insulator (21) to form an element isolation region (22). Second and third trenches (24, 24) are formed at positions respectively adjacent to both sides of the element isolation region (22) and opposing to each other sandwiching the element isolation region, and after a first polycrystalline silicon film (25) of an opposite conductivity type to that of the semiconductor substrate and an insulating film (27) are sequentially formed on the inner walls of the second and third trenches, the trenches (24, 24) are filled with a second polycrystalline silicon film (28). The trench-shaped capacitor uses the insulating film (27) as a dielectric layer and uses the first and second polcrystalline silicon films (25, 28) as electrodes.

In this capacitor, the width of the isolation region (22) can be reduced to about 111m and still the isolation dielectric strength can be improved.

Further, when the structure is applied to a DRAM, the memory cell can be made in a small size. Moreover, since an insulating film (27) of the capacitor is formed on a polycrystalline silicon film (25), the capacitor insulating film (27) is not affected by a defect caused in the silicon substrate (16) due to a work strain and the like, and as a result, a memory cell having high dielectric strength and an improved characteristic of a time (pause time) for the charges to disappear naturally due to leakage can be obtained.

Description

BACKGROUND OF THE INVENTION

Recently, MOS dynamic RAMs (hereinafter referred to as DRAMs) having a large storage capacity on the order of mega-bit have been realized. In keeping with such a trend, it has been designed to achieve higher density by reducing the size of a memory cell.
The present invention relates to a MOS capacitor and a manufacturing method thereof, and in particular, to a MOS capacitor suitable for increasing the density of a DRAM and a manufacturing method of such a MOS capacitor.
With the progress in study for increasing the degree of integration of the DRAM, a DRAM of a large capacity as large as several mega-bits has come to be reported. However, since the size of a chip generally increases as the storage capacity is increased, in order to achieve practical use, it is necessary to increase the density by further reducing the size of the memory cell.
An area of the memory cell per 1 bit is in a range from 50 to 70 µm² for a DRAM of 256 kb, and the area must be reduced to a range from 20 to 30 pm ²or less for 1 Mb. However, taking a soft error and noise margin into consideration, it is necessary that a capacitor capacity constituting the memory cell is made substantially comparable to the DRAM of 256 kb.
In order to maintain the capacity of the capacitor of the memory cell comparable to that of the DRAM of 256 kb while reducing the memory cell area, there is a method in which the effective film thickness of an insulating film (hereinafter referred to as a capacitor insulating film) which is a constituent element of the capacitor is reduced, or another method in which the effective area of the capacitor insulating film is increased.
However, in the former method, since it is difficult to make a silicon dioxide film thiner than about 10 - 15 pm in view of pinholes and the like, there exists a limitation.
On the other hand, a trench-shaped capacitor is known in which, in order to eliminate the drawbacks mentioned above, a trench of several ^pm in depth is formed in the semiconductor substrate, and by forming a capacitor on the inner wall of the trench, the effective area of the capacitor is increased (e.g., Kiyoo Itoh et al, "256 k/1 Mb DRAMS-II", 1984, ISSCC, pages 282 - 288).
The trench-shaped capacitor of this structure is a kind of the MOS capacitor structure in which an element isolation region is formed in the silicon substrate by a selective oxidation method, trenches are formed adjacent to the element isolation region and sandwiching this region, insulating films are respectively formed on inner walls of these trenches, and the trenches are filled up by forming polycrystalline silicon films on the insulating films so that the insulating films constitute dielectric layers and the silicon substrate and the polycrystalline . silicon films are used as electrodes.
In the trench-shaped capacitor mentioned above, it is designed to reduce the area of the memory cell by forming the trenches in the silicon substrate and forming the capacitor on the inner walls. However, when the trench-shaped capacitors are formed adjacent to both sides of the element isolation region formed by the selective oxidation method, punch through will be caused between the adjacent capacitors, and reducing the isolation width will become difficult. Moreover, since the selective oxidation method is employed in the element isolation, there arises a problem in that the generation of a bird's beak can not be avoided and higher integration can not be achieved.
Furthermore, a crystal defect or the like occured in the silicon substrate during the trench forming process and the heat treatment process will cause a leakage in the substrate and a defect in the capacitor insulating film. These problems pose a large obstacle in manufacturing a large capacity memory.

SUMMARY OF THE INVENTION

A first object of the present invention is to provide a MOS capacitor and a manufacturing method in which an element isolation region of high isolation dielectric strength is formed.
A second object of the present invention is to form an element isolation region which has a reduced isolation width and which is suitable for being made in a microstructure.
A third object of the present invention is to form an insulating film for a MOS capacitor which is not influenced by a crystal defect occured in the substrate.
A fourth object of the present invention is to form a MOS capacitor having a large capacity while being formed in a microstructure.
In the present invention, a capacitor is manufactured through a step of forming a first trench in the main surface of a semiconductor substrate of one conductivity type, after covering an inner wall of the trench with a first insulating film, filling the inside of the first trench with an insulator or a semiconductor material, and forming an element isolation region having the substrate surface flattened; a step of forming at least two trenches of second and third trenches adjacent to both sides of the element isolation region and opposing to each other sandwiching the element isolation region; a step of forming a first polycrystaline silicon film of an opposite conductivity type to that of the semiconductor substrate on the whole of the inner walls of the second and third trenches; a step of forming a second insulating film on the first polycrystalline silicon film; and a step of forming a second conductive polycrystalline silicon film on the second insulating film to fill the second and third trenches, wherein the second insulating film constitutes a dielectric layer and the first and second polycrystalline silicon films serve as electrodes.
According to the structure realized by the method mentioned above, a MOS capacitor is obtained in which a first set of a first polycrystalline silicon film constituting one electrode, a first insulating film constituting a dielectric layer, and a second polycrystalline silicon film constituting the other electrode are formed side by side, and are embedded in a first portion of the semiconductor substrate in substantially perpendicular directions to the main surface of the semiconductor substrate, and at least a second set of a similar composition to that of the first set is embedded in a second portion of the semiconductor substrate, and an isolation region including an insulator or a semiconductor material, and a first insulating film surrounding the insulator or the semiconductor material is embedded between the first and second portions.
In the MOS capacitor and the manufacturing method thereof in the present invention, the element isolation region can be formed to provide high isolation dielectric strength and in a trench shape having a reduced width. Furthermore, since _'a polycrystalline silicon film is formed on the inner wall of the trench-shaped capacitor, and an insulating film of the capacitor is formed on the polycrystalline silicon film, the capacitor insulating film can be formed in a region which is not influenced by a crystal defect occured in the substrate.
While the novel features of the invention are set forth with particularity in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. 1 to 10 are sectional views illustrating in the order of processes in a manufacturing method of a DRAM applied with a manufacturing method of a MOS capacitor in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of a manufacturing method of a DRAM applied in order to obtain a structure of a MOS capacitor in accordance with the present invention will be described with reference to a flow chart of a process.
First, as shown in Fig. 1, a silicon dioxide film 17 is formed on a surface of a P-type silicon substrate 16, and an opening 18 having a width of 1 pm is formed in a portion intended to be an element isolation region by a photoetching technique.
Next, as shown in Fig. 2, a trench 19 having a depth of 5 µm and a width of 1 µm is formed in the silicon substrate 16 by reactive ion etching using CC1₄ and 0₂ and by using the silicon dioxide film 17 as a mask. Following this, a channel stopper region 20 is formed on the bottom of the trench 19 by ion implanation of boron.
Next, as shown in Fig. 3, after oxidizing thermally the inner wall of the trench 19 and the surface of the silicon substrate 16, a silicon dioxide 21 is deposited by a CVD technique to fill the trench 19 with the silicon dioxide 21, and an element isolation region 22 is formed.
In this respect, as a technique for filling the trench 19, another technique may be used in which after the silicon dioxide is formed on the inner wall of the trench 19, a polycrystalline silicon layer is formed by the CVD technique thereby to fill the trench 19 with this polycrystalline silicon layer. Following this, as shown in Fig. 4, the silicon dioxide films 17 and 21 formed on the main surface of the substrate 16 are removed entirely by etching.
Next, as shown in Fig. 5, a new silicon dioxide film 23 is formed on the surface of the silicon substrate 16, and further, by the photoetching technique, openings for forming trench-shaped capacitors are formed at areas located at both sides of the element isolation region 22 and adjoining this region 22. Following this, the reactive ion etching is applied to silicon substrate portions exposed at the inside of these openings, and treches 24 and 24 each having a depth of 4 µm and a width of 1 µm are formed in the silicon substrate 16. These trenches 24 and 24 each having a U- or V-shaped cross section are located at both sides of the element isolation region 22 and are of a construction adjoining the element isolation region 22.
Next, as shown in Fig. 6, an N-conductivity type polycrystalline silicon film 25 containing phosphorous (P) is grown to a film thickness of about 200 nm on the inner walls of the trenches 24 and 24, and then N- type diffusion layers 26 and 26 are formed by diffusing the phosphorous contained in the polycrystalline silicon film 25 to the silicon substrate 16, and the silicon substrate 16 and the polycrystalline silicon film 25 are electrically connected.
Next, after coating a resist (not shown) all over the polycrystalline silicon film 25 to fill the trenches 24 and 24 with the resist, the resist film on the surface is removed by reactive ion etching using an oxygen gas, and leaves the resist only in the inside of the trenches 24 and 24. In this condition, the polycrystalline silicon film 25 and the silicon dioxide film 23 on the surface are sequentially removed. Thereafter, the resist in the inside of the trenches 24 and 24 are removed, and the resulting condition is shown in Fig. 7.
Next, as shown in Fig. 8, a silicon dioxide film 27 is formed so that an effective oxide film thickness becomes 15 nm as a capacitor insulating film. On this silicon dioxide film 27, a polycrystalline silicon film 28 containing phosphorous and intended to constitute the other electrode of a capacitor is formed to a thickness of 500 nm, and the surface is flattened by filling the trenches each having a width of 1 um.
Next, as shown in Fig. 9, the polycrystalline silicon film 28 on the surface is selectively removed, and an electrode pattern for the capacitor is formed. Following this, a gate oxide film 29 of an access MOS transistor is formed, and further, a layer insulating film 30 for insulating the capacitor electrode from a word line is formed. Then, after a gate electrode 31 made of tungsten or aluminum and the word line connected to the gate electrode 31 are formed, N- type diffusion regions 33 and 34 intented to serve as a source and a drain region are formed.
Next, as shown in Fig. 10, a layer insulating film 35 for insulating the word line 32 from a bit line is formed, and hereafter, an opening for forming an electrode is formed in the N-type diffusion region 33, and an aluminum wiring is selectively formed so that one end of the bit line 36 is connected to this opening.
Lastly, a memory cell of a DRAM is completed by forming a protective coat (not shown).
In this respect, the N-type diffusion layer 26 formed on the substrate side of the inner wall of each trench 24 shown in the embodiment may be omitted, and in this case, although the capacitor capacity decreases by about 10%, the effect of reduction of the memory cell area is not changed.
The memory cell of the DRAM formed by the MOS capacitor and the manufacturing method thereof in accordance with the present invention provides a capacity of 60 fF although the element isolation width and the trench width of the capacitor are reduced to 1 µm.
Moreover, even when the element isolation trench width is made 1 um, a substrate resistivity is about 4 - 5 n cm, and the dielectric strength between elements of 20 V can also be obtained.
Further, when this manufacturing method is used for a DRAM, since an insulating film is formed on a polycrystalline silicon film after the polycrystalline silicon film is formed on the inner wall of a trench for forming a capacitor, the capacitor insulating film for the DRAM is not influenced by a defect occured in the silicon substrate due to work strain or the like. Thus, a DRAM having high dielectric strength, and still having an improved characteristic of a time (pause time) for the charges stored in the capacitor naturally disappear due to leakage can be obtained.
While specific embodiments of the invention have been illustrated and described herein, it is realized that modifications and changes will occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes as fall within the true spirit and scope of the invention.

Claims

1. A MOS capacitor comprising:

a semiconductor substrate (16);

a first set of a first polycrystalline silicon film (25) serving as one electrode, a first insulating film (27) constituting a dielectric layer, and a second polycrystalline silicon film (28) serving as the other electrode embedded in a first portion of said semiconductor substrate (16) so that said first polycrystalline silicon film (25), said first insulating film (27), and said second polycrystalline silicon film (28) are arranged side by side in substantially perpendicular directions to a main surface of said semiconductor substrate;

a second set of a third polycrystalline silicon film (25) serving as one electrode, a second insulating film (27) constituting a dielectric layer, and a fourth polycrystalline silicon film (28) serving as the other electrode embedded in a second portion of said semiconductor substrate (16) so that said third polycrystalline silicon film (25), said third insulating film (27), and said fourth polycrystalline silicon film (28) being arranged side by side in substantially perpendicular directions to the main surface of said semiconductor substrate; and

an isolation region (22) embedded in said semiconductor substrate (16) between said first set and said second set, said isolation region including one of an insulator (21) and a semiconductor material, and a fourth insulating film (27) covering arround said one of the insulator and the semiconductor material.

2. A MOS capacitor according to claim 1, wherein each of said first polycrystalline silicon film (25), said first insulating film (27), said third polycrystalline silicon film (25), and said second insulating film (27) has a U- or V-shaped cross section.

3. A MOS capacitor according to claim 1, wherein each of said second polycrystalline silicon film (28) and said fourth polycrystalline silicon film (28) is a column shape.

4. A MOS capacitor according to claim 1 or 2, wherein each of said first polycrystalline silicon film

(25) and said third polycrystalline silicon film (25) is of an opposite conductivity type to that of said semiconductor substrate (16).

5. A MOS capacitor according to claim 1, 2, or 4, wherein a diffusion region (26) is formed in said semiconductor substrate (16) adjoining each of said first polycrystalline silicon film (25) and said third polycrystalline silicon film (25).

6. A manufacturing method of a MOS capacitor comprising the steps of:

forming a first trench (24) in a main surface of a semiconductor substrate (16) of one conductivity type, and after covering an inner wall of said first trench with a first insulating film, filling the inside of said first trench (24) with one of an insulator (21) and a semiconductor material thereby to form an element isolation region (22) with the substrate surface flattened;

forming at least two trenches of second and third trenches (24, 24) so that said second and third trenches respectively adjoin both sides of said element isolation region (22) and oppose to each other sandwiching said element isolation region (22) therebetween;

forming a first polycrystalline silicon film (25) of an opposite conductivity type to that of said semiconductor substrate (16) on the whole of inner walls of said second and third trenches (24, 24);

forming a second insulating film (27.) on said first polycrystalline silicon film (25); and

forming a second polycrystalline silicon film (28) respectively on said second insulating film (27) to fill said second and third trenches (24, 2.4),

thereby to form a capacitor having a dielectric layer constituted by said second insulating film (27) and having electrodes constituted by first polycrystalline silicon film (25) and said second polycrystalline silicon film (28).

7. A manufacturing method according to claim 6, wherein diffusion regions (26, 26) of an opposite conductivity type to that of said semiconductor substrate are resectively formed in said semiconductor substrate (16) at the inner sides of said second and third trenches (24, 24).