JPS6038855A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent leakage currents between recessed type capacitors (between memory cells) by inserting insulating films among the capacitors and a semiconductor substrate or isolating the cells by a groove deeper than the recessed type capacitors. CONSTITUTION:Field SiO2 7 is formed, the films of Si3N4 15 and PSG (phosphorus glass) 16 are applied, and a photo-resist pattern 17 to which sections forming the recessed sections of capacitors are bored is shaped. The PSG16, the Si3N4 15, the field SiO27 and pad SiO214 and an Si substrate 4 are etched. Si3N418 is etched selectively in a directional manner by using reactive sputtering etching by CH2F2 gas, Si3N419 adhering on side walls is left, and recessed sections 20 are formed to the Si substrate 4 through reactive sputtering etching by a mixed gas of CCl and O2. The Si3N415, 19 on the side walls and the surfaces are removed by a phosphoric acid solution, and polycrystalline silicon 22 is applied so that the recessed sections are not buried completely. An insulating film 25 (such as SiO2, Si3N4 or its multilayer film) and poly Si 26 are applied, thus forming MOS type capacitors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a concave capacitor and a method for manufacturing the same.

[Background of the invention]

In recent years, in a one-transistor type memory cell consisting of one capacitor and one effective transistor, as shown in FIG. A design with a total area increase was proposed. (Japanese Unexamined Patent Publication No. 51-130178) In FIG. 1, one memory cell is indicated by a broken line a in FIG.

FIG. 2 is a cross section taken along the line AA in FIG. 1. (In Figure 1, the wiring patterns for word Iw9 and bit line 12 are omitted.) With such a concave capacitor memory cell, the capacitor area can be significantly reduced compared to that of a conventional planar capacitor. When attempting to construct a large-scale memory by arranging these cells at high density, the following problem arises. Well, if concave capacitors are placed close together, arrow 13
A phenomenon occurs in which leakage current between capacitors as shown in Figure 2 is not easy to flow, and memory operation becomes unstable. Since impurity diffusion for V channel cutting is normally performed directly in the field 5iOz7 separating the confections, leakage current tends to flow near the arrow 13 where a potential saddle is formed. Furthermore, a similar leakage current occurs not only between the capacitors (between sources) but also between the capacitor and the contact portion 3 of the adjacent cell (between the source and drain). An object of the present invention is to provide a semiconductor device that prevents leakage current (between memory cells) and a method for manufacturing the same.

[Summary of the invention]

The present invention, which prevents leakage current caused by a concave capacitor, involves inserting an insulating film between the concave capacitor and the semiconductor substrate, or separating cells with deep grooves beyond the concave capacitor. The leakage flow path is defined by ~r
It is something to be cut into pieces.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a process diagram showing an embodiment of the present invention.

First, as shown in FIG. 3(1), after the entire field 5i027 is formed by the well-known LOCO8 method, 3i3
A film of N415 and PSG (phosphorus glass) 16 was deposited, and a photoresist pattern 17 was formed with openings in the areas where the concave portions of the capacitors were to be formed. The opening is field 5iQ
27 end.

Next, PSG16°5iaN4 was formed using a reactive sputter etching method using CF4 mixed with about 50% H2 gold.
15. Field SiO□7 and Bad 8jCh14
and etched the Si substrate 4. At this time, the etching rate ratio of each material is Si3N4:5iOz:5i=2:2
Etching conditions were selected so that the etching value was about 1:1, and the etching was terminated when the etching of field 5i027 was completed. Next, remove the photoresist) 17 and 5j3N
418 was applied.

(Figure 3 (2)) Using reactive sputter etching with CH2F2 gas, 513N418 is selectively etched in the direction to form lI+l.
1 Leave the plate-layered 5j3N419 on the wall, then CCt
Si is etched by reactive sputter etching using a mixed gas of 4 and 02.
A recess 20 was formed in the substrate 4. (FIG. 3(3)) The etching method used at this time may be any method other than those described above as long as it can directionally and selectively etch the Si, N418, and Si substrates 4, respectively.

Note that PS016 was created to protect S'5N415 and can be omitted.

Next, PSG16 was removed with a hydrofluoric acid solution, and S
After oxidizing the i-plane, the side walls and top surface were 8'3N415.
19 was removed with a phosphoric acid solution, and polyB i (polycrystalline silicon) 22 was deposited so that the four parts were not buried in the tip metal. (Figure 3 (4)) Here, 5i (Jz2
It is desirable that an impurity diffusion layer of the same conductivity type as the substrate 4 be formed under the substrate 1 by ion implantation in order to prevent the formation of a channel.

Poly Si 22 was etched into Poly 3 i 22 by reactive sputter etching of i, CC4 scum, which had a lower resistance by diffusing impurities of a conductivity type different from that of the substrate 4. By doing this, poJyS on the side wall of the recess
Only i23 remains, and this polySi is connected to the substrate 4 at the recess side wall 24 on the side where the field 5iOz7 is not present.

Next, an insulating film 25 (for example, bio□, Si3N4, or a multilayer film thereof) and PolyS i 26 are coated in 4.
Then, a gold MO8 type capacitor as shown in FIG. 3 f67 was formed.

The capacitor formed in the above manner is shown in Fig. 3 (
6), 5i0221 on the boundary with substrate 4
is inserted, making it extremely difficult for leakage current to flow between the p1 capacitors.

FIG. 4 is a plan view of the above manufacturing process. Field S! A pattern 31 forming a concave portion in the tL7 island-like region 30 surrounded by 02 is arranged as shown in FIG. 4(1). Since the four patterns 31 only need to overlap the island-like regions 30 even slightly, there is a large margin for alignment of the patterns in phosphorography. Also, Figure 4 (2)
As shown in , the formed capacitor part 1 has a weight of 510g2
1 surround the periphery and bottom t-ray-c, t,-, 6, arrow 32
．． It is clear that the leak 'tM, t& between the capacitors indicated by 33 and the leak current between the capacitor and the pit line contact section indicated by the notch J34 are unlikely to occur. In addition,
The 5io221 surrounding the capacitor may be connected between adjacent cells.

FIG. 5 shows an example in which a field is formed with thick 5i0235 by an element isolation method in which a groove formed in a Si substrate is filled with an insulating material. In such a case, the connecting portion 24 between the capacitor electrode 23 and the substrate 4 can be made larger.

FIG. 6 shows a case where the separation sieve is made deeper. When the insulating material 36 is formed deeper than the recess of the capacitor in this way, the recess 2 is arranged as shown in FIG. It may be used as one electrode of the capacitor. (FIG. 6 is a cross section taken along line H-B in FIG. 7.) In such a case, the alignment margin between the patterns of the island-like regions 30 and the recessed portions 2 will be small; If the cross-sectional shape of the concave portion 2 is made to be V-shaped, even if the pattern of the concave portion 2 is located at the end of the island region 30, the capacitor area will not be suddenly reduced.

〔Effect of the invention〕

As described above, according to the invention, since an insulating film is formed around the concave capacitor, it is possible to eliminate leakage currents occurring between adjacent capacitors. therefore,
Memory cells containing concave capacitors can be placed in close proximity to form large scale performance circuits.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a conventional memory cell, FIG. 2 is a sectional view taken along line AA in FIG. 1, FIGS. 3 and 4 are process diagrams showing an embodiment of the present invention, and FIGS. The figure is a sectional view showing another embodiment of the present invention, and FIG. 7 is a plan view of FIG. 6. l...Capacitor part, 2.20...Recessed part, 3...
Contact part, 4... Si substrate, 5.25... Insulating film for capacitor, 6, 22, 23.26... 1) ol
ysss, 7. 35.36...Field sho, 9...Word line, 12...Bit line, 13...Leak current path,
15゜18.19...5isN4.21...510
2.30...Island 1st figure Z z figure<+) 17 (?2 B (3) 3rd [2] (4) 2 (5) (Otsushiro 4th figure (υ (Z) Myo 5 No 2 Figure 7 F3 B

Claims (1)

[Claims] 1. In a semiconductor device VC having a concave capacitor,
A semiconductor device characterized in that the convex capacitor is formed on an insulating film, and one electrode of the concave capacitor is connected to a semiconductor substrate. 2. In a semiconductor memory having a memory cell having a concave capacitor as a storage capacitor, the memory cell is separated from the concave capacitor by an insulator formed deeply. Semiconductor equipment. 3. Forming a semi-circular substrate Vc recess so as to span the end of the island region separated by an insulating film, covering the inner surface of the recess with an insulating film, and forming a capacitor on the insulating film. A step of forming a film for a lower electrode and electrically connecting it to the semiconductor substrate in the island-like region, and a step of forming a capacitor insulating film and an upper electrode film on the lower electrode film to form a capacitor. A method for manufacturing a semiconductor device, characterized in that: