JPS61208256A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the increase of the quantity of charges stored in capacitor sections and the generation of interference leakage between the capacitor sections by forming a groove for isolating elements to the surface of a substrate between the groove-type capacitor sections. CONSTITUTION:A groove 21 deeper than the depth of grooves 15, 15 for capaci tors is formed to the surface of a substrate 1 between the grooves 15, 15 for capacitors, and an element isolation region 22 consisting of an SiO2 film is shaped into the groove 21. According to such a constitution, leakage currents between the capacitor sections is removed, and a DRAM having the large quan tity of charges stored can be acquired.

Description

[Detailed description of the invention] Technical field of invention C] related to process memory (DRAM).

[Technical background of the invention and its problems]

In recent years, as semiconductor integrated circuits have become more highly integrated, various attempts have been made to reduce the dimensions of elements.

Conventionally, the one shown in FIG. 2, for example, is known as a DRAM.

1 in the figure is a P-type silicon substrate. This board 1
On the top, there is a capacitor section 2 and a MOS transistor 3.
is formed. The carrier section 2 includes a substrate 1, an insulating film 4 on this substrate l, and a carrier on this insulating film 4.
It is composed of close electrodes 5. On the other hand, the [08 type transistor 3 is composed of an N+ type source and drain region 6.7, and an r-to electrode 9 provided on the substrate 1 with an e-to insulating film 8 interposed therebetween.

In a DRAM having such a structure, it is conceivable to reduce the area of the capacitor/transfer electrode 5 in order to increase the degree of integration. However, in this case, there is a drawback that the amount of charge accumulated in the canopy motherboard portion 2 decreases, and the margin against noise and the like decreases.

Therefore, it is recommended to reduce the thickness of the insulating film 4 to increase the amount of charge stored in the capacitor/4' capacitor part, or to use Si or N4, which has a high dielectric constant, instead of StO as the material for the insulating film 4. A method is being used to increase the amount of accumulated charge. However, all of these methods have problems in terms of withstand voltage and film quality (occurrence of pinholes, etc.) of the insulating film, and there are limits to reducing the area of the canopy electrode 5.

On the other hand, as a DRAM in which the amount of stored charge is increased without increasing the chip area, the one shown in FIG. 3 is known. Zl in the figure is an element isolation region. A trench I2 is provided on the substrate surface on both sides of this element isolation region 11, and an insulating film I3 is provided on the trench I2 and the substrate surface. A canoscillator electrode I4 made of polycrystalline silicon is formed on the element isolation region 11 and the insulating film 13 so as to fill the trench 12. Incidentally, a trench type capacitor portion I5.15 is formed by the substrate 11, insulating film 13, and capacitor electrode Z4.

However, according to the DRAM shown in FIG. 3, by appropriately changing the depth and shape of the groove 13, the effective area of the capacitor part can be arbitrarily selected, and the withstand voltage and film thickness of the insulating film I3 are also good. Can be done.

However, according to this DRAM, as the density of the capacitor portions I5 increases, interference leakage current occurs between adjacent capacitor portions 15. This is because the inversion layer in the adjacent carrier region I5 becomes dominant, and the element isolation region I5 becomes dominant.
This is caused by a leakage current flowing directly under the substrate I and a chip-through current flowing within the substrate I. Note that the punch-through current largely depends on the distance (L) between the grooves and the impurity concentration of the substrate I. For example, when the specific resistance of the substrate I is 100-α, L
is required to be about 3 μm, which hinders high density.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can increase the amount of charge stored in the carrier and capacitor sections, and can prevent interference leakage between the capacitor and capacitor sections. do.

[Summary of the invention]

The present invention provides a groove having a depth equal to or greater than the groove for the groove type capacitor/4' cap portion on the surface of the semiconductor substrate between the groove type capacitor portion and the arm portion, and further provides an element isolation region in this groove. The main point is to be able to prevent an increase in the amount of accumulated charge in the capacitor/mother part and the occurrence of interference leakage.

[Embodiments of the invention]

DRAMs according to embodiments of the present invention will be described below with reference to FIGS. 1, 4, and 5. Incidentally, the same members as those in the prior art are given the same reference numerals and the description thereof will be omitted.

Embodiment 1 In FIG. 1, 21 is a deep groove provided on the surface of the substrate 1 between the 4-side portions I5 and 15. This groove 2I is
Kiya A? It is formed deeper than the groove I2 for the bottom portion.

In the trench 21, an element isolation region 22 made of, for example, a StO film is provided.

For example, the rear and rear portions of the DRAM shown in FIG.
After forming a 1C deep groove 2I, this groove 21 is filled with S10. membrane t
After filling and further forming a shallow groove 12 in the substrate 1, the surface of the substrate I is oxidized to form an insulating film, and then polycrystalline silicon is deposited and turned.

According to the DRAM of Example 1, the carrier 972
Part 15. ．． 15. Since the structure has a structure in which a groove 21 deeper than the groove 12 is provided on the surface of the substrate 1 between the substrates 1 and 2, and an element isolation region 22 is provided within the groove 2/-, the carrier/base portion 15. ．． 1
5. It is possible to prevent the occurrence of interference leakage current between the two. In addition, the cano 4 seat part 15, . By making 15t groove-shaped, the amount of accumulated charge can be increased. Because of this, Kiya
Bottom part 15. ．． 15. The distance between them can be reduced compared to the conventional one (FIG. 3), and a high-density DRAM can be obtained.

In addition, in Example 1, the groove 2/ is replaced with the groove z for the gear/P seat part.
I made the depth deeper than step 2, but it will suffice as long as it is the same depth or more.

Embodiment 2 This embodiment has a structure in which a substrate 1/CP+ type impurity layer 31 is provided at the bottom of a deep groove 2/, as shown in FIG. Therefore, the DRAM of FIG. 4 has the same effect as the first embodiment.

Example 3 The DRAM of this embodiment has P as shown in FIG.

Instead of the P-type silicon substrate 1, an epitaxial layer 42 is formed on a P-type silicon substrate 4I, and the groove 43 for the element isolation region is deeper than the surface of the epitaxial layer 42.

Note that the groove 43 may be at the same level as the surface of the epitaxial layer 42. Therefore, the DRAM of FIG. 5 has the same effect as the first embodiment.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a highly reliable semiconductor memory device that can prevent an increase in the amount of accumulated charge in the capacitor section and interference leakage between the capacitor sections.

[Brief explanation of drawings]

1 is a cross-sectional view of a DRAM according to a first embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views of a conventional DRAM, respectively, and FIG. 4 is a cross-sectional view of a DRAM according to a second embodiment of the present invention. FIG. 5 is a sectional view of a DRAM according to Example 3 of the present invention. DESCRIPTION OF SYMBOLS 1... P- type silicon substrate, 3... MOS type transistor, 6... K-type source region, 7... N+ type drain region, 9... Dart electrode, I2.21. 4
3... Groove, I3... Insulating film, I4... Capacitor electrode, 15. ．． 15. ...Groove type cap and bottom part, 2z
. . . Element isolation region, 41.; P+ type silicon substrate, 42 . . Epitaxial layer. Applicant's representative Patent attorney Takehiko Suzue No. 1- No. 2 Fig. 3 Fig. 4

Claims (3)

[Claims] (1) In a semiconductor memory device in which a memory circuit whose main components are a groove-type capacitor part and a MOS transistor is integrally formed on a semiconductor substrate, a groove for the capacitor part is formed on the substrate surface between the groove-type capacitor parts. 1. A semiconductor memory device characterized in that a trench is provided with a depth equal to or greater than , and an element isolation region is provided in this trench. (2) The semiconductor memory device according to claim 1, wherein a highly concentrated impurity layer of the same conductivity type as the semiconductor substrate is provided at the bottom of the trench for the element isolation region. (3) Claims characterized in that the semiconductor substrate is one in which an epitaxial layer is formed on a highly doped semiconductor substrate, and the trench for the element isolation region has a depth equal to or greater than the surface of the substrate. 2. The semiconductor memory device according to item 1.