EP0196733A2 - Verfahren zur Anzeige von Bilddaten - Google Patents

Verfahren zur Anzeige von Bilddaten Download PDF

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Publication number
EP0196733A2
EP0196733A2 EP86300036A EP86300036A EP0196733A2 EP 0196733 A2 EP0196733 A2 EP 0196733A2 EP 86300036 A EP86300036 A EP 86300036A EP 86300036 A EP86300036 A EP 86300036A EP 0196733 A2 EP0196733 A2 EP 0196733A2
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EP
European Patent Office
Prior art keywords
memory elements
pixel data
data
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86300036A
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English (en)
French (fr)
Other versions
EP0196733A3 (de
Inventor
Hiroshi Kurusu
Tokuzo Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dainippon Screen Manufacturing Co Ltd
Original Assignee
Dainippon Screen Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dainippon Screen Manufacturing Co Ltd filed Critical Dainippon Screen Manufacturing Co Ltd
Publication of EP0196733A2 publication Critical patent/EP0196733A2/de
Publication of EP0196733A3 publication Critical patent/EP0196733A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Definitions

  • the present invention relates to a picture processing system, particularly to a method for displaying picture image data stored in a picture image memory in the case of displaying the data on monitoring means of display means such as CRT (cathod ray tube), crystal liquid, plasma etc.
  • CRT cathod ray tube
  • crystal liquid crystal liquid
  • plasma plasma
  • the picture image processing means is adapted that a memory means for displaying having four times of capacity larger than the number of pixels of a monitoring means is provided, and in usual only one fourth of capacity area of the memory means is displayed to perform various processing.
  • a memory means for displaying having four times of capacity larger than the number of pixels of a monitoring means is provided, and in usual only one fourth of capacity area of the memory means is displayed to perform various processing.
  • quantities of information to be processed may be completed only one picture plane of the monitoring means, and in other cases quantities of information to be processed are ranged over the whole picture images.
  • a simple method for displaying a reproduced picture on a reduced picture image display monitoring means from picture image data stored in a memory means so that, in general, the picture image may be displayed and/or reproduced is to thin out reading addresses from the memory means.
  • an access time T of the memory means is longer than a timing t for displaying one pixel (picture element) data on the monitoring means, so that by obtaining an integer N which satisfies t x N ⁇ T, writing each of data of N pixels being arranged in time series into the memory means in parallel, reading the data of N pixels in parallel out of the memory means, and assembling them in series according to the original time series within time duration of t x N, the data are supplied to the monitoring means as a usual picture image display.
  • the first one among the methods is a method in which a display memory means which has a short access time is accessed by a half period of usual reading out period, data for 2N pixels are read out in a period, when parallel/serial conversion (hereinafter, refer to P/S conversion) is carried out, unnecessary data are thinned out so that for one period every other data may be those of the pixels of N.
  • P/S conversion parallel/serial conversion
  • the second method i.e., the remaining method, is a method in which two display memories which store picture image data into the identical addresses are provided.
  • a certain address is read out as the LSB (the lowest significant bit) [0] and simultaneously as the next address (for example, an address of the LSB being "1") the address is read out of the other memory, and unnecessary data are thinned out so that those read out data of 2N pixels may be data of N pixels at P/S conversion time.
  • each of the memory elements addressed independently is accessed so that necessary data of 2 m may be obtained by one parallel reading from the memory elements of 2 m , and in the case of reduction display, each of the addresses in which necessary data are accommodated when data are thinned out is respectively read out in parallel simultaneously, and then these read out data of 2 m are displayed by rearranging these read data in time series.
  • the pixel data read out of the (2K.th) address are output to the side of the monitoring means according to the number of the memory elements, and the pixel data read out of the (2K+l.th) address are output to the side of the monitoring means with the number of the memory elements 1, 0, 3, 2,... 2 m- l, 2 m- 2 sequentially.
  • the smallest reduction ratio of a picture image obtained only by thinning out the picture image data without generating distortion in the picture image by using memory elements of 2 m is 1/2 .
  • usual display, 1/2 reduction display, 1/4 reduction display, ... 1/2 reduction display can be freely selected.
  • the order of the picture image data being stored in the memory elements of 2 m is as follows, that is, with respect to the least significant bit (LSB) address 2 m of the memory elements (for from address 0 to address 2 m ), to the address 0 the pixel data are stored according merely to their order in sequence of the number of the memory elements, to address 1 pixel data which are shifted by 1 in their order are stored according to the order of the number of the memory elements.
  • Picture image data being forced out are entered to addresses of emptied number of the memory elements generated by having been shifted 1. As described the above, the picture image data are stored by shifting by 1 up to addresses 2 m -1 of the memory means.
  • the thinned out picture image data can be read out.
  • the order of the data to be read out in the usual case is that the read out pixel data of 2 m are modified so that they may be arranged in the same order as the picture image data according to the least significant bit ( L S B ) addresses 2 m of the memory elements.
  • L S B least significant bit
  • the addresses of total 2 m are arranged according to the order of the pixel data.
  • the vertical addresses and the horizontal addresses are multiplied by 2 n , and those multiplied by 2 n vertical and horizontal addresses are divided into groups of the memory elements at every memory element numbers 2 n through independent address lines, and at every the least significant addresses of 2 , regarding Oth address of the memory elements in the memory elements groups, the pixel data read out of basing Oth address (which means that the data are read out of by accessing to the Oth address) are read, regarding the first of the memory elements, pixel date read out of basing the first address are read, and regarding kth memory elements, pixel data read out of basing on the kth address are read.
  • the sum of 2 m are read out, and those pixel data are aligned according to their order.
  • a method for modifying order of the pixel data being stored a method for reading out the pixel data by changing addresses to be accessed at every pixel memory according to an object to be displayed (usual display, reduction display) and the lower ranked address 2 m , and basing on a method of rearranging the order of pixel data basing on the object, thus, order of the pixel data are appropriately selected to achieve usual display or reduction display.
  • the embodiment is provided with a display memory 1 having size of horizontal length x vertical length being 2048 x 2048, and there are some cases in which the display memory 1 is displayed on a CRT monitor 2 having a picture plane size of 1024 x 1024.
  • a memory area (In) is equal to the size of the picture plane of 1024 x 1024.
  • Picture image data stored in the display memory 1 comprises, for example, as.shown in Fig. 4, picture data of the number of 4M which are numbered from 0 to 22 22 - 1 according to time sequence thereof.
  • the amount of the whole information is 4M x 1 byte x the number of colors, however, here, information of the 1 byte which expresses gradation and the number of colors are not displayed, so that we do not give further explanation thereto.
  • the pixel data of 4M are represented with the number of groups of time sequentially determined to which they belong and number of locations of the pixels in the group.
  • 16 pixel data of time sequentially determined 127th group In the data groups at the upper corner of the right hand, there are shown 16 pixel data of time sequentially determined 127th group.
  • the last data located at the lower corner of the right hand represent pixel data of the number of 0 to F in the (2 18 - 1)th group.
  • the display memory 1 comprises, as shown in.Fig. 5, 16 pieces of memory elements.(M),...(M) which are disposed in parallel and each having 256K x 1 bit memory capacity.
  • the display memory 1 composes a memory block (MB) and this memory block (MB) is used as 1 bit x 4M in the display memory 1.
  • Each of the memory elements (M) is previously numbered 0, 1, 2, ...,E and F, respectively. Hereinafter, each of the memory elements is indicated discriminatingly by each of the number.
  • the memory elements (M) have numbers from 0 to (12 18 - 1), and assuming that picture image data of time sequential order are accommodated in the memory elements according to the address order, and they are made to correspond to the composition of the picture image data shown in Fig.4, the 16 pixel data in the nth group are accommodated in the same address in each of the memory elements (M), that is, are accommodated in the nth address.
  • Fig. 1 shows a schematic block showing a display system which can reduce 4M picture to 1M (1024x1024) picture.
  • Circuit blocks 3, 4, 5, 6, 7 and 8 are controlled by a signal from a microprocessor 9.
  • a vertical address generating circuit 3 generates addresses from 0 + ⁇ to 1023 + ⁇ (here, ⁇ is a constant set up by the CPU 9, and indicates integers from 0 to 1024 which represent shift values in the vertical direction, and in the case of 1/2 reduction display, value 0 is set up.), in synchronization with a horizontal synchronizing signal from the CRT 2.
  • a horizontal address generator 4 generates addresses from 0 + P to 1023 + ⁇ (here, ⁇ is a constant set up by the CPU 9, and indicates integers from 0 to 1024 which represent shift values in the horizontal direction. In the case of 1/2 reduction , 0 is set up.) within one horizontal synchronizing signal period.
  • a display memory writing circuit 5 feeds an address signal of 4 bits for selecting memory element to the display memory 1, when data are written. Picture image data accommodated in a disc 10 are written into the display memory 1 through the display memory writing circuit 5.
  • the circuits 6 and 7 enable only when a control signal which indicates reduction display is given from the microprocessor 9.
  • the circuit 6 doubles vertical address generated in the vertical address generating circuit 3.
  • the circuit 7 doubles highly ranked 7 bits of the horizontal address generated in the horizontal address generating circuit 4.
  • a P/S conversion control circuit 8 controls a P/S conversion circuit 11 at the rear stage of the display memory 1, basing on an address signal of lower ranked 4 bits fed from the horizontal address generating circuit 4.
  • the P/S conversion control circuit 8 operates with two manners for normal display and reduction display which are different from each other, in response to the control signal from the microprocessor 9.
  • Picture image data written in the display memory 1 are accessed by 18 bits which comprises 11 bits of vertical address from the vertical address generating circuit 3 and the horizontal address composed of the highly ranked 7 bits from the horizontal address generating circuit 4.
  • This address composed of 18 bits is fed to each of the memory elements (M) shown in Fig.5, and from all the memory elements (M) data for one pixel are read out. Reading is carried out every 320ns period (access time of the memory element is equal or shorter than its access time).
  • the data of 16 pixels read out in parallel to one another from the display memory 1 are converted to series data by a clock of 20ns in the P/S conversion circuit 11.
  • the series pixel data are converted into an analog signal(s) in the D/A conversion circuit 12, and displayed on the CRT 2 one pixel for every 20ns.
  • Each of the memory elements (M) is accessed by a memory element address Madd of 18 bits comprising 11 bits vertical addresses 0 to 10 and highly ranked 7 bits Hadd 4 to 10 among the horizontal addresses Hadd 0 to 10.
  • the lower rank 4 bits Hadd 0 to 3 are used to access (chip select) to the address in the memory element (M).
  • the pixel data (1,0) are not written to the address 1 of the memory element (M - 0), but written to the address 1 of the memory element ( M - 1), and the pixel data (l,l) are written in the address 1.
  • Fig. 7(B) appearance of the pixel data written in each of the memory elements is illustrated in Fig. 7(B).
  • the picture data are latched by a latch circuit being provided additionally according to the select signals (CSO, CSl, CS2,...,CSF), and the latched 16 pixel data are written into the memory element in parallel at every writing period (320ns).
  • the order of picture data is remained what it is, when the read out address Hadd4 is an even number, and in the case of it is an odd number, the order of the picture data are alternated.
  • the address produced by doubling the address in normal display means that, as shown in Fig. 1, the highly ranked 7 bits of the horizontal address which is an address of the memory element in the case of d and ⁇ are set to 0 and the 11 bits of the vertical address are doubled, respectively.
  • FIG. 8 An example of a circuit performing the above described control is shown in Fig. 8.
  • an exclusive OR circuit 17 providing with two line systems comprising an address line (15) connected with those even numbered memory elements (M - 0), (M - 2), (M - 4),..,(M - E), and an address line 16 connected with the odd numbered memory elements (M - 1), (M - 3),..,(M - F).
  • the exclusive OR circuit 17 also works to add 1 to all the even numbered addresses.
  • one data are selected from the 16 output data DO to DF by applying the selector 25 which selects one data, and instead of setting 4 bits select signal to be HaddO, Haddl, Hadd2, Hadd3, they are switched to the order of Hadd3, HaddO, Haddl and Hadd2 by the selectors 21 to 24, and thus, output data are to be arranged to the order of the time sequence.
  • the select signal is sent from the P/S conversion control circuit 8.
  • the normal/reduction switching signal EX is set to [H]
  • a control input signal B turns to [H]
  • Hadd3 is set as the LSB, and from the selectors 21, 22, 23 and 24 HaddO, Haddl and Hadd2 are sequentially output.
  • the normal/reduction switching signal EX is turned to a low level signal [L].
  • the gate 18 closes and a gate circuit 19 is opened.
  • the normal memory element address in which the vertical and the horizontal addresses advance by 1 is input as an identified signal to all the memory elements simultaneously, through the gate circuit 19 and passing through the address lines 15 and 16.
  • the select signal to be fed to the selector 25 is to be controlled by the LSB Hadd4 of the horizontal address of the memory element.
  • control input B of the selectors 21, 22, 23 and 24 is [L]
  • input 0 or 1 is selected, while according to the control input A to which Hadd4 is input, either of input 0 or 1 is selected.
  • the selector 25 when the memory element is an even numbered address, the order becomes as D0, Dl,..D F , and when it is an odd numbered address, the order is Dl, D0, D3, D2,..,DF and DE.
  • the exclusive OR circuit 17 and the selector 25 play the same role as that of the P/S conversion circuit 11 shown in Fig. 1. In Fig. 10 there are shown this reading operation and manner of P/S conversion.
  • the above described embodiment relates to the case of 1/2 reduction display, and by applying the same method 1/2 n reduction display is also possible.
  • FIG. 11 there is shown an example of a writing circuit
  • Fig. 12 Fig. 13 and Fig. 14, there are shown examples of writing circuits.
  • the memory element number is selected in the horizontal direction address (HaddO - 3), and at the LSB address (Hadd4 - 7) of the memory element, the time sequence of the pixel data being written and the order of the memory element number are shifted.
  • addresses (HaddO - 3) and addresses (Hadd4 - 7) are added. Overflow resulting from the addition is neglected, and as shown in Fig. 7(c), according to the LSB address of the memory element, writing is performed in the predetermined order.
  • a latch circuit (not shown) is provided, and latched picture image data are latched by the select signals (CSO, CS1,...,CSF), and then the parallel 16 pixel data are written in the memory element at every period.
  • the address doubling circuits 6 and 7 must be vary their setting to 2 times, 4 times, 8 times, 16 times etc. according to desired reduction display, and shift values d and p are set to appropriate shift values such as 0; d/4, ⁇ /4, ⁇ /8, ⁇ /8 ; ⁇ /16, ⁇ /16 etc.
  • addresses may be previously formed in a ROM which addresses the addresses Hadd0 - 7 and reduction ratio so that necessary pixel data necessary for each of reduction display cases shown in Fig. 7(c) may come out in the order of the data.
  • Fig. 13 shows an embodiment of the address forming circuit of each element 32. It is composed of gate providing selectors (51 - 0) - (51 - F) and adders (52 - 0) - (52 - F), and to an address of each of the memory elements (M - 0) - (M - F) a shift amount according to the reduction ratio is added in an adder 52, and the shift amount is selected in selectors (51 - 0)- (51 - F).
  • Values of A and B are, when reduction ratio is 1/2, 0 and 0, when reduction ratio is 1/4, 1 and 0, in the case of reduction ratio being 1/8, 0 and 1, and when 1/16, 1 and 1.
  • the selector 51 selects 0 input at 1/2 reduction display, 1 input at 1/4 reduction display, 2 inputs at 1/8, and 3 inputs at 1/16 reduction display.
  • An address AddMl of the lth memory element (M - l) is divided into 2 groups, that is, they are the following 2 groups; the first group which includes even numbered addresses at which the shift amount is 0 in the case of 1/2 reduction display, the second group which includes odd numbered addresses at which the shift amount is 1 in the same case, and quite the same at the 1/4 reduction display, in this case the address is divided into 4 groups.
  • a shift amount 0 is added
  • a shift amount 1 is added
  • a shift amount 2 is added
  • a shift amount 3 is added to the third group.
  • the address is divided into 2 groups of 8 addresses, and at the Oth address of the group shift amount is 0,....and thus, at the 8th address of the group shift amount is 8.
  • the number of the memory element is the shift amount thereof.
  • Fig. 14 there is shown an embodiment of the P/S conversion control circuit 8' which is composed of a selectors 71 - 74, an adder 77 and gates 75 and 76.
  • a signal of level [H] is input to the gates 75 and 76, and both A and B turn to [H], then, according to the order of addresses H addO - 3 of 3 inputs of the selectors 71 to 73, they are output.
  • addresses Hadd4 to 7 are added thereto and are output to the selector 25. As shown in Fig. 7(c), the addresses Hadd4 to 7 are. added to the addresses Hadd0 to 3 as shift amounts.
  • the addresses HaddO to 3 exist at every two addresses, accordingly, by slipping off the HaddO - 3 by 1 (that is, as the order of Haddl, Hadd2, Hadd3, Hadd0), at. every 2 addresses the number of the memory elements are selected and added the Hadd4 to 7 thereto, they come to be equal to the shift amount in the address direction of the memory element shown in Fig. 7(c).
  • the Hadd0 - 3 exist at every 4 addresses, so that by slipping off by 1 from each of the conditions in the case of 1/2 reduction display, that is, each of the Hadd0 to.3 is slipped off by 1 (i.e., in the order of Hadd2, 3, 0, 1), at every 4 addresses memory elements are selected and the Hadd4 to 7 are added thereto, so that it comes to be equal to the shift amount in the address direction of the memory element shown in Fig. 7(C). Then, overflow is neglected.
  • the Hadd0 to 3 are at every 8 addresses, by slipping off the HaddO - 3 by 1 from the case of 1/4 reduction display (in the order of Hadd3, 0, 1, 2), at every 8 addresses memory elements are selected, and by being added the Hadd4 to 7 they come to be equal to the shift amount in the address direction of the memory elements shown in Fig. 7(c).
  • the HaddO - 3 exist at every 16 addresses, so that the addresses makes a round which results in returning to the original order.
  • the data outputs from the memory elements (M - 0) - (M - F) are fed to the selector 25 through the latch circuit 26 at every reading period.
  • writing and reading pixel data are adapted to be sequentially slipped off, however, it is needless to say that if ROM is used, within periodical range pixel data can be read out with any desired order irrespective of the order.
  • the present invention is to control writing and reading pixel data to the memory element, and further control arrangement of the read out data, and therefore the present invention can realize not only 1/2, 1/4 reduction displays but also, in general, up to 1/2 n reduction display.
  • addresses to be given to picture memory means are controlled so that time sequential picture data may be thinned out by pixel data corresponding to the reduction ratio, accordingly, a reduced picture image of high fidelity to the original picture can be obtained, in addition, without using any high speed memory element, and without applying a plurality of picture memory means, but merely using conventional picture memory means, reduction picture images of high fidelity to the original picture can be obtained.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Editing Of Facsimile Originals (AREA)
EP86300036A 1985-02-27 1986-01-06 Verfahren zur Anzeige von Bilddaten Withdrawn EP0196733A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60036275A JPS62988A (ja) 1985-02-27 1985-02-27 画像デ−タの表示方法
JP36275/85 1985-02-27

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Publication Number Publication Date
EP0196733A2 true EP0196733A2 (de) 1986-10-08
EP0196733A3 EP0196733A3 (de) 1990-03-07

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EP86300036A Withdrawn EP0196733A3 (de) 1985-02-27 1986-01-06 Verfahren zur Anzeige von Bilddaten

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0314922A2 (de) * 1987-11-03 1989-05-10 International Business Machines Corporation Gerät zur Bildpunktdatenübertragung von RAM-Speichern zu einer Anzeige
EP0334524A2 (de) * 1988-03-23 1989-09-27 Du Pont Pixel Systems Limited Kreuzschienenkonverter
EP0342022A2 (de) * 1988-05-11 1989-11-15 Fujitsu Limited System zum Lesen von Bilddaten in einem digitalen Bildverarbeitungssystem
EP0358374A2 (de) * 1988-09-06 1990-03-14 International Business Machines Corporation Datentransfer zwischen Speicher

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2647379B2 (ja) * 1987-02-18 1997-08-27 キヤノン株式会社 画像処理装置
DE3804938C2 (de) * 1987-02-18 1994-07-28 Canon Kk Bildverarbeitungseinrichtung
JP5777458B2 (ja) * 2011-09-12 2015-09-09 キヤノン株式会社 パターン識別装置、パターン識別方法及びプログラム

Citations (4)

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Publication number Priority date Publication date Assignee Title
US3794970A (en) * 1972-11-24 1974-02-26 Ibm Storage access apparatus
GB2092785A (en) * 1981-01-26 1982-08-18 Rca Corp Window-scanned memory
DE3109169A1 (de) * 1981-03-11 1982-09-23 Philips Patentverwaltung Gmbh, 2000 Hamburg Verfahren und anordnung zur erzeugung von bildpunktsignalen
EP0139094A2 (de) * 1983-08-16 1985-05-02 International Business Machines Corporation Rasteranzeigeeinrichtung mit einem Vergleicher für eine Vielfachspeichereinrichtung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081661A (ja) * 1983-10-11 1985-05-09 Matsushita Electric Ind Co Ltd デ−タ記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794970A (en) * 1972-11-24 1974-02-26 Ibm Storage access apparatus
GB2092785A (en) * 1981-01-26 1982-08-18 Rca Corp Window-scanned memory
DE3109169A1 (de) * 1981-03-11 1982-09-23 Philips Patentverwaltung Gmbh, 2000 Hamburg Verfahren und anordnung zur erzeugung von bildpunktsignalen
EP0139094A2 (de) * 1983-08-16 1985-05-02 International Business Machines Corporation Rasteranzeigeeinrichtung mit einem Vergleicher für eine Vielfachspeichereinrichtung

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0314922A2 (de) * 1987-11-03 1989-05-10 International Business Machines Corporation Gerät zur Bildpunktdatenübertragung von RAM-Speichern zu einer Anzeige
EP0314922A3 (de) * 1987-11-03 1991-03-20 International Business Machines Corporation Gerät zur Bildpunktdatenübertragung von RAM-Speichern zu einer Anzeige
EP0334524A2 (de) * 1988-03-23 1989-09-27 Du Pont Pixel Systems Limited Kreuzschienenkonverter
EP0334524A3 (de) * 1988-03-23 1991-08-28 Du Pont Pixel Systems Limited Kreuzschienenkonverter
US5047760A (en) * 1988-03-23 1991-09-10 Dupont Pixel Systems Limited Crossbar converter
EP0342022A2 (de) * 1988-05-11 1989-11-15 Fujitsu Limited System zum Lesen von Bilddaten in einem digitalen Bildverarbeitungssystem
EP0342022A3 (de) * 1988-05-11 1991-04-10 Fujitsu Limited System zum Lesen von Bilddaten in einem digitalen Bildverarbeitungssystem
EP0358374A2 (de) * 1988-09-06 1990-03-14 International Business Machines Corporation Datentransfer zwischen Speicher
EP0358374A3 (de) * 1988-09-06 1991-08-21 International Business Machines Corporation Datentransfer zwischen Speicher

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EP0196733A3 (de) 1990-03-07

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