EP0163148B1 - Système de traitement de données avec chevauchement du transfert de données entre registres de l'unité centrale de calcul et transfert de données de et vers la mémoire principale - Google Patents

Système de traitement de données avec chevauchement du transfert de données entre registres de l'unité centrale de calcul et transfert de données de et vers la mémoire principale Download PDF

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Publication number
EP0163148B1
EP0163148B1 EP85105246A EP85105246A EP0163148B1 EP 0163148 B1 EP0163148 B1 EP 0163148B1 EP 85105246 A EP85105246 A EP 85105246A EP 85105246 A EP85105246 A EP 85105246A EP 0163148 B1 EP0163148 B1 EP 0163148B1
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Prior art keywords
data
register
cpu
tag
transfer
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Expired
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EP85105246A
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German (de)
English (en)
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EP0163148A3 (en
EP0163148A2 (fr
Inventor
Philip Doyce Hester
William Michael Johnson
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International Business Machines Corp
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International Business Machines Corp
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Publication of EP0163148A3 publication Critical patent/EP0163148A3/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Definitions

  • the present invention relates to data processing systems and particularly to data processing systems having a primary I/0 bus to main storage and other I/0 devices.
  • such local storage means may customarily comprise a plurality of RAM registers in which the data fetched from the external main storage is temporarily stored while it is being manipulated in the CPU.
  • Such data manipulation normally requires a great number of register to register transfers within CPU.
  • register to register transfers are relatively short in duration, normally requiring an effective throughput one CPU time cycle to complete.
  • transfers over the I/0 bus to main storage or other I/O devices are much longer, normally requiring three or more CPU time cycles to complete.
  • it has been customary to employ a memory cache expedient in the CPU so that a substantial number of data transfer transactions from the I/0 bus to main storage or other I/0 devices may be carried out during time periods previous to their use in the CPU and stored or buffered in the storage cache associated with the CPU.
  • the present invention provides a solution to the microprocessor problem of maintaining high processing speeds while eliminating or substantially reducing CPU storage caches by providing apparatus in which the register to register data transfers required for CPU computations and other operations are conducted coincidentally or overlapped with transfer of data to and from main memory storage or other I/O units.
  • the invention is directed to data processing systems comprising a CPU, at least one external unit such as main storage requiring data from or providing data to the CPU, and I/0 bus for the transfer of data between the CPU and the external unit.
  • the present CPU comprises means for executing instructions on data, means responsive to the executing means for transferring data to or from the external unit over the bus during synchronized CPU time cycles, means responsive to the executing means for storing data in a plurality of registers within the CPU and means for internally transferring data within the CPU registers concurrently during the transfer of data to or from the external unit control means connected to the executing means, transferring means and storing means are provided for controlling the transfer of data wherein the transfer of data between the CPU registers coincides with the transfer of data to or from the external unit, said control means further including means for determining when data required for execution of a first of a sequence of instructions in the CPU has not been stored in one or more of the CPU registers as required by the first instruction and delaying the execution of the first instruction until such data is stored in one or more
  • control means further comprises means for generating data transfer commands to the external unit, means for assigning one of the plurality of registers within the CPU to which data from the external unit is to be transferred, and means connected to the assigning means for storing a tag identifying the assigned register in a tag register, for comparing subsequent data transfer commands to the stored tags to determine if data for these subsequent data transfer commands includes data resulting from the external unit transfer commands, for clearing the tag register when the external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared.
  • FIG. 1 a generalized diagram of the apparatus which may be used to carry out the present invention is shown.
  • the pertinent elements of the present invention are shown to be contained within CPU 10 which communicates over I/0 bus or channel 11 with main memory storage 12 through storage controller 13 and with various I/O devices such as diskette drives, printer or display (not shown) via I/0 bus controller 14.
  • the CPU 10 may be implemented using any conventional microprocessor. Before describing the particulars of the present invention, general operation of the CPU insofar as pertinent to the present invention will now be described. When the CPU is operational, instructions to be carried out are fetched from storage in the conventional manner and temporarily stored in an instruction buffer 15.
  • instruction multiplexer 16 breaks up the instruction, a portion of which goes to control logic 17 to control CPU operations as will be hereinafter described and a portion to various registers in the register array 18 which provides the local storage means for the CPU.
  • register array 18 data may be transferred through the ALU/Shifter 21 where various computorial operations may be carried out or to main storage via register 22, bus 23 and I/0 bus 11.
  • Data from main storage may be returned to the CPU via bus 11, bus 24, formatter 25 which will be subsequently described in greater detail back to register array 18.
  • data may be returned from the ALU/Shifter 21 back to register array 18 via ALU output register 26 and bus 27. It should be understood that a great many transactions within the CPU may involve operations on the contents of the registers in array 18. These will be referred to as register to register data transfers. Other transfers will be to and from main storage 12 or I/0 bus controller 14 via I/O bus 11.
  • Instructions either already in CPU 10 or obtained from main storage are stored in instruction buffer 15.
  • the instruction may be for a register to register transfer in which case it will have the format shown in Fig. 7 or it will be a transfer to or from main storage or other I/O external unit devices in which case it will have the format shown in Fig. 8.
  • Instruction multiplexer 16 will divide the instruction as follows.
  • the OP code 31 which indicates the type of instruction to be performed is applied to control logic 17 which will control the execution of the function by applying execute instructions through control register 32 (Fig. 1).
  • control register 32 Fig. 1).
  • the next two sections 33 and 34 of the instruction in Fig. 7 indicate the contents of the source registers.
  • R3 and R4 are the two source registers which are to be involved in the computation.
  • the last section 35 indicates the destination register.
  • contents of register 3 and register 4 are to be added and placed in destination register 3.
  • signals are applied along lines 33 and 34 resulting in the reading of the contents of the first and second source registers which will result in R3 and R4 being read.
  • the control register 32 will contain the add function resulting from the reading of the operational code.
  • control information i.e., the add function
  • control register 32 is used to control the operation to be carried out.
  • Control code from control register 32 is applied to the ALU/Shifter via input 37.
  • the operation in the ALU is performed in the conventional manner, and results of the operation are latched in ALU output register 26.
  • the next phase (which may be referred to as write back), the result of the ALU operation is written back or returned via bus 27 to the destination register, in the present example, R3 as indicated by the destination register input 49.
  • Each of these operations i.e., fetch, execute and write back is performed in a single CPU time cycle. While we have illustrated the carrying out of a single instruction, it should be noted that consecutive instructions are overlapped so that when a first instruction is in its execute phase, a second instruction may be initiated into its fetch phase, and when a first instruction is in its store back phase, the second instruction may be in its execute phase and a third instruction may be in its initial fetch phase. As a result, because of the overlapping of three instructions, while the normal internal CPU operation involving register to register transfers take three CPU time cycles to complete, the actual throughput of the CPU is one complete operation per cycle.
  • a transaction involving a transfer to or from main storage is carried out in a similar fashion in so far as CPU operations are concerned. It is controlled by the main storage transfer instruction shown in Fig. 8.
  • the instruction involves an OP code which is divided out by instruction multiplexer 16 through control logic 17 and applied to control register 32 indicating the type of storage operation, i.e., either store (write into main storage) or load (read out of main storage). This OP code is applied to the ALU/Shifter 21 as previously described via input 37.
  • Section 39 of the main storage transfer instruction indicates that the contents of register R2 in register array 18 is to be stored or written into main storage or in the case of a load operation, the destination register into which data read from main storage is loaded.
  • the equipment of the present specific embodiment it is possible to overlap two transfers to or from main storage with each other since it takes six CPU time cycles to complete a transfer . to or from main storage, with the overlap of two of these transfers, the effective throughput is one complete transferto or from main storage in three CPU time cycles. Since, as we have indicated above, the effective throughput of an internal register to register transfer within the CPU is one register to register transfer per CPU time cycle, the effective throughput of the apparatus is such that while one transfer to or from main storage is taking place, three register to register transfers within the CPU may coincidentally take place.
  • the apparatus of the present invention is capable of dynamically determining data dependencies, determining whether sufficient previous operations have been completed to provide the data required in the subsequent operation.
  • An example of this situation can occur when in a sequence of operation, an execution of an instruction is requested before the execution of a previously commenced but overlapped instruction which would provide data required by the subsequent instruction has been completed.
  • a main storage transfer instruction (Fig. 8) which is a load instruction whereby section 39 will indicate a destination register in array 18 to which data read from main storage will be loaded.
  • a load instruction whereby section 39 will indicate a destination register in array 18 to which data read from main storage will be loaded.
  • the tag logic shown in Fig. 2 has two tag registers, tag 0 and tag 1 which will keep track of registers in register array 18 and will function as destination registers for keeping track of load transfers from main storage 12 back to the designated array register which is respectively identified by either the tag (p register or the tag 1 register. Accordingly, after multiplexing, the first and second source registers which will be used to determine the storage address (Fig. 8) are applied to array 18 via lines 33 and 34 and are also respectively applied to the tag logic shown in Fig. 2 via lines 45 and 46.
  • Tag q Tag q register 43 has associated therewith compare units 52, 53 and 54 for respectively comparing the two source register lines 45 and 46 as well as the destination register line 47 with the destination register stored in tag ⁇ register 43.
  • tag 1 register 44 has associated therewith compare units 55, 56 and 57 but likewise comparing the inputs on lines 45, 46 and 47 with the contents of tag 1 register 44.
  • step 60 a determination is made, step 60, as to whether a tag register ( ⁇ or 1) is available. If none is available, then step 61, the instruction awaits the availability of a tag 4) or tag 1 register.
  • step 62 a determination is made, step 62, as to whether the tag q) register has already been used for a previous load instruction that is not as yet complete which designates the same destination load register in array 18. If this is the case, then, step 63, the whole previous instruction involving tag ⁇ is cancelled. After the cancellation of the previous instruction involving tag ⁇ or if the tag ⁇ register has not been used to designate a load register, then, step 64, a determination is made as to whether the tag 1 register has already been used for a previous load instruction which is not as yet complete which designates the same destination load register in array 18. If this is the case, then, step 65, the whole previous instruction involving tag 1 is cancelled.
  • step 66 a determination is made, step 66, as to whether the tag 4) register is available. If it is, then tag ⁇ register is allocated to save the load register number of the current instruction and the format information is applied via line 50 (Fig. 2) to tag register ⁇ . On the other hand, if the tag ⁇ register is not available, then the tag 1 register must be available. Consequently, it is allocated to the load register of the current instruction and the format data is applied via line 51.
  • the tag operation is set forth in step 60-68 is carried out under the control of tag control logic 70 which communicates with the tag ⁇ and the tag 1 registers via lines 72 and 73.
  • the outputs of tag ⁇ register 43 is applied to multiplexer 71 via line 72 while the output of tag 1 register 44 is applied to multiplexer 71 via line 73.
  • This multiplexed output of multiplexer 71 is applied to register array 18 over line 74 to provide to register array 18 the destination register address where data returned from main storage over line 24 is to be loaded in register array 18.
  • Lines 75 and 76 similarly apply to multiplexer 77.
  • the format control data (FMT) respectively is stored in association with tag register ⁇ and tag register 1 so that multiplexer 77 can provide an output along line 78 to formatter 25 indicative of the format of the data to be loaded in the designated register.
  • tag decode logic 80 determines whether the tag is one of several conventional tags indicating an instruction fetched from storage or one of the pair, tag ⁇ , tag 1. If the tag is indicative of an instruction, the tag code logic signals the instruction buffer 15 via line 81 to load the instruction in the instruction buffer via line 83.
  • step 85 a determination is made as to whether the tag is indicative of the tag ⁇ register. If it is, then, step 86, a further determination is made as to whether tag ⁇ has been cancelled. A tag is cancelled when its associated register has been overwritten so that the load associated with the tag is no longer valid. Thus, if the tag has not been cancelled, then, step 87, the data is loaded into the register of array 18 indicated in the tag ⁇ register. This is done by having the tag decode 80 issue a signal on line 82 (Fig.
  • tag control logic 70 in Fig. 2 causes tag control logic 70 in Fig. 2 to have the tag ⁇ register 43 put out its contents on line 72 which in turn passes through multiplexer 71 from which the appropriate load register destination which has been stored in the tag ⁇ register is applied over line 74 to register array 18.
  • format data in tag register ⁇ is applied via line 75 through multiplexer 77 and line 78 to provide the requisite format control.
  • the tag ⁇ register is set to an available state, step 88.
  • step 85 determines whether the tag associated with the data from storage is not a tag. If a determination was made in decision step 85 that the tag associated with the data from storage is not a tag (p, a determination is then made in step 90 of whether the tag is a tag 1. Then, steps 91, 92 and 93 respectively the same as steps 86, 87 and 88 are carried out with respect to the tag 1 register.
  • step 100 Fig. 4
  • a determination is made as to whether either source register equals the register in tag (p. This comparison is made using compare units 52 and 53 in Fig. 2. If there is such a comparison, then it indicates that there is a data dependency on the contents of the register indicated by tag 0 and, step 101, the system is put into a wait state. In Fig. 2 this is accomplished by an output on either line 102 or 103 respectively resulting from a compare on either compare unit 52 or compare unit 53 causing OR gate 104 to produce a hold output on line 105 to control logic 17.
  • step 100 If it is determined in step 100 (Fig. 4) that neither source register equals a tag ⁇ register, then, the operation proceeds to step 106, and the above procedure is repeated with respect to the tag 1 register 44 (Fig. 2) using compare units 55 and 56.
  • a compare leads to step 107 resulting in a wait or hold off until the register indicated in the tag 1 register is finally loaded by return from main storage.
  • Fig. 2 it should be noted that in addition to comparing source registers in a given instruction as described with respect to the procedure of Fig. 4, the destination register in the instruction applied via line 47 is also compared to tag ⁇ register 43 and tag 1 register 44 respectively by compare unit 54 and compare unit 57 resulting in either an output cancelling the tag 4) register on line 109 to control logic 17 or cancelling the tag 1 register on line 110 control logic 17.
  • This procedure is shown in the flow chart of Fig. 5.
  • the cancel procedure shown with respect to Figs. 5 and 2 covers the situation where a subsequent command transfers data to the load destination register indicated by a previous command before the transfer involved in the previous command is completed. In such a case, the assigned destination of the previous command is cancelled thereby, in effect, cancelling the previous command.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
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  • Information Transfer Systems (AREA)

Claims (5)

1. Système de traitement de données comprenant une unité centrale de traitement ou CPU (10), au moins une unité externe (12) nécessitantant des données provenant de ladite unité CPU ou lui en transmettant et un bus d'entrée/sortie (E/S) (11) pour transférer lesdites données entre ladite unité CPU et ladite unité externe, comprenant des moyens (21) pour exécuter des instructions relatives aux données, des moyens (13) qui, en réponse auxdits moyens d'exécution, transferrent des données de et vers ladite unité externe sur ledit bus pendant des cycles chronologiques synchronisés de l'unité CPU, des moyens (26) qui, en réponse auxdits moyens d'exécution, stockent des données dans une pluralité de registres (18) dans ladite unité CPU, et des moyens (16,17) pour transférer de façon interne des données dans lesdits registres dans le même temps que le transfert de données de et vers ladite unité externe a lieu,
ledit système étant caractérisé en ce qu'il comprend:
des moyens de commande (17) connectés auxdits moyens d'exécution, de transfert et de stockage pour commander le transfert de données de telle sorte que le transfert de données entre les registres de l'unité CPU coïncide avec le transfert de données de ou vers l'unité externe, lesdits moyens de commande comprenant en outre des moyens (42) pour:
déterminer à quel moment des données requises aux fins de l'exécution d'une première suite d'instructions dans ladite unité CPU n'ont pas été stockées dans un ou plusieurs des registres de l'unité CPU comme l'exigeait la première instruction, et
retarder l'exécution de la première instruction jusqu'à ce que ces données soient stockées dans un ou plusieurs des registres de l'unité CPU tout en permettant l'exécution des autres instructions de ladite suite quine nécessitent aucune donnée résultant de la première opération.
2. Système selon la revendication 1 dans lequel lesdits moyens de commande (16, 17) comprennent:
des moyens pour engendrer des commandes de transfert de données à l'intention de ladite unité externe (12),
des moyens (16) pour affecter l'un des registres (18) de ladite pluralité de registres contenus dans ladite unité CPU à la réception des données qui doivent lui être transférées depuis ladite unité externe, et
des moyens (42) connectés auxdits moyens d'affectation pour stocker une étiquette identifiant ledit registre affecté dans un registre d'étiquettes (43, 44) pour comparer les commandes ultérieures de transfert de données avec les étiquettes stockées afin de déterminer si les données afférentes à ces commandes ultérieures comprennent des données résultant de la commande de transfert à l'unité externe, pour effacer ladite étiquette dans le registre d'étiquettes une fois le transfert de données à l'unité externe achevé, et pour retarder l'exécution de toute commande ultérieure de transfert de données nécessitant des données provenant du résultat de ce transfert de données à l'unité externe jusqu'à ce que l'étiquette ait été effacée.
3. Système selon la revendication 2 dans lequel lesdits moyens de commande (16, 17) comprennent en outre:
des moyens pour annuler une commande antérieure de transfert de données au cas où une commande ultérieure de transfert de données affecterait le même registre de l'unité CPU que celui affecté par la commande antérieure avant que le transfert afférent à la commande antérieure ne soit achevé.
4. Système selon la revendication 3 dans lequel lesdits moyens de commande (16, 17) comprennent en outre:
des moyens pour engendrer des commandes de transfert de registre à registre, et
des moyens pour comparer lesdites commandes de transfert de registre à registre avec lesdites étiquettes stockées et pour annuler une commande antérieure de transfert de données au cas où une commande ultérieure de transfert de registre à registre tranfèrerait des données au même registre que celui affecté par la commande antérieure avant que le transfert afférent à la commande antérieure ne soit achevé.
5. Système selon l'une quelconque des revendications précédentes dans lequel ladite unité externe (12) est une unité externe de stockage de données.
EP85105246A 1984-05-31 1985-04-30 Système de traitement de données avec chevauchement du transfert de données entre registres de l'unité centrale de calcul et transfert de données de et vers la mémoire principale Expired EP0163148B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US615984 1984-05-31
US06/615,984 US4630195A (en) 1984-05-31 1984-05-31 Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage

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EP0163148A2 EP0163148A2 (fr) 1985-12-04
EP0163148A3 EP0163148A3 (en) 1987-12-23
EP0163148B1 true EP0163148B1 (fr) 1990-11-07

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US (1) US4630195A (fr)
EP (1) EP0163148B1 (fr)
JP (1) JPH0640307B2 (fr)
CA (1) CA1225748A (fr)
DE (1) DE3580396D1 (fr)
MY (1) MY100954A (fr)

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EP0163148A3 (en) 1987-12-23
EP0163148A2 (fr) 1985-12-04
US4630195A (en) 1986-12-16
MY100954A (en) 1991-06-15
CA1225748A (fr) 1987-08-18
JPH0640307B2 (ja) 1994-05-25
DE3580396D1 (de) 1990-12-13
JPS60256866A (ja) 1985-12-18

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