EP0132454A1 - Méthode et dispositif pour l'affichage typographique à haute définition de texte - Google Patents

Méthode et dispositif pour l'affichage typographique à haute définition de texte Download PDF

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Publication number
EP0132454A1
EP0132454A1 EP83107478A EP83107478A EP0132454A1 EP 0132454 A1 EP0132454 A1 EP 0132454A1 EP 83107478 A EP83107478 A EP 83107478A EP 83107478 A EP83107478 A EP 83107478A EP 0132454 A1 EP0132454 A1 EP 0132454A1
Authority
EP
European Patent Office
Prior art keywords
gray
bit
pixels
nibble
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83107478A
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German (de)
English (en)
Inventor
Peter Karow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dr Ing Rudolf Hell GmbH
Original Assignee
Dr Ing Rudolf Hell GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dr Ing Rudolf Hell GmbH filed Critical Dr Ing Rudolf Hell GmbH
Priority to EP83107478A priority Critical patent/EP0132454A1/fr
Publication of EP0132454A1 publication Critical patent/EP0132454A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G09G5/28—Generation of individual character patterns for enhancement of character form, e.g. smoothing

Definitions

  • the invention relates to the field of computer-controlled rendering of fonts.
  • the computer-controlled rendering of fonts is used today for the dialogue between humans and computers and is used to record, check, change and reproduce data.
  • screen terminals are used, which essentially consist of the following components: alphanumeric keyboard, computer interface, letter memory, display and control electronics and picture tube.
  • the letter memory consists, for. B. from PROM memories (Programmable Read Only Memory), the image information for the representation of each character, for. B. letters, numbers or punctuation marks etc. on the screen.
  • matrices of 7 x 9 bits are stored for each letter and displayed on the screen.
  • Each bit corresponds to a pixel, which can be either black or white.
  • a pixel which can be either black or white.
  • the letter "w” if it is to be reproduced in a font in which it is provided with serifs, is not readily recognizable as such, while in the representation without serifs the white portion of some letters, especially the letter "I" is too big.
  • the object of the invention is therefore to improve the legibility of the fonts and to better express the typographical features.
  • the invention achieves this in that the pixels to be displayed for the letters are stored in the form of gray value matrices by means of multi-bit bytes and recorded as gray values.
  • Another embodiment of the invention is that a multi-bit key of half Byte is used.
  • the gray value matrices all have the same height, preferably 16 gray value points and different widths, preferably 3-16 gray values, adapted to the width of the characters to be displayed.
  • a picture tube with more than 512 x 512 pixels, preferably 1024 lines of 1024 pixels or more without field separation can be provided.
  • the inventive device for implementing the method may be characterized preferably in that a bit - Map of the presentation of each screen character storage for storing character with at least n times as many rows and at least m times as much points per line as indicated on the Screen can be displayed, is provided and is read out n-line by line and summarized in m-pixel width by means of a computer, the corresponding gray value being determined for each mxn pixel and this information as multi-bit byte in the form of gray value matrices for the characters is storable.
  • the letter M and the small dot are shown with gray values.
  • the height of the matrices is constant, e.g. B. with 16 gray dots, and the width variable, z. B. with 16 gray dots, depending on how the width of the respective character requires, about 3 for the small dot and 16 for the small M.
  • a different picture tube than was previously used for screen terminals should be used, namely a picture tube with more than 512 x 512 pixels without field separation.
  • a picture tube with 1024 lines of 1024 pixels or more without field separation e.g. B. to represent the area of a DIN A4 page of about 200 mm wide and 300 mm high.
  • the line width is about 0.3 mm and the height of the capital letters is 3.3 mm.
  • a differently determined gray value can also be used to achieve a more favorable gradation.
  • FIG. 3 shows the representation of this character according to the prior art with a 64 x 64 bit matrix per letter. As can be seen from this, the quality is worse than in the representation with gray values according to FIG. 3.
  • the letter lines can get a desired thinning with lighter gray points in the middle.
  • FIGS. 6a to 6c show the mode of operation of the method according to the invention.
  • Fig. 6a shows the bit map for this letter with the z. B. in newspaper printing, the usual number of bits of 34 x 34 bits per 9p letters, with the "over pixels” combined according to the invention to form rectangles (in the example shown, 4 x 4 pixels). The number of black bits contained in each of these rectangles is indicated.
  • FIG. 6c shows how this letter would look like a quarter with 8.5 x 8.5 pixels per letter in pure black and white reproduction (black the rectangles with at least 7 and white, those with 6 or less black bits like rectangle) - namely completely illegible.
  • the method and device according to the invention can achieve a number of advantages over known terminals, e.g. B. a high-quality rendering of fonts, thus a significant improvement in legibility - that is, ergonomically cheaper -, the reproduction of typography and the choice of various fonts as well as the possibility to save characters in a much nicer form than before and display them on the screen.
  • Figure 7 (1) is a bus line via which the modules (2 to 7) can communicate with each other, for. B. a commercially available VME bus.
  • a font memory (2) is provided in which the bit matrices for the individual characters are stored permanently, preferably on magnetic disks (floppy disks). The sum of all characters of a certain font forms a so-called font.
  • a bit matrix of 34 x 34 bits is provided for a font that is to be displayed in 9p font size, cf. Fig. 1, in which the number of black pixels per 4 x 4 bit square are also entered.
  • the text to be set is from a sentence calculator (3), z. B.
  • the text commands to be processed by the typesetting computer (3) contain, in addition to the text, information about the thickness of each letter, ie the exact distance in bits, which it has before with a small white area (width) and a small white area afterwards. In this way, the sentence computer (3) can determine the most advantageous starting position for the bit map of the respective subsequent letter from the information of the character just set.
  • the partial byte computer (6) used according to the invention and also connected to the BUS (1) works.
  • it is a nibble byte computer, eg. B. a FORCE CPU 68000 Sys 68 K / CPU-1.
  • the computer (6) proceeds line by line and forms the first 1 x 1000 nibbles of the memory (7) from the first 4 x 4000 bits of the bit map (5) and likewise from the second 4 x 4000 bits the second 1 x 1000 nibbles, etc.
  • the video controller Independent of both the sentence processor (3) and the nibble processor (6), the video controller only connects to the nibble memory (7), but not to the BUS line (1) (8) from the nibble memory (7) line by line 1000 nibbles each. From these, the television signals for a television line are generated via the digital-to-analog converter (9) required for the screen input and are offered to the electronics of the monitor (10).
  • FIG. 8 The timely completion of these orders can be seen in FIG. 8, in which the top line represents the transfer cycle, which can be, for example, 125 ns.
  • the successive order numbers are given in the second line.
  • the requested nibble packet is transferred to the video controller (8) (transfer points F 1 , F 2 , F 3 ... ) , ( end points E 1 , E2, E3 ... ) .
  • FIG. 8 it is provided according to the preferred embodiment of the invention shown that several partially overlapping jobs - in the example shown 4 - are taken over and executed at the same time, as a result of which the transmission speed is considerably accelerated.
  • Figure 9 shows a circuit suitable for this purpose. It is a memory into and from which data can be transmitted asynchronously in both ways.
  • the block circuit enables multiple accesses, four times in the example shown. ,
  • an address sent by an address generator which will be shown later in FIGS. 10a and b, under which a 32-bit word is to be read, passes via the transfer interface b, which is denoted by (34) is in one of the 4 address / data registers (23), (26), (29), (32). Which one exactly depends on the address. With consecutive addresses, the registers (23), (26), (29), (32) are addressed in succession.
  • Each of the 4 registers is connected to a memory matrix (24), (27), (30), (33) with a capacity of 64 K 32 bit words and a memory controller (124, 127, 130, 133).
  • the memory controller which ensures the correct timing for the memory modules, is known per se and is made up of standard TTL modules.
  • the memory matrix is made up of 64 K-bit dynamic RAM memories (e.g. M ostek M K 4564). After the access time of the memory matrix (24), (27), (30), (33) has expired, the data are available at the output of the matrix and are written into the address / data registers (23), (26), (29), (32 ) loaded. Via the transfer interface (34), they arrive in a nibble byte catch register of the video controller (8).
  • the access of the nibble computer (6) is analogous to the memory access of the video controller.
  • connection to the bus (1) via the interface a takes place via the registers (22), (25), (28) and (31).
  • FIGS. 10a and 10b The transfer from the nibble memory (7) to the monitor (10) is shown in greater detail in FIGS. 10a and 10b.
  • An address generator (35) is provided (e.g. AMD AM 2932), which is controlled via a basic clock d. This clock is supplied by the synchronization generator (20) and is identical to the basic clock shown in FIG. 3, ie the transfer clock.
  • the address generator (35) via gives the current address of the nibble packet to be called to an address register (36) (e.g. TI SN 74LS374), which takes over the address with the system clock and makes it available at the output.
  • the address reaches the nibble memory (7) via a bus driver (21).
  • the data supplied by the nibble memory arrives in the nibble byte register (12) via a selector (11), where it is accepted with the system clock c.
  • a nibble packet consisting of 8 nibbles is available at the output of the synchronous register (12).
  • the individual nibbles are selected in sequence via a 1 out of 8 selector (15) and passed on to a nibble representation register (18), into which they are adopted with the system clock c.
  • the 1 out of 8 selector (15) has 8 inputs and a control unit (17).
  • the control unit (17) consists of a register (171) which is controlled by the system clock c.
  • the register (171) is connected to a selector (172) which is controlled by the basic clock d, which, like the clock c, is supplied by the synchronization generator (20).
  • the clock c is 8 times faster than the clock d since the 1 out of 8 selector (15) is queried 8 times in a clock period of d.
  • the selector (172) is also connected to a step-up circuit (173) and to a zero generator (174), which is also driven by the clock d.
  • the control unit (17) is reset via the control signal d, so that the first nibble via the 1 out of 8 selector (15) to a nibble representation register (18).
  • the system clock c increases the value of the control unit by 1, and the next nibble reaches the nibble representation register (18) via the 1 from the B selector (15).
  • the last nibble of the nibble packet is switched through to the nibble representation register (18).
  • a new output cycle of the nibbles then begins with the resetting of the control unit (17) via the control line d.
  • the nibble in the nibble representation register (18) is converted into an analog voltage signal via the digital / analog converter (19) (e.g. Analogic MP 8318) and sent to the monitor (10) as a video signal in the video input.
  • the digital / analog converter (19) e.g. Analogic MP 8318
  • a known and commercially available synchronization generator (10) which can be constructed discretely from standard TTL modules, supplies the necessary synchronization signals (horizontal and vertical synchronization signals) for operating the monitor (10) as well as the basic clock d and the 8 times higher clock c.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP83107478A 1983-07-29 1983-07-29 Méthode et dispositif pour l'affichage typographique à haute définition de texte Withdrawn EP0132454A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP83107478A EP0132454A1 (fr) 1983-07-29 1983-07-29 Méthode et dispositif pour l'affichage typographique à haute définition de texte

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP83107478A EP0132454A1 (fr) 1983-07-29 1983-07-29 Méthode et dispositif pour l'affichage typographique à haute définition de texte

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EP0132454A1 true EP0132454A1 (fr) 1985-02-13

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EP83107478A Withdrawn EP0132454A1 (fr) 1983-07-29 1983-07-29 Méthode et dispositif pour l'affichage typographique à haute définition de texte

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0411739A2 (fr) * 1989-08-01 1991-02-06 Adobe Systems Inc. Méthode d'édition des tableaux pour les éléments d'image sur écran des caractères à grandeurs minimes
EP0428356A2 (fr) * 1989-11-13 1991-05-22 Canon Kabushiki Kaisha Méthode et dispositif de génération de configurations

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2005500A (en) * 1977-09-26 1979-04-19 Burroughs Corp A video synthesizer for a digital video display system employing a plurality of gray-scale levels
US4158838A (en) * 1976-04-08 1979-06-19 Hughes Aircraft Company In-raster symbol smoothing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158838A (en) * 1976-04-08 1979-06-19 Hughes Aircraft Company In-raster symbol smoothing system
GB2005500A (en) * 1977-09-26 1979-04-19 Burroughs Corp A video synthesizer for a digital video display system employing a plurality of gray-scale levels

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PROCEEDINGS OF THE IFIP CONGRESS 80, INFORMATION PROCESSING 80, 6.-9. Oktober 1980, North-Holland Publishing Company, Tokyo (JP) *
THE COMPUTER JOURNAL, Heft 25, Nr. 1, Februar 1982, Londen (GB) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0411739A2 (fr) * 1989-08-01 1991-02-06 Adobe Systems Inc. Méthode d'édition des tableaux pour les éléments d'image sur écran des caractères à grandeurs minimes
EP0411739A3 (en) * 1989-08-01 1991-11-13 Adobe Systems Inc. Method for editing character bitmaps at small sizes
EP0428356A2 (fr) * 1989-11-13 1991-05-22 Canon Kabushiki Kaisha Méthode et dispositif de génération de configurations
EP0428356A3 (en) * 1989-11-13 1992-09-30 Canon Kabushiki Kaisha Pattern generation method and pattern generation apparatus

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Inventor name: KAROW, PETER