EP0127984B1 - Dekodierungsanordnung für fehlerkorrigierende Kodes - Google Patents

Dekodierungsanordnung für fehlerkorrigierende Kodes Download PDF

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EP0127984B1
EP0127984B1 EP84303496A EP84303496A EP0127984B1 EP 0127984 B1 EP0127984 B1 EP 0127984B1 EP 84303496 A EP84303496 A EP 84303496A EP 84303496 A EP84303496 A EP 84303496A EP 0127984 B1 EP0127984 B1 EP 0127984B1
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Prior art keywords
state
decision
time slot
code
metric
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EP0127984A3 (en
EP0127984A2 (de
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John Ashley Gordon
Graham Kenneth King
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British Telecommunications PLC
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British Telecommunications PLC
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end

Definitions

  • This invention relates to the design of electronic apparatus for the transmission of digital information, and specifically to the design of apparatus for decoding error-correcting codes.
  • a channel is said to be NOISY when signals received through it are likely to be a corrupted version of those actually sent over it.
  • DATA Messages to be protected against the corruption introduced by a noisy channel
  • CODEC convolutional error correcting code
  • a codec consists of two devices known as a CODER and a DECODER. Data to be protected against noise is fed into the coder which in turn generates a new signal called the CODE which is actually transmitted over the noisy channel.
  • the signal received through the noisy channel is a corrupted version of the code and it is the purpose of the decoder, using only knowledge of the corrupted, received code, to try to find a good approximation to the data which was originally fed into the coder.
  • the present invention is an improvement to the circuitry of decoders for convolutional error-correcting codes, and specifically to a type of decoder known as a Viterbi decoder.
  • the particular improvement to such decoders to which this invention relates is the handling of the PATH-HISTORY MANAGEMENT PROBLEM which will be described shortly.
  • figure 1 which shows a coder for a simple convolutional code
  • binary data is fed one bit at a time into the shift register 1 which in this example consists of two stages.
  • the number of stages is called K so that K is two in figure 1.
  • K is called the CONSTRAINT LENGTH of the code.
  • Modulo-2 gates 2 and 3 are used to form two modulo-2 sums of certain subsets of the data in the shift register. These two modulo-2 sums are the two code symbols to be transmitted. It is convenient to regard the contents of the shift register as the STATE of the coder. Thus in figure 1 there are four possible states, namely 00, 01, 10 and 11. In general there are 2 K (2 raised to the power K) states in a code of constraint length K.
  • the two code symbols sent to the noisy channel for each data bit entered into the coder depend:
  • Table 1 illustrates the relationship between present state, data in, code sent and the next state for the coder of figure 1.
  • the state of the coder is just the last K data bits that have been entered into to the coder.
  • the coder starts in state 00 and that the data sequence 1011010 is presented to it.
  • the chain of events is illustrated in table 2.
  • the code sequence transmitted is 11-10-00-01-01-00-10... which has twice as many symbols as the corresponding data 1011010... and this code is called accordingly a RATE 1/2 code.
  • the received sequence is likely to contain errors, for example it might consist of the sequence 11-10-00-11-01-00-10... which:
  • the decoder has the task of finding the data sequence corresponding to the code sequence which was most probably sent.
  • VA VITERBI ALBORITHM
  • Possible data sequences and/or the corresponding code are commonly called PATHS or PATH HISTORIES.
  • Each data symbol and/or its associated code symbols is called a BRANCH.
  • the best path leading to any particular state is in fact just that data sequence whose corresponding codeword has the highest metric since this path has the most correct branches, in other words the least number of errors.
  • Each state in the code has two possible PREDECESSOR states called its 0-predecessor and its 1- predecessor. For example state 01 and 00 and 10 as its 0-predecessor and 1-predecessor states respectively, since either of these states could give rise to state 01 if a data bit of 0 resp. 1 is entered.
  • time has advanced by one TIMESLOT.
  • the current time at which a symbol pair is being received is timeslot T and will use timeslot T-1 to denote the moment when the previous symbol pair was received and so on.
  • the timeslot T+ 1 will denote the moment when the next pair of symbols is to be received.
  • the decoder updates this stored information as follows.
  • the decoder will choose MO for the new metric for state S and will choose for the new, best path terminating in state S the previously best path terminating in P0, plus the extra branch 0. Conversely, if M1 is greater than MO the decoder will choose M1 for the new metric for state S and will choose for the new, best path terminating in state S the previously best path terminating in P1, plus the extra branch 1.
  • the decoder can update its stored information each timeslot.
  • the decoder at all times knows the best path which terminates in each state. Now it turns out that if the best paths for each of the states are compared, they usually differ from each other in only the last few symbols. Symbols in the best paths associated with times greater than L branches earlier, where L is about 10 x K are usually the same for all states.
  • the decoder thus can choose any state S and "look back" along the best path terminating in state S and send out as a decoder digit, any branch (i.e. data bit) a given fixed number L of branches earlier, i.e. a data bit entered at time T-L.
  • L is the history segment length of between 3 x K and 25 x K mentioned above.
  • the decoder does not store path history segments longer than L bits since once it has decoded a bit (i.e. retrieved it from the path history segment L branches earlier) this information is no longer needed by the decoder.
  • the larger the value of L the more likely are the best paths for all states to be identical at timeslot T-L. Thus the longer are the stored path history segments the better is the performance of the decoder, although as L is increased the performance asymptotically levels out.
  • This invention is an improvement to decoders which greatly simplifies the problem of management of the stored paths.
  • every time a new set of received signal symbols is acquired by the decoder it must, for every state make a copy of the best path terminating in either its 0-predecessor ot its 1-predecessor and append either a 0 or a 1 to this path.
  • K 6
  • the amount of information which must be moved around in the decoder presents a design problem. There is thus a conflict between the desire to make the value of L large to improve the performance of the decoder, and the difficulty which this produces of moving around very large amounts of information in a small time. This difficulty will here be called the PATH-HISTORY MANAGEMENT PROBLEM.
  • the purpose of the present invention is to reduce this difficulty.
  • the decoder instead of storing, for each state S, the best path terminating at S, stores instead, the decisions which it has made for that state, represented by Os and 1s. These decisions are never copied from one state to another as is done in conventional decoders described above. Instead only a 0 or a 1 is appended to the list of decisions for each state in each timeslot. The need to move large amounts of digits does not arise.
  • the best path terminating in state S is determined from a stored set of decisions for the states. This we will do in two parts. Firstly we show that the best path can be recovered by a search, and secondly we show that this search can be carried out very economically.
  • the decoder examines the last decision (i.e. the decision made at time T) stored for state S. If this is a 0 then the decoder continues the search by examining the decisions for timeslot T-1 of the 0-predecessor PO(S). Otherwise it continues the search by examining the decisions for timeslot T-1 for the 1-predecessor P1(S). Suppose for example, that the decision was a 0, then the decoder examines the decision stored for state PO(S) at time T-1. If this decision is a 0 the decoder continues the search with PO(PO(SS)) at time T-2, otherwise it continues the search with state P1 (PO(S)) at time T-2. The decoder continues in this way examining earlier and earlier timeslots.
  • the decoder can recover the best path terminating in state S by such a continued search, and by searching to whatever depth it requires the decoder can recover as many branches in the best path as it requires.
  • the decoder does not need to search through decision space each and every time it needs a branch symbol to send out as decoded data. Instead it is more efficient to carry out such a search only every M timeslots, where M is an integer greater than one, and then it searches back L branches to recover not just one, but M bits from this best path at one search. These M bits can then be saved temporarily and output from the decoder one per timeslot when required. In this way, since searches do not now need to be undertaken very often, the decoder can, with little effort, afford to carry out very long searches with corresponding improvement in performance of the decoder.
  • K 2 is lower than used in commercial practice but it involves only four legitimate states which is convenient for description. It is emphasised that, although there are many paths, every legitimate path ends in one or other of the four legitimate states.
  • each bit is represented by a signal taking one of two frequencies (i.e. 2-FSK) which signal demodulates to a voltage taking one of two values; it is convenient to choose the scale and origin so that these two values are +1 and -1.
  • 2-FSK frequency shifting keying
  • the demodulator would only ever give values of +1 or -1, i.e. the "correct" value to conform with the transmitter.
  • the Viterbi method is designed for operation when conditions are not perfect when, e.g. because of interference, values between +1 and -1 occur. Under adverse condition values close to, and even on the wrong side of, zero may occur. It is the purpose of the decoding to avoid confusion except under extreme adversity.
  • the receiver uses the matrix T to calculate a metric for each legal signal.
  • the four metrics which it calculates are:-
  • the receiver includes metric storage means which stores four metrics, i.e. one for each of these end states, and these metrics are updated in each time slot.
  • the receiver computes all the expressions on the right hand sides and selects the higher alternative in each case.
  • the selection determines both an updated metric and a path fit for each state.
  • the selected value is the updated metric and, when the full set of values has been determined, the selected values are transferred each to its appropriate location in the metric storage means.
  • the selection decides the path followed for each legitimate end state, i.e. it designs a predessor to each state. In the case of a 1/2-rate system there is always a choice of two predecessors and, therefore a single bit is sufficient to define the decision. If the selection is taken from the column headed "0-predecessor" the decision bit is "0". In the alternate case the decision bit is "1".
  • the metrics are retained only into the next time slot where they are updated (and used to generate a new set of four decision bits).
  • the decision bits are retained for 16 time slots so that by using these decision bits a path can be traced for 16 steps. This keeps storage demand low, i.e. 4 locations for metrics, 64 locations for decision bits (i.e. 16 sets each of 4 bits) plus working storage for updating.
  • bits are retained in a decision store and this decision store is accessed using as addresses
  • This retrograde step generates from the decision storage using a single bit of the path. Successively retrograde stages generate successively earlier bits of the path.
  • the oldest sections of the path constitutes the output from the receiver.
  • Table X shows an arbitrary state for the decision-store (but only 6 time slots, designated A-F, are provided to save space). Time slot A is the most recent with slots B-F running in retrograde time sequence.
  • Table X can be used for a retrograde trace initiated at any of the four possible end states.
  • Table Y(00) shows a trace initiated from state (00).
  • Table Y(00) was constructed as follows. State 00 was selected for initiation in time slot A. Using “00" and “A” as addresses and accessing Table X retrives path bit "1" and "1" is entered in Table Y(00). The 1- predecessor of state 00 is state 10 which, as is shown in line B of Table Y(00), is used to initiate the second step. Table Y(00) is built up line by line as indicated. The column headed "Path Bit” constitutes the output of the receiver. Since the output is required in chronological sequence and Table Y(00) is retrograde, the output is obtained by reading up the column. (It should be noted that the next "state” is obtained from the current state by concatenating the decision bit at the left and excising the right bit. A shift register can be used for this purpose.)
  • Table Y(10) is similar to Table Y(00) but initiated from state (10).
  • Table X indicates the organisation suitable for the decision-bit storage means. That is it requires an area for each time slot and each area must provide one-bit capacity for each state.
  • the time slot areas are operated in a cyclic time sequence with a pointer to define the starting and end points of the cycle.” Each new set of four path-bits overwrites the oldest area.
  • the pointer is set to define the oldest area and the overwriting always occurs in the area defined by the pointer. Immediately after overwriting the pointer defines the newest area (and therefore the starting point for a trace). Adding one to the pointer (and resetting to zero if needed) resets it to the oldest area. It is emphasised that the stored decision-bits are never moved.
  • the system is still 1/2-rate so that there are still 4 legitimate signals in each time slot.
  • This feature is related to the 1/2-rate; the path length is not relevant to this feature.
  • the decoder in this example will store decisions in a Random Access Memory (RAM) containing 2048 eight-bit bytes.
  • RAM Random Access Memory
  • Such a RAM has 11 address bits and 8 data bits.
  • Circular addressing will be used for timeslots.
  • a counter capable of counting from 0 to 255 will be used to address the current timeslot T.
  • a timeslot t timelots earlier is associated with count T-t modulo 256. Timeslots older Than T-255 will never be needed and will have their data overwritten.
  • a convenient way to store the decisions is to wait until (for example) 8 decisions are available, saving them temporarily in a serial-to-parallel shift register, and then to write the set of 8 decisions simultaneously into a single RAM address.
  • 8 occasions when the need arises to write decisions to RAM. These occasions will be called BREAKS. This terminology neither implies nor excludes any temporal pause.
  • FIG. 2 A simple method of searching through decision space is illustrated in figure 2.
  • six parallel outputs 11 from a six-bit shift register 10 connect to six of the fourteen address terminals of a memory system 12.
  • the remaining eight address terminals 13 for the memory system are connected to a backward timeslot counter 13.
  • the input terminal 14 to the shift register 10 is taken from the single output terminal of the memory system.
  • FIG 3 A simple method of implementing the memory system using a memory device with 8 data bits is illustrated in figure 3.
  • three parallel outputs 24 from a six-bit shift register 20 are connected to select the output from a eight-to-one multiplexer 21 which recovers a particular bit 25, associated with a decision regarding a particular state, from a block of eight decisions 26 stored in an eight-bit byte.
  • This multiplexer is in turn connected to the data output from the RAM 22.
  • the RAM is addressed by eight outputs 27 from a backward timeslot counter 23, and from three outputs 28 from the shift register 20.
  • the shift register contains the number S and that the backward timeslot counter contains the number T.
  • the input 24 to the shift register from the RAM is precisely the decision which was made regarding the predecessor to state S at timeslot T.
  • the shift register is clocked and the backward timeslot counter is decremented.
  • a convenient moment to carry out a search is during a break as defined above.
  • a backward search of one timeslot i.e. one decision bit on the best path
  • a lookback of 8 decisions will be achieved.
  • a lookback of 128 timeslots can be achieved.
  • the last 16 decisions found by this search are then saved, for example in a 16 bit shift register. These are output, one per timeslot during the next 16 timesiots, as outputs from the decoder.

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Claims (12)

1. Verfahren zum Wiedererlangen von Daten von konvolutional kodierten Signalen, welches Verfahren aufweist:
(I) Erzeugen eines Entscheidungskodes für jeden Endzustand in jedem Zeitschlitz, worin jeder dieser Entscheidungskodes einen Schritt eines Rückwärtspfades darstellt, wobei der Schritt einen Endzustand in einem vorigen Zeitschlitz definiert;
(11) Speichern aller der Entscheidungskodes in Entscheidungspeichereinrichtungen, wobei jeder der Kodes in einer Stelle gespeichert wird, die durch den Kodeendzustand und den Zeitschlitz adressierbar ist;
(111) Erzeugen eines Pfades durch schrittweise Rückwärtssuche durch die gespeicherten Entscheidungskodes, worin jeder Schritt aufweist das Zugreifen auf die Entscheidungsspeichereinrichtungen, wobei als Adressen die Identität eines Zeitschlitzes und eines Endzustandes in dem Zeitschlitz verwendet werden, um einen Entscheidungskode wiederzuerlangen;
(IV) Erzeugen der Identität des Vorgängerendzustandes von dem wiedererlangten Kode und der Adresse, die verwendet wurde um es wiederzuerlangen, und ebenfalls Erzeugen der Identität des vorangehenden Zeitschlitzes, wobei Wiederholungen dieses Schrittes von jedem Zeitschlitz zu seinem vorangehenden Zeitschlitz den Pfad erzeugt; und
(V) Ausgeben des Endes dieses Pfades als die wiedererlangten Daten.
2. Verfahren nach Anspruch 1, worin der Empfänger:
(a) ein Maß für jeden Endzustand speichert und
(b) jedes Maß für jeden Zeitschlitz in Übereinstimmung mit in diesem Zeitschlitz empfangenen Daten aktualisiert, worin das Aktualisieren aufweist
(b)(i) Zugreifen auf die Maß-Speichereinrichtungen, die eine Speicherstelle für jedes Endzustandsmaß mit einer Vielzahl von Adressen für jeden Endzustand liefern, wobei diese Adressen die Identitäten von allen legitimen Vorgängerzuständen von jedem Zustand bilden, wodurch eine Vielzahl von Vorgängermaßen wiedererlangt wird;
- (b)(ii) Addieren zu jedem wiedererlangten Maß ein Signalmaß, das die Korrelation zwischen dem empfangenen Signal und dem legitimen Signal mißt, das der Übertragung von dem Vorgängerzustand zu dem Zustand entspricht, wobei eine Vielzahl, falls möglich, Maße für jeden Zustand erzeugt wird; und
(b)(iii) Auswählen des höchsten der möglichen Maße als das auf den neuesten Stand gebrachte Maß für den Endzustand und den Zustand, von dem es abgeleitet wurde als dem festgelegten Vorgängerzustand;

wobei Durchführen der Schritte (b)(i), (b)(ii) und (b)(iii) für jeden Endzustand ein aktualisiertes Endmaß für jeden Zustand erzeugt und der Entscheidungskode von dem festgelegten Vorgängerzustand abgeleitet wird.
3. Verfahren nach Anspruch 2, worin jeder Entscheidungskode aus einem einzigen Bit besteht, der den Wert "0" annimmt, wenn der festgelegte Vorgänger der 0-Vorgänger ist und den Wert "1", wenn der festgelegte Vorgänger der 1-Vorgänger ist.
4. Verfahren nach einem der vorhergehenden Ansprüche, worin die Entscheidungskodes in einem zyklischen Speicher gespeichert werden und die laufenden Kodes die ältesten Kodes überschreiben und ein Zeiger aufrechterhalten wird, um Anfang und Ende der Folge zu definieren.
5. Verfahren nach einem der vorhergehenden Ansprüche, worin die Zwangslänge 6 ist mit 64 Endzuständen und die Rückwärtssuche aus 32 bis 2048 Schritten besteht.
6. Verfahren nach einem der vorhergehenden Ansprüche von Anspruch 1, worin Punkt (V) das Ausgeben von mehr als einem Bit als die wiedererlangten Daten aufweist.
7. Dekodierer, der geeignet ist, ein Verfahren gemäß Anspruch 1 durchzuführen, um einen Ausgang von konvolutional kodierten Signalen wiederzugewinnen, welcher Dekodierer aufweist:
(A) einen Entscheidungskodegenerator zum Erzeugen eines Entscheidungskodes für jeden Endzustand in jedem Zwitschlitz;
(B) eine Entscheidungsspeichereinrichtung, die Speicherstellen liefert, die adressierbar sind durch die Identität von Zeitschlitz und Endzustand für Pfadentscheidungskodes, wobei diese Kodespeichereinrichtung wirksam verbunden ist mit dem Generator, um jeden Kode in der Stelle zu speichern, die durch den Kodeendzustand und den laufenden Zeitschlitz adressiert ist;
(C) ein erstes Adressenregister, das wirksam verbunden ist mit der Entscheidungsspeichereinrichtung, wobei das erste Register geeignet ist, eine Zeitschlitzidentität als Adresse zurüchz.uhalten;
(D) ein zweites Adressenregister, das wirksam mit der Entscheidungsspeichereinrichtung verbunden ist, wobei das zweite Register 10 geeignet, um einen Zustand als Adresse zurückzuhalten;
(E) Einrichtungen zum Aktualisieren des Inhalts des ersten Adressenregisters auf die Identität des vorangehenden Zeitschlitzes; und
(F) Einrichtungen zum Aktualisieren des zweiten Adressenregisters auf den Zustand, der durch den wiedererlangten Entscheidungskode und den Inhalt des zweiten Registers definiert ist.
8. Dekodierer nach Anspruch 7, worin das zweite Adressenregister 10 ein Schieberegister ist, das verbunden ist, um als Eingang den von der Entscheidungsspeichereinrichtung wiedererlangten Kode zu empfangen.
9. Dekodierer nach Anspruch 7 oder Anspruch 8, der ebenfalls aufweist:
(G) Maßspeichereinrichtungen, die eine Speicherstelle für ein Maß für jeden Endzustand aufweisen;
(H) Korrelierungseinrichtungen, die geeignet sind, Signalmaße zu erzeugen, die die Korrelation zwischen einem empfangenen Signal und einem legitimen Signal messen;
(K) Einrichtungen zum Aktualisieren, die wirksam mit den Korrelierungseinrichtungen und den Maßspeichereinrichtungen verbunden sind, wobei die Aktualisierungseinrichtungen geeignet sind, um die gespeicherten Maße in Ubereinstimmung mit den Signalmaßen zu aktualisieren, wobei die Aktualisierungseinrichtung aufweisen:
(K)(1) Einrichtungen zum Zugreifen auf die Maßspeichereinrichtungen mit Adressen, die die Identitäten von allen legitimen Vorgängerzuständen eines jeden Endzustandes bilden, um die Vorgängermaße wiederzuerlangen;
(K)(11) einen Addierer zum Addieren des Signalmaßes, das dem Übergang von dem Vorgängerzustand zu dem Endzustand entspricht, zu jedem wiedererlangten Maß;
(K)(III) Auswahleinrichtungen zum Auswählen der höchsten Summe und ihres Vorgängerzustandes, die jedem Endzustand entspricht;
(K)(IV) Einrichtungen zu Übertragen dieser höchsten Summe in die Speicherstelle der Maßspeichereinrichtungen, welche Stelle durch den Endzustand adressiert wird; und
(L) Einrichtungen zum Ableiten des Pfadentscheidungskodes von dem in Schritt (K)(III) ausgewählten Vorgänger.
10. Verfahren zum Wiedererlangen von Daten von konvolutional kodierten Signalen, welches Verfahren aufweist:
(I) Erzeugen eines Entscheidungskodes für jeden Endzustand in jedem Zeitschlitz;
(11) Speichern aller dieser Entscheidungskodes in Entscheidungsspeichereinrichtungen, wobei jeder der Kodes in einer Stelle gespeichert ist, die durch den Kodeendzustand und Zeitschlitz adressierbar ist;
(111) Wiedererlangen eines Pfads von den Entscheidungsspeichereinrichtungen, worin der Pfad erzeugt wird durch schrittweise Rückwärtssuche durch die gespeicherten Entscheidungskodes, worin jeder Schritt aufweist das Zugreifen auf die Entscheidungsspeichereinrichtungen, wobei als Adresse die Identität eines Zeitschlitzes und ein Zustand in dem Zeitschlitz verwendet wird, um einen Entscheidungskode wiederzuerlangen, der einen Zustand in dem vorangehenden Zeitschlitz definiert, wobei Wiederholung dieses Schrittes von jedem Zeitschlitz zu seinem vorhergehenden Zeitschlitz den Pfad erzeugt;
(IV) Ausgeben von M-Bits, die das Ende des Pfades sind, als wiedererlangte Daten, und Beginnen einer Rückwärtssuche wie in (111) spezifiziert für alle M-Zeitschlitze, worin M eine ganze Zahl >1 ist.
11. Verfahren nach Anspruche 10, worin M eine ganze Zahl im Bereich von 4 bis 16 ist.
12. Verfahren nach Anspruch 11, worin M = 16.
EP84303496A 1983-06-03 1984-05-23 Dekodierungsanordnung für fehlerkorrigierende Kodes Expired EP0127984B1 (de)

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GB838315363A GB8315363D0 (en) 1983-06-03 1983-06-03 Decoding errorcorrecting codes
GB8315363 1983-06-03

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EP0127984A2 EP0127984A2 (de) 1984-12-12
EP0127984A3 EP0127984A3 (en) 1985-01-09
EP0127984B1 true EP0127984B1 (de) 1987-04-01

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JPS60173930A (ja) * 1984-02-20 1985-09-07 Fujitsu Ltd パイプライン処理ビタビ復号器
JPS61210435A (ja) * 1985-03-14 1986-09-18 Nec Corp ビタビ最▲ゆう▼推定装置
GB8507903D0 (en) * 1985-03-26 1985-05-01 Tomlinson M Noise-reduction signal processing arrangement
GB2182529A (en) * 1985-10-30 1987-05-13 Philips Electronic Associated Digital communication of analogue signals
JPS62114334A (ja) * 1985-11-14 1987-05-26 Fujitsu Ltd シ−ケンシヤル復号器
DE3600905A1 (de) * 1986-01-15 1987-07-16 Ant Nachrichtentech Verfahren zum dekodieren von binaersignalen sowie viterbi-dekoder und anwendungen
CA1260143A (en) * 1986-02-24 1989-09-26 Atsushi Yamashita Path trace viterbi decoder
GB8609711D0 (en) * 1986-04-21 1986-05-29 Clark A P Channel estimation & detection
JPS6312676A (ja) * 1986-07-03 1988-01-20 Sakura Color Prod Corp 水性インキ組成物
US4748626A (en) * 1987-01-28 1988-05-31 Racal Data Communications Inc. Viterbi decoder with reduced number of data move operations
US4968985A (en) * 1988-06-06 1990-11-06 Digital Equipment Corporation Data demodulation system
US4979175A (en) * 1988-07-05 1990-12-18 Motorola, Inc. State metric memory arrangement for a viterbi decoder
JP2531533B2 (ja) * 1988-08-25 1996-09-04 富士通株式会社 逐次復号器
US5068859A (en) * 1989-06-19 1991-11-26 California Institute Of Technology Large constraint length high speed viterbi decoder based on a modular hierarchial decomposition of the deBruijn graph
JP2795935B2 (ja) * 1989-11-24 1998-09-10 三菱電機株式会社 最尤系列推定装置
DE4038251A1 (de) * 1990-11-30 1992-06-04 Philips Patentverwaltung Entzerrer fuer ein digitales uebertragungssystem
US5343500A (en) * 1991-09-03 1994-08-30 At&T Bell Laboratories Non-linear encoder and decoder for information transmission through non-linear channels
US5491705A (en) * 1992-06-18 1996-02-13 The United States Of America As Represented By The Secretary Of The Air Force De bruijn graph based VLSI viterbi decoder
US5490178A (en) * 1993-11-16 1996-02-06 At&T Corp. Power and time saving initial tracebacks
EP0656712A1 (de) * 1993-11-16 1995-06-07 AT&T Corp. Viterbi-Entzerrer mit "Traceback" variabler länge
US5465275A (en) * 1993-11-16 1995-11-07 At&T Ipm Corp. Efficient utilization of present state/next state registers
US5533065A (en) * 1993-12-28 1996-07-02 At&T Corp. Decreasing length tracebacks
US5619514A (en) * 1994-12-29 1997-04-08 Lucent Technologies Inc. In-place present state/next state registers
US6473010B1 (en) * 2000-04-04 2002-10-29 Marvell International, Ltd. Method and apparatus for determining error correction code failure rate for iterative decoding algorithms
JP6957392B2 (ja) * 2018-03-15 2021-11-02 キオクシア株式会社 メモリシステム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0052463A1 (de) * 1980-11-14 1982-05-26 Plessey Overseas Limited Übertragungssystem mit Konvolutionalkode und weicher Entscheidung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240156A (en) * 1979-03-29 1980-12-16 Doland George D Concatenated error correcting system
NL7907141A (nl) * 1979-09-26 1981-03-30 Philips Nv Inrichting voor het behandelen van een informatiestroom met behulp van een foutenkorrigerende konvolutiekode en inrichting voor het detekteren van een daarbij alsnog onherstelbare fout.
US4346473A (en) * 1980-02-26 1982-08-24 Harris Corporation Error correction coding method and apparatus for multilevel signaling

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0052463A1 (de) * 1980-11-14 1982-05-26 Plessey Overseas Limited Übertragungssystem mit Konvolutionalkode und weicher Entscheidung

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JPS6037834A (ja) 1985-02-27
US4630032A (en) 1986-12-16
DE3462982D1 (en) 1987-05-07
CA1221460A (en) 1987-05-05
EP0127984A3 (en) 1985-01-09
EP0127984A2 (de) 1984-12-12
JPH0453128B2 (de) 1992-08-25
GB8315363D0 (en) 1983-07-06
ATE26371T1 (de) 1987-04-15

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