EP0115737B1 - Matrix conversion system for dynamically redefinable character sets in a video system - Google Patents

Matrix conversion system for dynamically redefinable character sets in a video system Download PDF

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Publication number
EP0115737B1
EP0115737B1 EP83460006A EP83460006A EP0115737B1 EP 0115737 B1 EP0115737 B1 EP 0115737B1 EP 83460006 A EP83460006 A EP 83460006A EP 83460006 A EP83460006 A EP 83460006A EP 0115737 B1 EP0115737 B1 EP 0115737B1
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pixels
inputs
phase
outputs
circuit
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German (de)
French (fr)
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EP0115737A1 (en
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Alain André Leger
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Telediffusion de France ets Public de Diffusion
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Telediffusion de France ets Public de Diffusion
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G09G5/26—Generation of individual character patterns for modifying the character dimensions, e.g. double width, double height

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  • the present invention relates to a system for transcoding between elementary matrices at 12 ⁇ 10 points and at 8 ⁇ 10 points respectively in videography systems with dynamically redefinable matrices and alphabets.
  • Known matrix or graphical videography systems are, for example, the French Teletel and Antiope systems or the British Prestel and Ceefax systems.
  • the Canadian Telidon system is a system with alphageometric graphics which is not concerned with the present invention.
  • Dynamically redefinable matrix and alphabet videography systems are known. As an example, such a system is described in French patent 2,419,623.
  • a random access memory for character forms is associated with the usual read-only memories and can receive particular forms of characters which are commonly transmitted to it via the channel for transmitting videography information, these particular forms of characters supplementing the sets of forms already existing in the read-only memories.
  • DRCS systems Dynamically redefinable character set.
  • the elementary matrices comprise 8x10 points and, in the other, 12x10 points.
  • An object of the present invention is to provide a transcoding system which provides low distortions and which can be implemented by simple means which do not significantly increase the cost of the terminal.
  • the logical processing of a group of three initial pixels a, b, c produces a group of transformed pixels â, b, according to the following logical formulas:
  • the pixels 6 and â ', calculated in the second phase are defined either by the following two logical equations: either by the two equivalent logical equations (1 ') and (II') where - is replaced by +.
  • a conversion circuit operating according to the system of the invention and comprising an input of digital signals of matrix 12 ⁇ 10 connected to the input of a set of three upstream shift registers with twelve cells, mounted in series, the outputs of the first and second upstream registers being connected to the corresponding inputs of a first phase calculation circuit, a digital signal output of matrix 8 ⁇ 1 connected to the output of a set of three downstream registers with eight stages , connected in series, the outputs of the first phase calculation circuit being connected to the parallel inputs of the first downstream register, the parallel outputs of the second upstream register being connected to corresponding inputs of a second phase processing circuit, the parallel outputs the first and third upstream registers being connected by an inverter circuit to corresponding inputs of the second phase processing circuit, the parallel outputs, except the first and the last, of the third downstream register being connected to corresponding inputs of the second phase processing circuit, the outputs of the second phase processing circuit being connected to the parallel inputs, except the first and the last, of the second phase processing circuit, the outputs
  • Fig. 1 is a relatively simplified block diagram showing the entire 12/8 converter.
  • the input wires of the transcoding circuit of FIG. 1 include the wires 1, 2 and 3 corresponding respectively to the wires 85, 84 and 83 mentioned above, and the output wires 4, 5, and 6 connected to a random access memory of character 7, corresponding to 37.
  • Wire 3 is connected to the input of a shift register 73 which is intended to delay the character address by a time equivalent to the processing of the first three lines of the character.
  • the synchronization of the register 73 is carried out by the signal presented on the wire 5 coming from the control logic 12.
  • Wire 2 is connected to the input of a shift register 74 which is intended to delay each line address received by a processing time equivalent to the processing time of three character lines.
  • the synchronization of the register 74 is carried out by the signal presented on the wire 6 coming from the control logic 12.
  • Wire 1 is connected to the data input of a shift register 8, the serial output of which is connected to the data input of a shift register 9.
  • the serial output of shift register 9 is connected to l input of a shift register 10.
  • the three shift registers 8, 9 and 10 each have twelve stages and can therefore each store a matrix line. Their clock inputs are connected to the output il of a clock circuit 12.
  • the registers 8 to 10 can be circuits of the type sold under the reference DM 74195.
  • Register 8 has its parallel outputs "1", “2” and “3” connected to the corresponding inputs of a first logic processing circuit 13.1, its parallel outputs “4", “5" and “6” connected to the corresponding inputs of a second logic processing circuit 13.2, its outputs “7”, “8” and “9” connected to the corresponding inputs of a third logic processing circuit 13.3, and its parallel outputs "10", “11” and “ 12 “connected to the corresponding inputs of a fourth logic processing circuit 13.4.
  • the set of circuits 13.1, 13.2, 13.3 and 13.4, which are identical, forms a conversion circuit 13 which converts slices of three pixels into slices of two pixels.
  • the register 9 has its parallel outputs "1", “2” and “3” connected to corresponding inputs of the circuit 13.1, its parallel outputs "4", “5" and “6” connected to corresponding inputs of circuit 13.2, its parallel outputs "7”, “8” and “9” connected to corresponding inputs of circuit 13.3, and its parallel outputs "10”, “11” and “12” connected to corresponding inputs of circuit 13.4.
  • the circuit 13.1 has two outputs which are respectively connected to the parallel inputs "1" and "2" of an eight-stage shift register 14; circuit 13.2 has two outputs respectively connected to the inputs parallel "3" and "4" of the register 14, the circuit 13.3 has two outputs connected respectively to the parallel inputs "5" and "6" of the register 14; and the circuit 13.4 has two outputs respectively connected to the inputs "7" and "8" of the register 14.
  • the serial output of the register 14 is connected to the input of an eight-stage shift register 15.
  • the serial output of register 15 is connected to the serial input of another shift register 16 with eight stages, the output of which is connected to wire 4.
  • Register 8 also has its parallel outputs "1" to "3" connected respectively to the first inputs of three AND gates P1; its parallel outputs "4" to “6” connected respectively, on the one hand, to the first inputs of three AND gates Q1 and, on the other hand, to the first inputs of three AND gates P2; its three parallel outputs "7” to “9” connected respectively, on the one hand, to the first inputs of three AND gates Q2 and, on the other hand, to the first inputs of three AND gates P3; and, finally, its three parallel outputs "10” to "12” connected to the first inputs of three AND gates Q3.
  • the set of AND gates P1 to P3 and Q1 to Q3 form a switch 17.
  • the outputs of AND gates P1 and Q1 are respectively connected to the first inputs of six OR gates R1; the outputs of AND gates P2 and Q2 are respectively connected to the first inputs of six OR gates R2, and the outputs of AND gates P3 and Q3 are respectively connected to the first inputs of six OR gates R3.
  • the OR gates R1 to R3 form the connection circuit 18.
  • the outputs of the six OR gates R1 are connected to the corresponding inputs A1 to A6 of a logic processing circuit 19.1; the outputs of the six OR gates R2 are connected to the corresponding inputs A of a logic processing circuit 19.2, and the outputs of the six OR gates R3 are connected to the corresponding inputs A of a third logic processing circuit 19.3.
  • circuit 19.1 has two outputs which are respectively connected to the parallel inputs "2" and "3" of the register 15; circuit 19.2 has two outputs which are respectively connected to inputs "4" and "5" of register 15; and circuit 19.3 has two outputs which are respectively connected to inputs "6" and "7" of register 15:
  • circuit 19.1 has inputs B which are respectively connected to the parallel outputs "2", “3", "4" and "5" of the register 9; circuit 19.2 has inputs B which are respectively connected to parallel outputs "5", "6", "7" and "8" of register 9; and circuit 19.3 has inputs B which are respectively connected to outputs "8", "9", "10" and "11" of register 9.
  • the circuit 19.1 also has inputs C which are respectively connected to the parallel outputs "2" and "3" of the register 16; the circuit 19.2 has inputs C which are respectively connected to the parallel outputs "4" and "5" of the register 16; and the circuit 19.3 has inputs C which are respectively connected to the parallel outputs "6" and "7" of the register 16.
  • circuit 19.1 has an output D connected to the second inputs of the doors P1 and Q1; circuit 19.2 has an output D connected to the second inputs of AND gates P2 and Q2; and circuit 19.3 has an output D connected to the second inputs of AND gates P3 and 03.
  • the register 10 has its parallel outputs "1" to "3" connected respectively to the first inputs of three AND gates P'1; its parallel outputs "4" to “6” connected respectively, on the one hand, to the first inputs of three AND gates Q'1 and, on the other hand, to the first inputs of three AND gates P'2, its three parallel outputs "7” to “9” connected respectively, on the one hand, to the first inputs of three AND gates Q'2 and, on the other hand, to the first inputs of three AND gates P'3; and, finally, its three parallel outputs "10" to "12” connected to the first inputs of three AND gates Q3.
  • the set of AND gates P'1 to P'3 and Q'1 to Q'3 forming a switch 20.
  • AND gates P'1 and Q'1 are respectively connected to the second inputs of the six OR gates R1; the outputs of AND gates P'2 and Q'2 are respectively connected to the second inputs of the six OR gates R2, and the outputs of AND gates P'3 and Q'3 are respectively connected to the second inputs of the six OR R3 gates.
  • circuit 19.1 has an output E connected to the second inputs of the doors P'1 and Q'1; circuit 19.2 has an output E connected to the second inputs of AND gates P'2 and Q'2, and circuit 19.3 has an output E connected to second inputs of AND gates P'3 and Q'3.
  • FIG. 3a Before describing in detail the logic processing circuit 13.1, FIG. 4, and the logic processing circuit 19.1, FIG. 5, we will consider the diagrams of Figs. 3a and 3b.
  • FIG. 3a In the diagram of FIG. 3a, there is shown on the left, looking at the drawing, a portion of matrix 12 ⁇ 10 and, on the right, the transformed portion of matrix 8 ⁇ 10, after passing through the circuit 13.1.
  • This transformation will, in the following, be designated by first phase or phase 1. It will be noted that, in this phase, the twelve pixels of a line i are grouped into four groups of three pixels: a, b, c, a ', b ', c'; a ", b", etc. Each group of three pixels is transformed into a group of two pixels in the 8x10 matrix.
  • Each line of the 8x10 matrix comprises four groups of transformed pixels: â, b, â ', b'; â ", etc. More particularly, for the matrix 12x10, we represent, at line i, a first group of three pixels a, b, c, followed by a second group of three pixels a ', b', c ', and, at line (i ⁇ 1), the first corresponding group of three pixels a- i , b_ 1 , c- i , followed by the second corresponding group of three pixels a'- i , b'_ 1 , c '-. i It corresponds to them, in the 8x10 matrix, at row i, the first group of two pixels, b, followed by the second group of two pixels a', b '.
  • Fig. 4 shows in detail the logic diagram of the logic processing circuit 13.1 which calculates the pixels â and b as a function of the pixels, a, b, c, a_ 1 , b_ 1 and c- i , according to the following logic equations:
  • the digital references of the inputs are those of the data of the pixels to which they correspond.
  • Input a is connected, on the one hand, to the inverting input of an AND gate 21 and, on the other hand, to the input of an OR gate 22.
  • Input b is connected to the non-inverting input of AND gate 21.
  • Input c is connected, on the one hand, to the other inverting input of AND gate 21 and, on the other hand, to an input of an OR gate 23.
  • L input a_ 1 is connected, on the one hand, to a direct input of an AND gate 24 and, on the other hand, to an inverting input of an AND gate 25.
  • Input b_ 1 is connected, of on the one hand, to inverting inputs of doors 24 and 25 and, on the other hand, to direct inputs of AND doors 26 and 27.
  • the input c_ 1 is connected, on the one hand, to a direct input of the door AND 26 and, on the other hand, to an inverting input of the AND gate 27.
  • the output of AND gate 21 is connected to the first inputs of two AND gates 28 and 29.
  • the outputs of AND gates 25 and 26 are respectively connected to two inputs of an OR gate 30 with three inputs.
  • the outputs of AND gates 24 and 27 are respectively connected to two inputs of an OR gate 31 with three inputs.
  • the outputs of OR gates 30 and 31 are respectively connected to the second inputs of AND gates 29 and 28.
  • the outputs of AND gates 28 and 29 are respectively connected to the second inputs of OR gates 22 and 23.
  • the third inputs of OR gates 30 and 31 are connected to the activation input 32.
  • the outputs of the OR gates 22 and 23 respectively deliver the pixels a and b which are transmitted by the output wires of 13.1 to the inputs "1" and "2" of the register 14 .
  • the circuit 13.2 calculates the pixels â 'and b' from the second groups of three pixels of the lines i and (i-1), etc.
  • FIG. 3b there is shown, on the left, a portion of 12 ⁇ 10 matrix and, on the right, the transformed portion of 8 ⁇ 10 matrix, after the first phase and the portion transformed after the second phase.
  • the second phase is useful for reducing the thicknesses of the lines at the borders between the groups of two pixels.
  • Fig. 3b we consider the observation window comprising, line i, the pixels c and a ', and, line (i-1), the pixels b_ 1 , c_ 1 , a'_ 1 , b'_ 1 .
  • the pixels of this window are used, in certain cases, which will be defined below, to possibly modify the pixels b and â 'resulting from the processing in circuits 13.1 and 13.2 to obtain the final pixels b * and a' * resulting processing in the circuit 19.1.
  • circuit 19.1 Processing in circuit 19.1 is only triggered for a configuration of pixels b, c, a ', b' equal to 0110..
  • circuit 19.1, Fig. 5 allows to take into account pixels of the line (i ⁇ 1 and possibly pixels of the line (i + 1), or of the line (i + 1 to define the transformed pixels b and â 'of line i
  • the transformed pixels b and â ' are those which have been calculated by the circuits 13.1 and 13.2.
  • the transformed pixels 6 and â ' are defined, either by the following two logical equations: and either by the two equivalent logical equations (1 ') and (II') where - is replaced by +.
  • the data inputs of circuit 19.1 are the six-wire input A used to receive the pixel data a_ 1 , b_ 1 , c- 1 , a'_ 1 , b'_ 1 , c'_ 1 , when the wire E is activated, or the pixel data a + ,, b +1 , c +1 , a ' +1 , b' +1 , c ' +1 , when the wire D is activated; four-wire input B for receiving data from pixels b, c, a ', b'; and the input C for receiving data from pixels b * +1 , â +1 .
  • an NI gate 33 has its direct inputs connected to inputs b and b 'and its inverting inputs to inputs c and a'. Gate 33 makes it possible to detect the configuration 0110, mentioned above, in line i.
  • An NI 34 door has its four direct inputs connected to wires b 1 , c 1 , a ' 1 and b 1 ,.
  • Gate 34 is used to detect case 1) or case 4), mentioned above.
  • An NI 35 door has its two direct inputs connected to wires b 1 and b ' 1 , and its inverting inputs to wires c 1 and a'.
  • Gate 35 is used to detect case 2) or case 5), mentioned above.
  • the outputs of doors 34 and 35 are respectively connected to the two inputs of an OR gate 30, the output of which is connected to an input of an AND gate 64.
  • the output of gate 34 is still connected to the input D of a flip-flop 37 which has a reset input R connected to the output of an OR gate 38 one input of which is connected to the control input 39 and the other input to the control input 40, an input S of set to a connected to the control input 41, an output Q connected to the output wire D and an output Q connected to the output wire E.
  • the circuit 19.1 further comprises two calculation circuits 42 and 43 respectively carrying out the two logic calculations mentioned above.
  • an ET 44 part has its two direct inputs connected to wires c 'and c 1 ; an AND gate 45 has three direct inputs connected to the wires a 1 , b 1 , c 1 and an inverting input connected to the wire c ' 1 ; an AND gate 46 has a direct input connected to wire c 1 and an inverting input connected to wire b 1 ; a door 47 has a direct input connected to the wire b 1 and an inverting input connected to the wire c 1 ; an AND gate 48 has a direct input connected to wire a ' 1 and three inverting inputs connected to wires b 1 , c 1 and a. Note that above we did not specify the sign of the index 1, because it is negative or positive depending on the state of flip-flop 37.
  • the outputs of AND gates 44 and 47 are connected to the two inputs of an OR gate 49.
  • the outputs of AND gates 45, 46 and 47 are connected to the three inputs of an OR gate 50.
  • the output of OR gate 49 is connected to the direct input of an AND gate 51 whose inverting inputs are connected to wires a ' 1 and b' 1 .
  • the output of the OR gate 50 is connected to a direct input of an AND gate 52, the other two direct inputs of which are connected to the inputs a ' 1 and b' 1 .
  • the outputs of AND gates 48, 51 and 52 are connected to three inputs of an OR gate 53.
  • an AND gate 54 has its two direct inputs connected to wires a and a '; an AND gate 55 has three direct inputs connected to wires a ' 1 , b' 1 , c ' 1 and an inverting input connected to wire a ,; an AND gate 56 has a direct input connected to wire b ' 1 and its inverting input connected to wire a',; an AND gate 57 has its direct input connected to wire a ' 1 and its inverting input connected to wire b' 1 ; and an AND gate 58 has a direct input connected to the wire c_, and three inverting inputs connected to the wires a ' 1 , b' 1 and c '.
  • the outputs of AND gates 54 and 56 are connected to the two inputs of an OR gate 59.
  • the outputs of AND gates 55, 56 and 57 are connected to the three inputs of an OR gate 60.
  • the output of OR gate 59 is connected to the direct input of an AND gate 61 whose inverting inputs are connected to wires b_ 1 and c_ 1 .
  • the output of the OR gate 60 is connected to a direct input of an AND gate 62, the other two direct inputs of which are connected to the wires b_ 1 and c_ 1 .
  • the outputs of AND gates 58, 61 and 62 are connected to three inputs of an OR gate 63.
  • OR gate 36 The output of the OR gate 36 is connected to an input of an AND gate 64, the other input of which is connected to the output Q of the flip-flop 37 and the output of which is connected to the first input of two OR gates 65 and 66
  • the OR gates each have an activation input which is connected to the output of gate NI 33.
  • the output of the NI gate 35 is also connected to an input of an AND gate 67, the other input of which is connected to the output Q of the flip-flop 37 and the output of which is connected to the first input of two AND gates 68 and 69.
  • the second inputs of doors 68 and 69 are respectively connected to the wires a '* +1 and b * +1 of input C and their outputs are respectively connected to the second inputs of doors OR 65 and 66.
  • the third inputs of doors 65 and 66 are respectively connected to the outputs of doors 53 and 63.
  • circuit 19.1 which is used to define the transformed pixels b and â 'of line i.
  • the circuit 19.1 operates whatever the state of the output of 33 which only serves to validate the calculations.
  • the time base or logic control 12 comprises a four-stage counter 121 receiving at C the bit clock signal which it also delivers at H. Furthermore its outputs QA, QB, QC and QD are respectively connected to the first two inputs inverters, to the third non-inverting input and to the fourth inverting input of an NI 122. gate The output of gate 122 and the output H of 121 are connected to the inputs of an AND gate 123 whose output is connected to the inputs clock registers 8, 9 and 10. In addition, the outputs QA, QB, QC and QD are respectively connected to the first non-inverting input and to the other three inverting inputs of an NI 124 door. The door output 124 and the output H and 121 are connected to the inputs of an AND gate 125 whose output is connected to the clock inputs of the registers 14, 15 and 16.
  • the outputs QD and H of 121 are also connected to the inputs of an AND gate 126 whose output is connected to the clock inputs of the registers 14 to 16.
  • the circuit 12 includes another counter 127 whose input C receives the bit clock signal and whose output H 'delivers clock signals.
  • the counter 127 has its QA, QB, QC and QD outputs respectively connected to the first inverting input and to the other three non-inverting inputs of an NI 128 gate, on the one hand, and to the first non-inverting input, to the second. inverting input and the other two non-inverting inputs of an NI 129 door.
  • gate 128 provides the signal at the input of gates 30 and 31 of circuits 13.1 to 13.4.
  • the outputs of gates 128 and 129 provide signals 40 and 41 in circuits 19.1 to 19.2.
  • Fig. 9 is the diagram of an 8x10 to 12x10 conversion circuit. It includes an eight-stage shift register 130 whose data input receives the bits of the line pixels of an 8 ⁇ 10 matrix. Its outputs "1" and “2" are respectively connected to the inputs of an OR gate 131. Furthermore, the circuit includes a twelve-stage shift register 132 which delivers the bits of the line pixels of a 12 ⁇ 10 matrix. The output "1" of 130 is connected to the parallel input "1" of 132, the output of the gate 131 is connected to the parallel input "2" of 132 and the output "2" of 130 is connected to the 'parallel input "3" of register 132. We then find the same structure three times for successively outputs "3" to "8” of 130 and inputs "4" to "12” of 132.

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Description

La présente invention concerne un système de transcodage entre matrices élémentaires à 12x10 points et à 8x10 points respectivement dans des systèmes de vidéographie à matrices et à alphabets dynamiquement redéfinissables.The present invention relates to a system for transcoding between elementary matrices at 12 × 10 points and at 8 × 10 points respectively in videography systems with dynamically redefinable matrices and alphabets.

Des systèmes de vidéographie à matrices ou à graphisme alphamosaïque connus sont, par exemple, les systèmes français Télétel et Antiope ou les systèmes britanniques Prestel et Ceefax. Par opposition, le système canadien Télidon est un système à graphisme alphagéométrique qui n'est pas concerné par la présente invention.Known matrix or graphical videography systems are, for example, the French Teletel and Antiope systems or the British Prestel and Ceefax systems. In contrast, the Canadian Telidon system is a system with alphageometric graphics which is not concerned with the present invention.

Des systèmes de vidéographie à matrices et à alphabets dynamiquement redéfinissables sont connus. A titre d'exemple, un tel système est décrit dans le brevet français 2 419 623. Dans le générateur de caractères des terminaux de ces systèmes, une mémoire vive de formes de caractères est associée aux mémoires mortes habituelles et peut recevoir des formes particulières de caractères qui lui sont couramment transmises par le canal de transmission des informations de vidéographie, ces formes particulières de caractères complétant les jeux de formes existant déjà dans les mémoires mortes. Dans la terminologie anglo-saxonne, de tels systèmes sont appelés systèmes DRCS (Dynamically redefinable character set). Il existe actuellement deux types de structures DRCS: dans l'une, les matrices élémentaires comportent 8x10 points et, dans l'autre, 12x10 points. D'une manière générale, en ce qui concerne les systèmes DRCS, on pourra se reporter à l'article de O. Lambert et autres, paru dans la revue IEEE Transactions on Consumer Electronics, Vol. CE 26, août 1980, pages 600 à 602, et intitulé ANTIOPE AND D.R.C.S.Dynamically redefinable matrix and alphabet videography systems are known. As an example, such a system is described in French patent 2,419,623. In the character generator of the terminals of these systems, a random access memory for character forms is associated with the usual read-only memories and can receive particular forms of characters which are commonly transmitted to it via the channel for transmitting videography information, these particular forms of characters supplementing the sets of forms already existing in the read-only memories. In Anglo-Saxon terminology, such systems are called DRCS systems (Dynamically redefinable character set). There are currently two types of DRCS structures: in one, the elementary matrices comprise 8x10 points and, in the other, 12x10 points. In general, with regard to DRCS systems, reference may be made to the article by O. Lambert et al., Which appeared in the journal IEEE Transactions on Consumer Electronics, Vol. CE 26, August 1980, pages 600 to 602, and entitled ANTIOPE AND D.R.C.S.

Des efforts sont actuellement faits pour définir un procédé permettant de rendre compatibles les deux structures DRCS, avec un minimum de distorsions. A la réunion du CEPT pour la vidéographie, tenue du 25 au 27 mars 1981 à Darmstadt, un projet de transcodage d'origine suédoise, intitulé "Common coding schemes for 8 and 12 dot DRCS" a été proposé. Son utilisation semble entraîner des déformations importantes des formes originelles.Efforts are currently being made to define a process making it possible to make the two DRCS structures compatible, with a minimum of distortions. At the CEPT meeting for videography, held from 25 to 27 March 1981 in Darmstadt, a transcoding project of Swedish origin, entitled "Common coding schemes for 8 and 12 dot DRCS" was proposed. Its use seems to cause significant distortions of the original forms.

Un objet de la présente invention consiste à prévoir un système de transcodage qui apporte de faibles distorsions et qui peut être mis en oeuvre par des moyens simples ne grévant pas sensiblement le coût du terminal.An object of the present invention is to provide a transcoding system which provides low distortions and which can be implemented by simple means which do not significantly increase the cost of the terminal.

Suivant une caractéristique de la présente invention, il est prévu un système de transcodage d'une matrice 12x10 points en matrice 8x10 points, dans lequel la conversion comporte deux phases, une première phase dans laquelle les pixels de chaque ligne sont groupés par trois dans l'ordre naturel et dans laquelle chaque groupe de trois pixels est traité logiquement pour obtenir un groupe de deux pixels transformés, une seconde phase dans laquelle la configuration de l'ensemble initial des quatre pixels qui est à cheval sur la limite entre deux groupes est examiné de manière que, quand cet ensemble est différent de 0110, l'ensemble transformé formé des deux pixels transformés de la première phase, qui sont de part et d'autre de la limite, est conservé et que, dans le cas contraire, la configuration de l'ensemble initial correspondant de la ligne antérieure est examiné et:

  • -s'il est trouvé égal à 0110, les pixels de l'ensemble transformé sont remplacés par les pixels correspondants, définitivement transformés de la ligne précédente,
  • -s'il n'est ni égal à 0110, ni à 0000, les pixels de l'ensemble transformé sont replacés par des pixels calculés dans la seconde phase à partir des pixels initiaux, voisins de la ligne courante et de la ligne antérieure,
  • -s'il est trouvé égal à 0000, l'ensemble initial correspondant de la ligne postérieure est examiné et:
    • ―s'il est trouvé égal à 0000 ou à 0110, les pixels de l'ensemble transformé sont remplacés par 1 et 1,
    • ―s'il est trouvé différent de 0000 et de 0110, les pixels de l'ensemble transformé sont remplacés par des pixels calculés dans la seconde phase.
According to a characteristic of the present invention, there is provided a system for transcoding from a 12 × 10 dot matrix to an 8 × 10 dot matrix, in which the conversion comprises two phases, a first phase in which the pixels of each line are grouped by three in the natural order and in which each group of three pixels is processed logically to obtain a group of two transformed pixels, a second phase in which the configuration of the initial set of four pixels which straddles the boundary between two groups is examined so that, when this set is different from 0110, the transformed set formed by the two transformed pixels of the first phase, which are on either side of the limit, is preserved and that, otherwise, the configuration of the corresponding initial set of the previous line is examined and:
  • -if it is found equal to 0110, the pixels of the transformed set are replaced by the corresponding pixels, definitively transformed from the previous line,
  • -if it is neither equal to 0110, nor to 0000, the pixels of the transformed set are replaced by pixels calculated in the second phase from the initial pixels, neighbors of the current line and of the previous line,
  • -if it is found equal to 0000, the corresponding initial set of the posterior line is examined and:
    • ― If it is found equal to 0000 or 0110, the pixels of the transformed set are replaced by 1 and 1,
    • ― If it is found to be different from 0000 and 0110, the pixels of the transformed set are replaced by pixels calculated in the second phase.

Suivant une autre caractéristique, dans la première phase, le traitement logique d'un groupe de trois pixels initiaux a, b, c, produit un groupe de pixels transformés â, b, suivant les formules logiques suivantes:

Figure imgb0001
According to another characteristic, in the first phase, the logical processing of a group of three initial pixels a, b, c, produces a group of transformed pixels â, b, according to the following logical formulas:
Figure imgb0001

Suivant une autre caractéristique, les pixels 6 et â', calculés dans la seconde phase, sont définis, soit par les deux équations logiques suivantes:

Figure imgb0002
Figure imgb0003
soit par les deux équations logiques équivalentes (1') et (II') où - est replacé par +.According to another characteristic, the pixels 6 and â ', calculated in the second phase, are defined either by the following two logical equations:
Figure imgb0002
Figure imgb0003
 either by the two equivalent logical equations (1 ') and (II') where - is replaced by +.

Suivant une autre caractéristique, il est prévu un circuit de conversion fonctionnant suivant le système de l'invention et comprenant une entrée de signaux numériques de matrice 12x10 reliée à l'entrée d'un jeu de trois registres amont à décalage à douze cellules, montés en série, les sorties des premier et second régistres amont étant reliées aux entrées correspondantes d'un circuit de calcul de première phase, une sortie de signal numérique de matrice 8x 1 reliée à la sortie d'un jeu de trois registres aval à huit étages, montés en série, les sorties du circuit de calcul de première phase étant reliées aux entrées parallèles du premier registre aval, les sorties parallèles du second registre amont étant reliées à des entrées correspondantes d'un circuit de traitement de seconde phase, les sorties parallèles du premier et du troisième registres amont étant reliées par un circuit inverseur à des entrées correspondantes du circuit de traitement de seconde phase, les sorties parallèles, sauf la première et la dernière, du troisième registre aval étant reliées à des entrées correspondantes du circuit de traitement de seconde phase, les sorties du circuit de traitement de seconde phase étant reliées aux entrées parallèles, sauf la première et la dernière, du second registre aval, et une base de temps commandant les fonctionnements des circuits de calcul de première phase et de traitement de seconde phase et l'avancement dans les registres.According to another characteristic, there is provided a conversion circuit operating according to the system of the invention and comprising an input of digital signals of matrix 12 × 10 connected to the input of a set of three upstream shift registers with twelve cells, mounted in series, the outputs of the first and second upstream registers being connected to the corresponding inputs of a first phase calculation circuit, a digital signal output of matrix 8 × 1 connected to the output of a set of three downstream registers with eight stages , connected in series, the outputs of the first phase calculation circuit being connected to the parallel inputs of the first downstream register, the parallel outputs of the second upstream register being connected to corresponding inputs of a second phase processing circuit, the parallel outputs the first and third upstream registers being connected by an inverter circuit to corresponding inputs of the second phase processing circuit, the parallel outputs, except the first and the last, of the third downstream register being connected to corresponding inputs of the second phase processing circuit, the outputs of the second phase processing circuit being connected to the parallel inputs, except the first and the last, of the second register downstream, and a time base controlling the operations of the first phase calculation and second phase processing circuits and the progress in the registers.

Les caractéristiques mentionnées ci-dessus, ainsi que d'autres, apparaîtront plus clairement à la lecture de la description suivante d'un exemple de réalisation, ladite description étant faite en relation avec les dessins joints, parmi lesquels:

  • la Fig. 1 est un bloc-diagramme schématique d'un circuit de conversion suivant l'invention,
  • les Figs. 2a à 2d, assemblées comme l'indique la Fig. 2, sont des bloc-diagrammes des différentes parties du circuit de la Fig. 1,
  • les Figs. 3a et 3b sont des diagrammes illustrant le fonctionnement du circuit des Figs. 1 et 2,
  • la Fig. 4 est le schéma du circuit de calcul de première phase,
  • la Fig. 5 est le schéma du circuit de traitement de seconde phase,
  • la Fig. 6 est un organigramme illustrant le fonctionnement du circuit de traitement de la Fig. 5,
  • la Fig. 7 représentent des formes d'onde des signaux de sortie de la base de temps, montrée aux Figs. 1 et 2,
  • la Fig. 8 est un exemple de conversion de matrice 12x10 en matrice 8x10, et
  • la Fig. 9 est un schéma de conversion de matrice 8x10 eh matrice 12x10.
The characteristics mentioned above, as well as others, will appear more clearly on reading the following description of an exemplary embodiment, said description being made in relation to the accompanying drawings, among which:
  • Fig. 1 is a schematic block diagram of a conversion circuit according to the invention,
  • Figs. 2a to 2d, assembled as shown in Fig. 2, are block diagrams of the various parts of the circuit of FIG. 1,
  • Figs. 3a and 3b are diagrams illustrating the operation of the circuit of Figs. 1 and 2,
  • Fig. 4 is the diagram of the first phase calculation circuit,
  • Fig. 5 is the diagram of the second phase processing circuit,
  • Fig. 6 is a flow diagram illustrating the operation of the processing circuit of FIG. 5,
  • Fig. 7 show waveforms of the time base output signals, shown in Figs. 1 and 2,
  • Fig. 8 is an example of converting from a 12 × 10 matrix to an 8 × 10 matrix, and
  • Fig. 9 is a 8x10 matrix conversion scheme to a 12x10 matrix.

On rappelle que pour écrire, la nouvelle forme d'un caractère dans une mémoire vive, il faut trois données: la première concerne l'adresse de la matrice unitaire dans la mémoire, la seconde l'adresse de la ligne dans la matrice et la troisième les bits constituant la ligne. Dans le brevet français 2 419 623, ces trois données sont transmises sur trois fil 83, 84 et 85, Fig. 7, vers la mémoire vive 37, les trois fils 83 à 85 constituant la liaison 80. Le circuit de transcodage, suivant l'invention, utilisé avec le système de télétexte du brevet 2 419 623, trouve sa place, monté en série dans la liaison 80.It is recalled that to write, the new form of a character in a random access memory, three data are needed: the first concerns the address of the unitary matrix in memory, the second the address of the line in the matrix and the third the bits constituting the line. In French patent 2,419,623, these three data are transmitted on three wires 83, 84 and 85, FIG. 7, to the RAM 37, the three wires 83 to 85 constituting the link 80. The transcoding circuit according to the invention, used with the teletext system of patent 2,419,623, finds its place, connected in series in the connection 80.

La Fig. 1 est un bloc-diagramme relativement simplifié montrant l'ensemble du convertisseur 12/8.Fig. 1 is a relatively simplified block diagram showing the entire 12/8 converter.

Les fils d'entrées du circuit de transcodage de la Fig. 1 comprennent les fils 1, 2 et 3 correspondant respectivement aux fils 85, 84 et 83 mentionnés plus haut, et les fils de sortie 4, 5, et 6 reliés à une mémoire vive de caractère 7, correspondant à 37.The input wires of the transcoding circuit of FIG. 1 include the wires 1, 2 and 3 corresponding respectively to the wires 85, 84 and 83 mentioned above, and the output wires 4, 5, and 6 connected to a random access memory of character 7, corresponding to 37.

Le fil 3 est relié à l'entrée d'un registre à décalage 73 qui est destiné à retarder l'adresse caractère d'un temps équivalent au traitement des trois premières lignes du caractère. La synchronisation du registre 73 est effectuée par le signal présenté sur le fil 5 provenant de la logique de commande 12.Wire 3 is connected to the input of a shift register 73 which is intended to delay the character address by a time equivalent to the processing of the first three lines of the character. The synchronization of the register 73 is carried out by the signal presented on the wire 5 coming from the control logic 12.

Le fil 2 est relié à l'entrée d'un registre à décalage 74 qui est destiné à retarder chaque adresse ligne reçue d'un temps de traitement équivalent au temps de traitement de trois lignes de caractère. La synchronisation du registre 74 est effectuée par le signal présenté sur le fil 6 provenant de la logique de commande 12.Wire 2 is connected to the input of a shift register 74 which is intended to delay each line address received by a processing time equivalent to the processing time of three character lines. The synchronization of the register 74 is carried out by the signal presented on the wire 6 coming from the control logic 12.

Le fil 1 est relié à l'entrée de données d'un registre à décalage 8 dont la sortie série est reliée à l'entrée de données d'un registre à décalage 9. La sortie série du registre à décalage 9 est reliée à l'entrée de données d'un registre à décalage 10. Les trois registres à décalage 8, 9 et 10 comportent chacun douze étages et peuvent donc emmagasiner chacun une ligne de matrice. Leurs entrées d'horloge sont reliées à la sortie il d'un circuit d'horloge 12. En pratique, les registres 8 à 10 peuvent être des circuits du type commercialisé sous la référence DM 74195.Wire 1 is connected to the data input of a shift register 8, the serial output of which is connected to the data input of a shift register 9. The serial output of shift register 9 is connected to l input of a shift register 10. The three shift registers 8, 9 and 10 each have twelve stages and can therefore each store a matrix line. Their clock inputs are connected to the output il of a clock circuit 12. In practice, the registers 8 to 10 can be circuits of the type sold under the reference DM 74195.

Le registre 8 a ses sorties parallèles "1", "2" et "3" reliées aux entrées correspondantes d'un premier circuit de traitement logique 13.1, ses sorties parallèles "4", "5" et "6" reliées aux entrées correspondantes d'un second circuit de traitement logique 13.2, ses sorties "7", "8" et "9" reliées aux entrées correspondantes d'un troisième circuit de traitement logique 13.3, et ses sorties parallèles "10", "11" et "12" reliées aux entrées correspondantes d'un quatrième circuit de traitement logique 13.4. L'ensemble des circuits 13.1, 13.2, 13.3 et 13.4, qui sont identiques, forme un circuit de conversion 13 qui convertit des tranches de trois pixels en tranches de deux pixels.Register 8 has its parallel outputs "1", "2" and "3" connected to the corresponding inputs of a first logic processing circuit 13.1, its parallel outputs "4", "5" and "6" connected to the corresponding inputs of a second logic processing circuit 13.2, its outputs "7", "8" and "9" connected to the corresponding inputs of a third logic processing circuit 13.3, and its parallel outputs "10", "11" and " 12 "connected to the corresponding inputs of a fourth logic processing circuit 13.4. The set of circuits 13.1, 13.2, 13.3 and 13.4, which are identical, forms a conversion circuit 13 which converts slices of three pixels into slices of two pixels.

D'une manière analogue, le registre 9 a ses sorties parallèles "1", "2" et "3" reliées à des entrées correspondantes du circuit 13.1, ses sorties parallèles "4", "5" et "6" reliées à des entrées correspondantes du circuit 13.2, ses sorties parallèles "7", "8" et "9" reliées à des entrées correspondantes du circuit 13.3, et ses sorties parallèles "10", "11" et "12" reliées à des entrées correspondantes du circuit 13.4.Similarly, the register 9 has its parallel outputs "1", "2" and "3" connected to corresponding inputs of the circuit 13.1, its parallel outputs "4", "5" and "6" connected to corresponding inputs of circuit 13.2, its parallel outputs "7", "8" and "9" connected to corresponding inputs of circuit 13.3, and its parallel outputs "10", "11" and "12" connected to corresponding inputs of circuit 13.4.

Le circuit 13.1 a deux sorties qui sont respectivement reliées aux entrées parallèles "1" et "2" d'un registre à décalage 14 à huit étages; le circuit 13.2 a deux sorties respectivement reliées aux entrées parallèles "3" et "4" du registre 14, le circuit 13.3 a deux sorties reliées respectivement aux entrées parallèles "5" et "6" du registre 14; et le circuit 13.4 a deux sorties respectivement reliées aux entrées "7" et "8" du registre 14. La sortie série du registre 14 est reliée à l'entrée d'un registre à décalage 15 à huit étages. La sortie série du registre 15 est reliée à l'entrée série d'un autre registre à décalage 16 à huit étages dont la sortie est reliée au fil 4.The circuit 13.1 has two outputs which are respectively connected to the parallel inputs "1" and "2" of an eight-stage shift register 14; circuit 13.2 has two outputs respectively connected to the inputs parallel "3" and "4" of the register 14, the circuit 13.3 has two outputs connected respectively to the parallel inputs "5" and "6" of the register 14; and the circuit 13.4 has two outputs respectively connected to the inputs "7" and "8" of the register 14. The serial output of the register 14 is connected to the input of an eight-stage shift register 15. The serial output of register 15 is connected to the serial input of another shift register 16 with eight stages, the output of which is connected to wire 4.

Le registre 8 a encore ses sorties parallèles "1" à "3" reliées respectivement aux premières entrées de trois portes ET P1; ses sorties parallèles "4" à "6" reliées respectivement, d'une part, aux premières entrées de trois portes ET Q1 et, d'autre part, aux premières entrées de trois portes ET P2; ses trois sorties parallèles "7" à "9" reliées respectivement, d'une part, aux premières entrées de trois portes ET Q2 et, d'autre part, aux premières entrées de trois portes ET P3; et, enfin, ses trois sorties parallèles "10" à "12" reliées aux premières entrées de trois portes ET Q3. L'ensemble des portes ET P1 à P3 et Q1 à Q3 forment un commutateur 17.Register 8 also has its parallel outputs "1" to "3" connected respectively to the first inputs of three AND gates P1; its parallel outputs "4" to "6" connected respectively, on the one hand, to the first inputs of three AND gates Q1 and, on the other hand, to the first inputs of three AND gates P2; its three parallel outputs "7" to "9" connected respectively, on the one hand, to the first inputs of three AND gates Q2 and, on the other hand, to the first inputs of three AND gates P3; and, finally, its three parallel outputs "10" to "12" connected to the first inputs of three AND gates Q3. The set of AND gates P1 to P3 and Q1 to Q3 form a switch 17.

Les sorties des portes ET P1 et Q1 sont respectivement reliées aux premières entrées de six portes OU R1; les sorties des portes ET P2 et Q2 sont respectivement reliées aux premières entrées de six portes OU R2, et les sorties des portes ET P3 et Q3 sont respectivement reliées aux premières entrées de six portes OU R3. Les portes OU R1 à R3 forment le circuit de liaison 18. Les sorties des six portes OU R1 sont reliées aux entrées correspondantes A1 à A6 d'un circuit de traitement logique 19.1; les sorties des six portes OU R2 sont reliées aux entrées correspondantes A d'un circuit de traitement logique 19.2, et les sorties des six portes OU R3 sont reliées aux entrées correspondantes A d'un troisième circuit de traitement logique 19.3. Les circuits 19.1 à 19.3, qui sont identiques, forment le circuit de traitement 19.The outputs of AND gates P1 and Q1 are respectively connected to the first inputs of six OR gates R1; the outputs of AND gates P2 and Q2 are respectively connected to the first inputs of six OR gates R2, and the outputs of AND gates P3 and Q3 are respectively connected to the first inputs of six OR gates R3. The OR gates R1 to R3 form the connection circuit 18. The outputs of the six OR gates R1 are connected to the corresponding inputs A1 to A6 of a logic processing circuit 19.1; the outputs of the six OR gates R2 are connected to the corresponding inputs A of a logic processing circuit 19.2, and the outputs of the six OR gates R3 are connected to the corresponding inputs A of a third logic processing circuit 19.3. The circuits 19.1 to 19.3, which are identical, form the processing circuit 19.

Le circuit 19.1 a deux sorties qui sont respectivement reliées aux entrées parallèles "2" et "3" du registre 15; le circuit 19.2 a deux sorties qui sont respectivement reliées aux entrées "4" et "5" du registre 15; et le circuit 19.3 a deux sorties qui sont respectivement reliées aux entrées "6" et "7" du registre 15:The circuit 19.1 has two outputs which are respectively connected to the parallel inputs "2" and "3" of the register 15; circuit 19.2 has two outputs which are respectively connected to inputs "4" and "5" of register 15; and circuit 19.3 has two outputs which are respectively connected to inputs "6" and "7" of register 15:

Par ailleurs, le circuit 19.1 a des entrées B qui sont respectivement reliées aux sorties parallèles "2", "3", "4" et "5" du registre 9; le circuit 19.2 a des entrées B qui sont respectivement reliées aux sorties parallèles "5", "6", "7" et "8" du registre 9; et le circuit 19.3 a des entrées B qui sont sont respectivement reliées aux sorties "8", "9", "10" et "11" du registre 9.Furthermore, the circuit 19.1 has inputs B which are respectively connected to the parallel outputs "2", "3", "4" and "5" of the register 9; circuit 19.2 has inputs B which are respectively connected to parallel outputs "5", "6", "7" and "8" of register 9; and circuit 19.3 has inputs B which are respectively connected to outputs "8", "9", "10" and "11" of register 9.

Le circuit 19.1 a encore des entrées C qui sont respectivement reliées aux sorties parallèles "2" et "3" du registre 16; le circuit 19.2 a des entrées C qui sont respectivement reliées aux sorties parallèles "4" et "5" du registre 16; et le circuit 19.3 a des entrées C qui sont respectivement reliées aux sorties parallèles "6" et "7" du registre 16.The circuit 19.1 also has inputs C which are respectively connected to the parallel outputs "2" and "3" of the register 16; the circuit 19.2 has inputs C which are respectively connected to the parallel outputs "4" and "5" of the register 16; and the circuit 19.3 has inputs C which are respectively connected to the parallel outputs "6" and "7" of the register 16.

Enfin, le circuit 19.1 a une sortie D reliée aux secondes entrées des portes P1 et Q1; le circuit 19.2 a une sortie D reliée aux secondes entrées des portes ET P2 et Q2; et le circuit 19.3 a une sortie D reliée aux secondes entrées des portes ET P3 et 03.Finally, the circuit 19.1 has an output D connected to the second inputs of the doors P1 and Q1; circuit 19.2 has an output D connected to the second inputs of AND gates P2 and Q2; and circuit 19.3 has an output D connected to the second inputs of AND gates P3 and 03.

Le registre 10 a ses sorties parallèles "1" à "3" reliées respectivement aux premières entrées de trois portes ET P'1; ses sorties parallèles "4" à "6" reliées respectivement, d'une part, aux premières entrées de trois portes ET Q'1 et, d'autre part, aux premières entrées de trois portes ET P'2, ses trois sorties parallèles "7" à "9" reliées respectivement, d'une part, aux premières entrées de trois portes ET Q'2 et, d'autre part, aux premières entrées de trois portes ET P'3; et, enfin, ses trois sorties parallèles "10" à "12" reliées aux premières entrées de trois portes ET Q3. L'ensemble des portes ET P'1 à P'3 et Q'1 à Q'3 formant un commutateur 20.The register 10 has its parallel outputs "1" to "3" connected respectively to the first inputs of three AND gates P'1; its parallel outputs "4" to "6" connected respectively, on the one hand, to the first inputs of three AND gates Q'1 and, on the other hand, to the first inputs of three AND gates P'2, its three parallel outputs "7" to "9" connected respectively, on the one hand, to the first inputs of three AND gates Q'2 and, on the other hand, to the first inputs of three AND gates P'3; and, finally, its three parallel outputs "10" to "12" connected to the first inputs of three AND gates Q3. The set of AND gates P'1 to P'3 and Q'1 to Q'3 forming a switch 20.

Les sorties des portes ET P'1 et Q'1 sont respectivement reliées aux secondes entrées des six portes OU R1; les sorties des portes ET P'2 et Q'2 sont respectivement reliées aux secondes entrées des six portes OU R2, et les sorties des portes ET P'3 et Q'3 sont respectivement reliées aux secondes entrées des six portes OU R3.The outputs of AND gates P'1 and Q'1 are respectively connected to the second inputs of the six OR gates R1; the outputs of AND gates P'2 and Q'2 are respectively connected to the second inputs of the six OR gates R2, and the outputs of AND gates P'3 and Q'3 are respectively connected to the second inputs of the six OR R3 gates.

Le circuit 19.1 a une sortie E reliée aux secondes entrées des portes P'1 et Q'1; le circuit 19.2 a une sortie E reliée aux secondes entrées des portes ET P'2 et Q'2, et le circuit 19.3 a une sortie E reliée aux secondes entrées des portes ET P'3 et Q'3.The circuit 19.1 has an output E connected to the second inputs of the doors P'1 and Q'1; circuit 19.2 has an output E connected to the second inputs of AND gates P'2 and Q'2, and circuit 19.3 has an output E connected to second inputs of AND gates P'3 and Q'3.

Avant de décrire en détail le circuit de traitement logique 13.1, Fig. 4, et le circuit de traitement logique 19.1, Fig. 5, on va considérér les diagrammes des Figs. 3a et 3b. Dans le diagramme de la Fig. 3a, on a représenté à gauche, en regardant le dessin, une portion de matrice 12x10 et, à droite, la portion transformée de matrice 8x10, après passage dans le circuit 13.1. Cette transformation sera, dans la suite, désignée par première phase ou phase 1. On notera que, dans cette phase, les douze pixels d'une ligne i sont groupés en quatre groupes de trois pixels: a, b, c, a', b', c'; a", b", etc. Chaque groupe de trois pixels est transformé en un groupe de deux pixels dans la matrice 8x10. Chaque ligne de la matrice 8x10 comprend quatre groupes de pixels transformés: â, b, â', b'; â", etc. Plus particulièrement, pour la matrice 12x10, on a représente, à la ligne i, un premier groupe de trois pixels a, b, c, suivi d'un second groupe de trois pixels a', b', c', et, à la ligne (i―1), le premier groupe correspondant de trois pixels a-i, b_1, c-i, suivi du second groupe correspondant de trois pixels a'-i, b'_1, c'-i. Il leur correspond, dans la matrice 8x10, à la ligne i, le premier groupe de deux pixels â, b, suivi du second groupe de deux pixels â', b'.Before describing in detail the logic processing circuit 13.1, FIG. 4, and the logic processing circuit 19.1, FIG. 5, we will consider the diagrams of Figs. 3a and 3b. In the diagram of FIG. 3a, there is shown on the left, looking at the drawing, a portion of matrix 12 × 10 and, on the right, the transformed portion of matrix 8 × 10, after passing through the circuit 13.1. This transformation will, in the following, be designated by first phase or phase 1. It will be noted that, in this phase, the twelve pixels of a line i are grouped into four groups of three pixels: a, b, c, a ', b ', c'; a ", b", etc. Each group of three pixels is transformed into a group of two pixels in the 8x10 matrix. Each line of the 8x10 matrix comprises four groups of transformed pixels: â, b, â ', b'; â ", etc. More particularly, for the matrix 12x10, we represent, at line i, a first group of three pixels a, b, c, followed by a second group of three pixels a ', b', c ', and, at line (i ― 1), the first corresponding group of three pixels a- i , b_ 1 , c- i , followed by the second corresponding group of three pixels a'- i , b'_ 1 , c '-. i It corresponds to them, in the 8x10 matrix, at row i, the first group of two pixels, b, followed by the second group of two pixels a', b '.

La Fig. 4 représente en détail le schéma logique du circuit de traitement logique 13.1 qui calcule les pixels â et b en fonction des pixels, a, b, c, a_1, b_1 et c-i, suivant les équations logiques suivantes:

Figure imgb0004
Fig. 4 shows in detail the logic diagram of the logic processing circuit 13.1 which calculates the pixels â and b as a function of the pixels, a, b, c, a_ 1 , b_ 1 and c- i , according to the following logic equations:
Figure imgb0004

Dans le circuit 13.1, les références numériques des entrées sont celles des données des pixels auxquelles elles correspondent. L'entrée a est reliée, d'une part, à l'entrée inverseuse d'une porte ET 21 et, d'autre part, à l'entrée d'une porte OU 22. L'entrée b est reliée à l'entrée non inverseuse de la porte ET 21. L'entrée c est reliée, d'une part, à l'autre entrée inverseuse de la porte ET 21 et, d'autre part, à une entrée d'une porte OU 23. L'entrée a_1 est reliée, d'une part, à une entrée directe d'une porte ET 24 et, d'autre part, à une entrée inverseuse d'une porte ET 25. L'entrée b_1 est reliée, d'une part, à des entrées inverseuses des portes 24 et 25 et, d'autre part, à des entrées directes de portes ET 26 et 27. L'entrée c_1 est reliée, d'une part, à une entrée directe de la porte ET 26 et, d'autre part, à une entrée inverseuse de la porte ET 27.In circuit 13.1, the digital references of the inputs are those of the data of the pixels to which they correspond. Input a is connected, on the one hand, to the inverting input of an AND gate 21 and, on the other hand, to the input of an OR gate 22. Input b is connected to the non-inverting input of AND gate 21. Input c is connected, on the one hand, to the other inverting input of AND gate 21 and, on the other hand, to an input of an OR gate 23. L input a_ 1 is connected, on the one hand, to a direct input of an AND gate 24 and, on the other hand, to an inverting input of an AND gate 25. Input b_ 1 is connected, of on the one hand, to inverting inputs of doors 24 and 25 and, on the other hand, to direct inputs of AND doors 26 and 27. The input c_ 1 is connected, on the one hand, to a direct input of the door AND 26 and, on the other hand, to an inverting input of the AND gate 27.

La sortie de la porte ET 21 est reliée aux premières entrées de deux portes ET 28 et 29. Les sorties des portes ET 25 et 26 sont respectivement reliées à deux entrées d'une porte OU 30 à trois entrées. Les sorties des portes ET 24 et 27 sont respectivement reliées à deux entrées d'une porte OU 31 à trois entrées. Les sorties des portes OU 30 et 31 sont respectivement reliées aux secondes entrées des portes ET 29 et 28. Les sorties des portes ET 28 et 29 sont respectivement reliées aux secondes entrées des portes OU 22 et 23. Les troisièmes entrées des portes OU 30 et 31 sont reliées à l'entrée d'activation 32. Les sorties des portes OU 22 et 23 délivrent respectivement les pixels à et b qui sont transmis par les fils de sortie de 13.1 vers les entrées "1" et "2" du registre 14.The output of AND gate 21 is connected to the first inputs of two AND gates 28 and 29. The outputs of AND gates 25 and 26 are respectively connected to two inputs of an OR gate 30 with three inputs. The outputs of AND gates 24 and 27 are respectively connected to two inputs of an OR gate 31 with three inputs. The outputs of OR gates 30 and 31 are respectively connected to the second inputs of AND gates 29 and 28. The outputs of AND gates 28 and 29 are respectively connected to the second inputs of OR gates 22 and 23. The third inputs of OR gates 30 and 31 are connected to the activation input 32. The outputs of the OR gates 22 and 23 respectively deliver the pixels a and b which are transmitted by the output wires of 13.1 to the inputs "1" and "2" of the register 14 .

Bien entendu, le circuit 13.2 calcule les pixels â' et b' à partir des seconds groupes de trois pixels des lignes i et (i-1), etc.Of course, the circuit 13.2 calculates the pixels â 'and b' from the second groups of three pixels of the lines i and (i-1), etc.

Dans le diagramme de la Fig. 3b, on a représenté, à gauche, une portion de matrice 12x10 et, à droite, la portion transformée de matrice 8x10, après première phase et la portion transformée après deuxième phase. En pratique, la deuxième phase est utile pour réduire aux frontières entre les groupes de deux pixels les épaisseurs des traits.In the diagram of FIG. 3b, there is shown, on the left, a portion of 12 × 10 matrix and, on the right, the transformed portion of 8 × 10 matrix, after the first phase and the portion transformed after the second phase. In practice, the second phase is useful for reducing the thicknesses of the lines at the borders between the groups of two pixels.

Dans la matrice 12x10, Fig. 3b, on considère la fenêtre d'observation comportant, ligne i, les pixels c et a', et, ligne (i-1), les pixels b_1, c_1, a'_1, b'_1. Les pixels de cette fenêtre servent, dans certains cas, que l'on définira ci-dessous, à éventuellement modifier les pixels b et â' résultant des traitements dans les circuits 13.1 et 13.2 pour obtenir les pixels définitifs b* et a'* résultant du traitement dans le circuit 19.1.In the 12x10 matrix, Fig. 3b, we consider the observation window comprising, line i, the pixels c and a ', and, line (i-1), the pixels b_ 1 , c_ 1 , a'_ 1 , b'_ 1 . The pixels of this window are used, in certain cases, which will be defined below, to possibly modify the pixels b and â 'resulting from the processing in circuits 13.1 and 13.2 to obtain the final pixels b * and a' * resulting processing in the circuit 19.1.

Le traitement dans le circuit 19.1 n'est déclenché que pour une configuration des pixels b, c, a', b' égale à 0110..Dans ce cas, le circuit 19.1, Fig. 5, permet de prendre en compte des pixels de la ligne (i―1 et éventuellement des pixels de la ligne (i+1 ), ou de la ligne (i+1 pour définir les pixels transformés b et â' de la ligne i. Dans toutes les autres configurations des pixels b, c, a', b', les pixels transformés b et â' sont ceux qui ont été calculés par les circuits 13.1 et 13.2.Processing in circuit 19.1 is only triggered for a configuration of pixels b, c, a ', b' equal to 0110..In this case, circuit 19.1, Fig. 5, allows to take into account pixels of the line (i ― 1 and possibly pixels of the line (i + 1), or of the line (i + 1 to define the transformed pixels b and â 'of line i In all the other configurations of the pixels b, c, a ', b', the transformed pixels b and â 'are those which have been calculated by the circuits 13.1 and 13.2.

Dans le cas, (b, c, a', b')=0110, plusieurs circonstances peuvent se présenter:

Figure imgb0005
In the case, (b, c, a ', b') = 0110, several circumstances can arise:
Figure imgb0005

Dans le cas 6), les pixels transformés 6 et â' sont définis, soit par les deux équations logiques suivantes:

Figure imgb0006
et
Figure imgb0007
soit par les deux équations logiques équivalentes (1') et (II') où - est remplacé par +.In case 6), the transformed pixels 6 and â 'are defined, either by the following two logical equations:
Figure imgb0006
 and
Figure imgb0007
 either by the two equivalent logical equations (1 ') and (II') where - is replaced by +.

Les entrées de données du circuit 19.1 sont l'entrée A à six fils permettant de recevoir les données des pixels a_1, b_1, c-1, a'_1, b'_1, c'_1, quand le fil E est activé, ou les données des pixels a+,, b+1, c+1, a'+1, b'+1, c'+1, quand le fil D est activé; l'entrée B à quatre fils permettant de recevoir les données des pixels b, c, a', b'; et l'entrée C permettant de recevoir les données des pixels b*+1, â+1.The data inputs of circuit 19.1 are the six-wire input A used to receive the pixel data a_ 1 , b_ 1 , c- 1 , a'_ 1 , b'_ 1 , c'_ 1 , when the wire E is activated, or the pixel data a + ,, b +1 , c +1 , a ' +1 , b' +1 , c ' +1 , when the wire D is activated; four-wire input B for receiving data from pixels b, c, a ', b'; and the input C for receiving data from pixels b * +1 , â +1 .

Dans le circuit 19.1, une porte NI 33 a ses entrées directes reliées aux entrées b et b' et ses entrées inverseuses aux entrées c et a'. La porte 33 permet de détecter la configuration 0110, mentionnée plus haut, dans la ligne i.In circuit 19.1, an NI gate 33 has its direct inputs connected to inputs b and b 'and its inverting inputs to inputs c and a'. Gate 33 makes it possible to detect the configuration 0110, mentioned above, in line i.

Une porte NI 34 a ses quatre entrées directes reliées aux fils b1, c1, a'1 et b1,. La porte 34 sert à détecter le cas 1) ou le cas 4), mentionnés ci-dessus.An NI 34 door has its four direct inputs connected to wires b 1 , c 1 , a ' 1 and b 1 ,. Gate 34 is used to detect case 1) or case 4), mentioned above.

Une porte NI 35 a ses deux entrées directes reliées aux fils b1 et b'1, et ses entrées inverseuses aux fils c1 et a',. La porte 35 sert à détecter la cas 2) ou le cas 5), mentionnée ci-dessus.An NI 35 door has its two direct inputs connected to wires b 1 and b ' 1 , and its inverting inputs to wires c 1 and a'. Gate 35 is used to detect case 2) or case 5), mentioned above.

Les sorties des portes 34 et 35 sont respectivement reliées aux deux entrées d'une porte OU 30 dont la sortie est reliée à une entrée d'une porte ET 64. La sortie de la porte 34 est encore reliée à l'entrée D d'une bascule 37 qui a une entrée R de remise à zéro reliée à la sortie d'une porte OU 38 dont une entrée est reliée à l'entrée de commande 39 et l'autre entrée à l'entrée de commande 40, une entrée S de mise à un reliée à l'entrée de commande 41, une sortie Q reliée au fil de sortie D et une sortie Q reliée au fil de sortie E.The outputs of doors 34 and 35 are respectively connected to the two inputs of an OR gate 30, the output of which is connected to an input of an AND gate 64. The output of gate 34 is still connected to the input D of a flip-flop 37 which has a reset input R connected to the output of an OR gate 38 one input of which is connected to the control input 39 and the other input to the control input 40, an input S of set to a connected to the control input 41, an output Q connected to the output wire D and an output Q connected to the output wire E.

Le circuit 19.1 comprend encore deux circuits de calculs 42 et 43 effectuant respectivement les deux calculs logiques mentionnés ci-dessus.The circuit 19.1 further comprises two calculation circuits 42 and 43 respectively carrying out the two logic calculations mentioned above.

Dans le circuit 42, une parte ET 44 a ses deux entrées directes reliées aux fils c' et c1; une porte ET 45 a trois entrées directes reliées aux fils a1, b1, c1 et une entrée inverseuse reliée au fil c'1; une porte ET 46 a une entrée directe reliée au fil c1 et une entrée inverseuse reliée au fil b1; une porte 47 a une entrée directe reliée au fil b1 et une entrée inverseuse reliée au fil c1; une porte ET 48 a une entrée directe reliée au fil a'1 et trois entrées inverseuses reliées aux fils b1, c1 et a. On notera que ci-dessus on n'a pas précisé le signe de l'indice 1, car il est négatif ou positif selon l'état de la bascule 37.In circuit 42, an ET 44 part has its two direct inputs connected to wires c 'and c 1 ; an AND gate 45 has three direct inputs connected to the wires a 1 , b 1 , c 1 and an inverting input connected to the wire c '1; an AND gate 46 has a direct input connected to wire c 1 and an inverting input connected to wire b 1 ; a door 47 has a direct input connected to the wire b 1 and an inverting input connected to the wire c 1 ; an AND gate 48 has a direct input connected to wire a ' 1 and three inverting inputs connected to wires b 1 , c 1 and a. Note that above we did not specify the sign of the index 1, because it is negative or positive depending on the state of flip-flop 37.

Les sorties des portes ET 44 et 47 sont reliées aux deux entrées d'une porte OU 49. Les sorties des portes ET 45,46 et 47 sont reliées aux trois entrées d'une porte OU 50. La sortie de la porte OU 49 est reliée à l'entrée directe d'une porte ET 51 dont les entrées inverseuses sont reliées aux fils a'1 et b'1. La sortie de la porte OU 50 est reliée à une entrée directe d'une porte ET 52 dont les deux autres entrées directes sont reliées aux entrées a'1 et b'1. Les sorties des portes ET 48, 51 et 52 sont reliées à trois entrées d'une porte OU 53.The outputs of AND gates 44 and 47 are connected to the two inputs of an OR gate 49. The outputs of AND gates 45, 46 and 47 are connected to the three inputs of an OR gate 50. The output of OR gate 49 is connected to the direct input of an AND gate 51 whose inverting inputs are connected to wires a ' 1 and b' 1 . The output of the OR gate 50 is connected to a direct input of an AND gate 52, the other two direct inputs of which are connected to the inputs a ' 1 and b' 1 . The outputs of AND gates 48, 51 and 52 are connected to three inputs of an OR gate 53.

Dans le circuit 43, une porte ET 54 a ses deux entrées directes reliées aux fils a et a',; une porte ET 55 a trois entrées directes reliées aux fils a'1, b'1, c'1 et une entrée inverseuse reliée au fil a,; une porte ET 56 a une entrée directe reliée au fil b'1 et son entrée inverseuse reliée au fil a',; une porte ET 57 a son entrée directe reliée au fil a'1 et son entrée inverseuse reliée au fil b'1; et une porte ET 58 a une entrée directe reliée au fil c_, et trois entrées inverseuse reliées aux fils a'1, b'1 et c'.In circuit 43, an AND gate 54 has its two direct inputs connected to wires a and a '; an AND gate 55 has three direct inputs connected to wires a ' 1 , b' 1 , c ' 1 and an inverting input connected to wire a ,; an AND gate 56 has a direct input connected to wire b ' 1 and its inverting input connected to wire a',; an AND gate 57 has its direct input connected to wire a ' 1 and its inverting input connected to wire b'1; and an AND gate 58 has a direct input connected to the wire c_, and three inverting inputs connected to the wires a ' 1 , b' 1 and c '.

Les sorties des portes ET 54 et 56 sont reliées aux deux entrées d'une porte OU 59. Les sorties des portes ET 55,56 et 57 sont reliées aux trois entrées d'une porte OU 60. La sortie de la porte OU 59 est reliées à l'entrée directe d'une porte ET 61 dont les entrées inverseuses sont reliées aux fils b_1 et c_1. La sortie de la porte OU 60 est reliée à une entrée directe d'une porte ET 62 dont les deux autres entrées directes sont reliées aux fils b_1 et c_1. Les sorties des portes ET 58, 61 et 62 sont reliées à trois entrées d'une porte OU 63.The outputs of AND gates 54 and 56 are connected to the two inputs of an OR gate 59. The outputs of AND gates 55, 56 and 57 are connected to the three inputs of an OR gate 60. The output of OR gate 59 is connected to the direct input of an AND gate 61 whose inverting inputs are connected to wires b_ 1 and c_ 1 . The output of the OR gate 60 is connected to a direct input of an AND gate 62, the other two direct inputs of which are connected to the wires b_ 1 and c_ 1 . The outputs of AND gates 58, 61 and 62 are connected to three inputs of an OR gate 63.

La sortie de la porte OU 36 est reliée à une entrée d'une porte ET 64 dont l'autre entrée est reliée à la sortie Q de la bascule 37 et dont la sortie est reliée à la première entrée de deux portes OU 65 et 66. Les portes OU ont chacune une entrée d'activation qui est reliée à la sortie de la porte NI 33.The output of the OR gate 36 is connected to an input of an AND gate 64, the other input of which is connected to the output Q of the flip-flop 37 and the output of which is connected to the first input of two OR gates 65 and 66 The OR gates each have an activation input which is connected to the output of gate NI 33.

La sortie de la porte NI 35 est encore reliée à une entrée d'une porte ET 67 dont l'autre entrée est reliée à la sortie Q de la bascule 37 et dont la sortie est reliée à la première entrée de deux portes ET 68 et 69. Les secondes entrées des portes 68 et 69 sont respectivement reliées aux fils a'*+1 et b*+1 de l'entrée C et leurs sorties sont respectivement reliées aux secondes entrées de portes OU 65 et 66. Les troisièmes entrées des portes 65 et 66 sont respectivement reliées aux sorties des portes 53 et 63.The output of the NI gate 35 is also connected to an input of an AND gate 67, the other input of which is connected to the output Q of the flip-flop 37 and the output of which is connected to the first input of two AND gates 68 and 69. The second inputs of doors 68 and 69 are respectively connected to the wires a '* +1 and b * +1 of input C and their outputs are respectively connected to the second inputs of doors OR 65 and 66. The third inputs of doors 65 and 66 are respectively connected to the outputs of doors 53 and 63.

Quand la configuration bca'b'=0110 n'apparaît pas dans une ligne i, les portes OU 65 et 66 sont inhibées si bien que le circuit 19.1 est inopérant. Dans le cas contraire, c'est le circuit 19.1 qui sert à définir les pixals transformés b et â' de la ligne i. Dans l'exemple de réalisation décrit, le circuit 19.1 fonctionne quel que soit l'état de la sortie de 33 qui ne sert qu'à valider les calculs.When the configuration bca'b '= 0110 does not appear in a line i, the OR gates 65 and 66 are inhibited so that the circuit 19.1 is inoperative. Otherwise, it is circuit 19.1 which is used to define the transformed pixels b and â 'of line i. In the example of embodiment described, the circuit 19.1 operates whatever the state of the output of 33 which only serves to validate the calculations.

A chaque ligne i, avec i≠1, écrite dans le registre 9, la bascule 37 est remise à zéro par 39 ou 40. Donc la sortie Q est a "1" si bien que les signaux entrant dans 19.1 sont ceux qui sont présents dans les registres 9 et 10. Autrement dit, l'indice 1 des entrées de 42 et 43 est égal à -1 et les formules 1 et Il s'appliquent. L'état de la porte 34 indique si on rencontre le cas 1 ) et celui de la porte 35 si l'on rencontre le cas 2), ou leurs états indiquent que l'on est dans le cas 6). Trois fonctionnements différents peuvent donc être déclenchés:

  • cas 1: Par 34, l'entrée D de la bascule 37 passe à "1" si bien que en sortie Q passe à "1". Il en résulte que les signaux entrants sont maintenant ceux des registres 8 et 9. On analyse donc la ligne (i+1) avec la ligne i. Les trois cas 4), 5) ou 6) peuvent se présenter:
    • cas 4): la sortie de 34 est à "1" et la sortie Q de 37 est à "1", ce qui entraîne la sortie de la porte ET 64 à "1". Donc, les sorties b et â' sont à "1". Les pixels transformés en phase 2 sont b=â'=1.
    • cas 5: la sortie de 35, donc de 36, est à "1" et la sortie Q de 37 est à "1", ce qui entraîne la sortie de la porte ET 64 à "1 ". Donc, les sorties b et â' sont à "1 ". Les pixels transformés en phase 2 sont b=â'=1.
    • cas 6: les sorties de 34 et de 35 sont à "0". Donc les portes 66 et 65 laissent passer les pixels calculés par 43 et 42 et les pixels transformés en phase 1 sont modifiés. Les formules l' et II' s'appliquent.
  • cas 2): La sortie de 35 est à "1" et la sortie Q de 37 est à "1". Donc, la sortie de la porte 67 est à "1" ce qui entraîne que les portes ET transmettent les données des pixels b*-, et a'*-, qui viennent prendre la place des pixels transformés en phase 1.
  • cas 3: Les pixels de la première ligne à transformer sont écrits dans le registre 9. L'entrée 41 est activés si bien que la sortie Q de la bascule 37 est à "1". Il en résulte que les signaux entrants sont immédiatement ceux des registres 8 et 9. Les trois cas 4), 5) ou 6) peuvent se présenter:
    • cas 4: on retrouve le fonctionnement décrit en relation avec le cas 1) ci-dessus.
    • cas 5: la sortie de 35 est à "1" et la sortie Q de 37 est à "1", ce qui entraîne la sortie de la porte ET 64 à "1". On retrouve le cas 4) ci-dessus.
    • cas 6: Les sorties de 34 et de 35 sont "0". Donc, on retrouve le cas 6) mentionné ci-dessus.
  • cas 6: on retrouve les fonctionnements déjà vus pour ce cas. Les pixels transformés sont obtenus à partir des calculs logiques effectués dans 42 et 43. Les formules 1 et Il s'appliquent.
At each line i, with i ≠ 1, written in register 9, the flip-flop 37 is reset to zero by 39 or 40. So the output Q is at "1" so that the signals entering 19.1 are those which are present in registers 9 and 10. In other words, the index 1 of the entries of 42 and 43 is equal to -1 and the formulas 1 and II apply. The state of door 34 indicates whether we meet case 1) and that of door 35 if we meet case 2), or their states indicate that we are in case 6). Three different operations can therefore be triggered:
  • case 1: By 34, the entry D of rocker 37 passes to "1" so that in exit Q passes to "1". It follows that the incoming signals are now those of registers 8 and 9. We therefore analyze the line (i + 1) with the line i. The three cases 4), 5) or 6) can arise:
    • case 4): the output of 34 is at "1" and the Q output of 37 is at "1", which causes the output of AND gate 64 to be "1". Therefore, the outputs b and â 'are at "1". The pixels transformed in phase 2 are b = â '= 1.
    • case 5: the output of 35, therefore 36, is at "1" and the Q output of 37 is at "1", which causes the output of the AND gate 64 to "1". Therefore, the outputs b and â 'are at "1". The pixels transformed in phase 2 are b = â ' = 1 .
    • case 6: the outputs of 34 and 35 are at "0". So the gates 66 and 65 allow the pixels calculated by 43 and 42 to pass and the pixels transformed in phase 1 are modified. Formulas l 'and II' apply.
  • case 2): The output of 35 is at "1" and the Q output of 37 is at "1". Therefore, the output of gate 67 is at "1" which causes the AND gates to transmit the data of the pixels b * - , and a ' * -, which take the place of the pixels transformed in phase 1.
  • case 3: The pixels of the first line to be transformed are written in the register 9. The input 41 is activated so that the output Q of the flip-flop 37 is at "1". As a result, the incoming signals are immediately those of registers 8 and 9. The three cases 4), 5) or 6) can occur:
    • case 4: we find the operation described in relation to case 1) above.
    • case 5: the output of 35 is at "1" and the Q output of 37 is at "1", which causes the output of gate AND 64 to be "1". We find the case 4) above.
    • case 6: The outputs of 34 and 35 are "0". So, we find the case 6) mentioned above.
  • case 6: we find the functions already seen for this case. The transformed pixels are obtained from the logical calculations carried out in 42 and 43. Formulas 1 and II apply.

La base de temps ou commande logique 12 comprend un compteur 121 à quatre étages recevant en C le signal d'horloge bit qu'il délivre aussi en H. Par ailleurs ses sorties QA, QB, QC et QD sont respectivement reliées aux deux premières entrées inverseuses, à la troisième entrée non inverseuse et à la quatrième entrée inverseuse d'une porte NI 122. La sortie de la porte 122 et la sortie H de 121 sont reliées aux entrées d'une porte ET 123 dont la sortie est reliée aux entrées d'horloge des registres 8, 9 et 10. Par ailleurs, les sorties QA, QB, QC et QD sont respectivement reliées à la première entrée non inverseuse et aux trois autres entrées inverseuses d'une porte NI 124. La sortie de la porte 124 et la sortie H et 121 sont reliées aux entres d'une porte ET 125 dont la sortie est reliée aux entrées d'horloge des registres 14, 15 et 16.The time base or logic control 12 comprises a four-stage counter 121 receiving at C the bit clock signal which it also delivers at H. Furthermore its outputs QA, QB, QC and QD are respectively connected to the first two inputs inverters, to the third non-inverting input and to the fourth inverting input of an NI 122. gate The output of gate 122 and the output H of 121 are connected to the inputs of an AND gate 123 whose output is connected to the inputs clock registers 8, 9 and 10. In addition, the outputs QA, QB, QC and QD are respectively connected to the first non-inverting input and to the other three inverting inputs of an NI 124 door. The door output 124 and the output H and 121 are connected to the inputs of an AND gate 125 whose output is connected to the clock inputs of the registers 14, 15 and 16.

Les sorties QD et H de 121 sont encore reliées aux entrées d'une porte ET 126 dont la sortie est reliée aux entrées d'horloge des registres 14 à 16.The outputs QD and H of 121 are also connected to the inputs of an AND gate 126 whose output is connected to the clock inputs of the registers 14 to 16.

Le circuit 12 comprend un autre compteur 127 dont l'entrée C reçoit le signal d'horloge bit et dont la sortie H' délivre des signaux d'horloge. Le compteur 127 a ses sorties QA, QB, QC et QD respectivement reliées à la première entrée inverseuse et aux trois autres entrées non inverseuses d'une porte NI 128, d'une part, et à la première entrée non inverseuse, à la seconde entrée inverseuse et aux deux autres entrées non inverseuses d'une porte NI 129.The circuit 12 includes another counter 127 whose input C receives the bit clock signal and whose output H 'delivers clock signals. The counter 127 has its QA, QB, QC and QD outputs respectively connected to the first inverting input and to the other three non-inverting inputs of an NI 128 gate, on the one hand, and to the first non-inverting input, to the second. inverting input and the other two non-inverting inputs of an NI 129 door.

La sortie de la porte 128 fournit le signal à l'entrée des portes 30 et 31 des circuits 13.1 à 13.4.The output of gate 128 provides the signal at the input of gates 30 and 31 of circuits 13.1 to 13.4.

Les sorties des portes 128 et 129 fournissent les signaux 40 et 41 dans les circuits 19.1 à 19.2.The outputs of gates 128 and 129 provide signals 40 and 41 in circuits 19.1 to 19.2.

La Fig. 9 est le schéma d'un circuit de conversion 8x10 vers 12x10. Il comprend un registre à décalage 130 à huit étages dont l'entrée de données reçoit les bits des pixels de ligne d'une matrice 8x10. Ses sorties "1" et "2" sont respectivement reliées aux entrées d'une porte OU 131. Par ailleurs, le circuit comprend un registre à décalage à douze étages 132 qui délivre les bits des pixels de ligne d'une matrice 12x10. La sortie "1" de 130 est reliée à l'entrée parallèle "1" de 132, la sortie de la porte 131 est reliée à l'entrée parallèle "2" de 132 et la sortie "2" de 130 est reliée à l'entrée parallèle "3" du registre 132. On retrouve ensuite trois fois la même structure pour successivement les sorties "3" à "8" de 130 et les entrées "4" à "12" de 132.Fig. 9 is the diagram of an 8x10 to 12x10 conversion circuit. It includes an eight-stage shift register 130 whose data input receives the bits of the line pixels of an 8 × 10 matrix. Its outputs "1" and "2" are respectively connected to the inputs of an OR gate 131. Furthermore, the circuit includes a twelve-stage shift register 132 which delivers the bits of the line pixels of a 12 × 10 matrix. The output "1" of 130 is connected to the parallel input "1" of 132, the output of the gate 131 is connected to the parallel input "2" of 132 and the output "2" of 130 is connected to the 'parallel input "3" of register 132. We then find the same structure three times for successively outputs "3" to "8" of 130 and inputs "4" to "12" of 132.

Claims (4)

1. A system for transcoding a 12x10 dot matrix into a 8x10 dot matrix, characterized in that the conversion process comprises two phases, a first phase wherein the pixels of each line are arranged in groups of three in their natural order and wherein each group of three pixels is logically processed for obtaining a group of two converted pixels, a second phase wherein the configuration of the initial 4-pixel block which straddles the limit between two groups is scrutinized so that, when this block is different of 0110, the converted group formed with two pixels converted from the first phase which are on either side of the limit, is hold and, in the opposite case, the configuration of the initial block corresponding to the former line is scrutinized and:
- when it is found equal to 0110, the pixels of the converted group are replaced by the corresponding definitely converted pixels of the former line,
- when it is different of either 0110 or 0000, the pixels of the converted group are replaced by pixels calculated in the second phase from the initial pixels nearly related with the current line and the former line,
- when it is found equal to 0000, the corresponding initial block in the next line is scrutinized and:
- when this one is found equal either to 0000 or 0110, the pixels of the converted group are replaced by 1 and 1,
- when this one is found different either of 0000 or 0110, the pixels of the converted group are replaced by pixels calculated in the second phase.
2. A system according to claim 1, characterized in that, in the first phase, the logical processing of a group of three initial pixels a, b, c provides a group of converted pixels â, b according to the following logical formulae:
Figure imgb0014
3. A system according to claim 1, characterized in that the pixels b and â', calculated in the second phase, are defined either by the two following logical equations:
Figure imgb0015
and
Figure imgb0016
or by the two equivalent equations (I') and (II') in which - has been changed to +.
4. A converting circuit operating according to the system of anyone of claims 1-3, characterized in that it comprises a digital signal input of a 12x10 dot matrix connected to the input of a set of three serially mounted upward 12-stage shift registers (8, 9, 10), the outputs of the first (8) and second (9) upward registers being connected to the corresponding inputs of a first phase processing circuit (13), a digital signal output of a 8x10 dot matrix connected to the output of a set of three serially mounted downward 8-stage registers (14, 15, 16), the outputs of the first phase processing circuit (13) being connected to the parallel inputs of the first downward register (14), the parallel outputs of the second upward register (9) being connected to corresponding inputs of a second phase processing circuit (19), the parallel outputs of the first (8) and third (10) upward registers being connected through an inverter circuit (17, 20) to corresponding inputs of the second phase processing circuit (19), the parallel outputs, except the first one and the last one, of the third downward register (16) being connected to corresponding inputs of the second phase processing circuit (19), the outputs of said second phase processing circuit being connected to the parallel inputs, except the first one and the last one, of the second downward register (15), and a time base (12) controlling the operation of the first phase processing circuit (13) and the second phase processing circuit (19), and clocking the registers.
EP83460006A 1982-12-29 1983-12-22 Matrix conversion system for dynamically redefinable character sets in a video system Expired EP0115737B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8222225 1982-12-29
FR8222225A FR2538979B1 (en) 1982-12-29 1982-12-29 DIE TRANSCODING SYSTEM FOR DYNAMICALLY REDEFINABLE ALPHABET VIDEOGRAPHY

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EP0115737A1 EP0115737A1 (en) 1984-08-15
EP0115737B1 true EP0115737B1 (en) 1988-04-06

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EP (1) EP0115737B1 (en)
JP (1) JPS6035781A (en)
BR (1) BR8307310A (en)
CA (1) CA1216676A (en)
DE (1) DE3376237D1 (en)
ES (1) ES8500537A1 (en)
FR (1) FR2538979B1 (en)
PT (1) PT77908B (en)
SU (1) SU1479015A3 (en)

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JPS63205257A (en) * 1987-02-23 1988-08-24 Oki Electric Ind Co Ltd Printing control system
NL8800052A (en) * 1988-01-11 1989-08-01 Philips Nv TELEVISION RECEIVER WITH TELETEXT DECODER.
US5237316A (en) * 1990-02-02 1993-08-17 Washington University Video display with high speed reconstruction and display of compressed images at increased pixel intensity range and retrofit kit for same
FR2658681B1 (en) * 1990-02-21 1992-04-30 Alcatel Business Systems METHOD OF ADAPTING VIDEOTEX DISPLAY FOR TELEMATIC TERMINAL.
TW247952B (en) * 1992-07-09 1995-05-21 Seikosha Kk
JP3058028B2 (en) * 1994-10-31 2000-07-04 三菱電機株式会社 Image encoded data re-encoding device

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JPS526419A (en) * 1975-07-07 1977-01-18 Fuji Xerox Co Ltd Dot matrix convertor
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CA1216676A (en) 1987-01-13
PT77908A (en) 1984-01-01
FR2538979A1 (en) 1984-07-06
DE3376237D1 (en) 1988-05-11
EP0115737A1 (en) 1984-08-15
US4709232A (en) 1987-11-24
ES528499A0 (en) 1984-10-01
BR8307310A (en) 1984-08-14
FR2538979B1 (en) 1985-07-05
PT77908B (en) 1986-03-27
JPS6035781A (en) 1985-02-23
ES8500537A1 (en) 1984-10-01
SU1479015A3 (en) 1989-05-07

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