EP0107687B1 - Anzeige für einen rechner - Google Patents

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Publication number
EP0107687B1
EP0107687B1 EP19830901331 EP83901331A EP0107687B1 EP 0107687 B1 EP0107687 B1 EP 0107687B1 EP 19830901331 EP19830901331 EP 19830901331 EP 83901331 A EP83901331 A EP 83901331A EP 0107687 B1 EP0107687 B1 EP 0107687B1
Authority
EP
European Patent Office
Prior art keywords
digital
colour
latch
signal
words
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19830901331
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English (en)
French (fr)
Other versions
EP0107687A1 (de
Inventor
Richard Francis Altwasser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amstrad PLC
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Amstrad PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amstrad PLC filed Critical Amstrad PLC
Priority to AT83901331T priority Critical patent/ATE35586T1/de
Publication of EP0107687A1 publication Critical patent/EP0107687A1/de
Application granted granted Critical
Publication of EP0107687B1 publication Critical patent/EP0107687B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/024—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour registers, e.g. to control background, foreground, surface filling

Definitions

  • the present invention relates to computers and more particularly to coloured displays for computers.
  • GB 2044052 discloses an apparatus for producing a coloured display from a computer, comprising a memory for storing digital words corresponding to a pattern to be displayed, and a smaller number of digital words corresponding to the colour of the pattern to be displayed. Each colour word is associated with a number of pattern words. The words are read out of memory and digital colour signals are produced in response to the pattern and colour words.
  • the present invention provides an apparatus for producing a coloured display from a computer as defined in the attached claims.
  • a VDU read out for a computer consists of a "page" of characters on the screen of the VDU arranged in rows and columns.
  • the size of each character position is such that 8 raster scan lines are required to fully display one row of the display.
  • the character locations of the display can be used to display either alpha-numeric symbols or graphical symbols but it will be appreciated that when displaying graphical symbols, the display will be somewhat crude due to the small number of character locations. It has already been proposed to sub-divide the character locations for graphics display using what are termed "pixels" and it is this latter concept which we are using. In our case, we envisage notionally dividing up the display area into a matrix of pixels of 192 rows each containing 256 pixels.
  • each character location requires 8 bytes of data to define the dot pattern i.e. the pixel pattern in the character location but only 1 byte of data, the attribute byte, for the colour of the character location.
  • Each attribute byte comprises a number of bits representing the foreground colour, a number of bits representing the background colour and preferably a bit to indicate whether or not to cause the character location to flash and also preferably a further bit to allow two different levels of illumination to cause particular desired areas to be highlighted.
  • the number ' of bits required for the colour information is chosen having regard to the size of the byte and the number of colours which it is wished to use. In the present case, eight colours are used which means - that 3 bits are required for background colour and 3 bits for foreground colour giving an 8 bit attribute byte.
  • a high resolution graphics display can be produced in colour using a one memory device, namely a random access memory of the dynamic type.
  • the size of the memory device is a function of the number of pixels and also the number of attribute bytes. With our system of 192x256 pixels and 768 character locations, the memory device has to be capable of storing approximately 6k bytes of data for the 192x256 pixel pattern plus approximately ik of data for the attribute bytes for the 768 character locations.
  • each character location consists of eight pixels horizontally by eight rows i.e. TV raster scan lines vertically.
  • the memory device In order to generate the raster scan TV picture, the memory device has to be accessed sequentially in a cycle that repeats every TV field.
  • the computer For every eight pixels generated, the computer needs two bytes of data from memory, a pixel pattern byte and an attribute byte. These two bytes are loaded into respective intermediate registers from which they then are loaded into further registers.
  • the six least significant bits of the attribute byte represent the foreground and background colours.
  • a data selector is controlled by the pixel pattern bytes shifted out of their register to select foreground or background colour for each pixel and fed to a colour generator circuit for generating a 3 bit (R.G.B) signal for each pixel.
  • Eight bit data words are fed from memory (not shown) to eight input pins D0 to D7.
  • the eight bits of each word are fed in parallel to the inputs of an intermediate pixel pattern latch 10 and an attribute latch 11.
  • the latch 10 or the latch 11 is gated by the processor depending on whether the data to be loaded into the latch is pixel pattern data or colour (attribute) data.
  • the memory is addressed to sequentially recover the 32 pixel pattern bytes for the 256 pixels for that line. With each of these bytes, a further portion of memory is addressed in order to recover the attribute byte for eight pixels associated therewith.
  • each of the latches 10 and 11 are connected in parallel to the pins DO to D7 and are clocked by different phases of a clock signal, it is necessary to address the memory device to deliver alternately the pixel pattern byte and associated colour attribute byte.
  • the data in the latch 10 is then transferred to a further latch 15.
  • the bits of data held in the latch 15 are shifted out serially. Each bit represents a pixel and the logical level of each bit determines whether it is a foreground or a background pixel.
  • Each bit as it is shifted out is used to gate a 3- channel 2 line to 1 line selector 16 via a logic circuit 17 which will be described in more detail later.
  • the result is a 3-bit R, G, or B signal.
  • Attribute data held in latch 11 is likewise transferred to a further latch 20. It will be recalled that 6 bits of the 8 bit data word represent foreground and background colours. These six bits are fed to the data selector 16. The remaining two bits are control bits one for indicating the level of brightness of the display for that pixel, this being indicated by the output labelled HL and the other for indicating whether or not flashing of the pixel is required, this being indicated by the output labelled FL. Flashing, in this case, is achieved by causing the pixel in question to alternately display the foreground and background colour at a rate determined by a clock signal T.
  • the logic circuit 17 contains an inverter 17a for inverting the signal on the output FL and feeding the inverted signal as an input an OR gate 17b to whose input clock signal T is applied.
  • the output of the gate 17b is fed as one input to an EX-OR gate 17c whose other input is the data bit indicating a foreground pixel.
  • the data selector 16 In operation if a data bit representing a foreground pixel is shifted out of the latch 15 to one input to the EX-OR gate 17c, the data selector 16 is conditioned to cause the 3 bits of attribute data indicative of a foreground colour to be fed to the Blue, Red and Green outputs of the selector. If flashing is required, a signal is cyclically applied to the other input of the EX-OR gate 17c to cause its output to alternate which in turn causes the output from the data selector to alternate the foreground and background colours.
  • a further latch 22 and data selector 23 are present. These are used so that the colour of the picture area around the pixel display area on the television screen can be defined to have a different colour to that of the background of the pixel display area.
  • This process is repeated along a raster line with 32 pixel pattern bytes being successively fed to the latch 10 and the 32 associated attribute bytes being successively fed to the latch 11.
  • a fresh set of 32 pixel pattern bytes are transferred successively from memory to the latch 10 but the associated attribute bytes are the same as the previous line.
  • This process is repeated line by line until 8 lines have been displayed. Thereafter a fresh set of attribute bytes are used for the next 8 lines.
  • the output of the data selector 16 is an indication of the colour required, it is not in a form which can be utilised by the colour circuits of a conventional television receiver and so further processing of the R.G.B output from the data selector 16 is required.
  • a further aspect of the present invention lies in the circuitry used to process the R,G,B signals into the more conventional Y,U,V signals.
  • Figure 2 shows a circuit for deriving the U signal for a colour television receiver.
  • the digital R,G,B outputs from the data selector 16 are combined with sync, blank and burst signals to provide correct phase digital signals in a digital to analogue converter circuit which is shown in Figure 2.
  • the R,G,B signals are now Blue” Green” and Red” and are used to gate a respective transistor switch 31, 32, 33 to cause varying amounts of base bias to be applied to an output transistor 34.
  • the Burst signal is also used to gate a transistor 36 which also varies the amount of base bias on transistor 34.
  • Figure 3 shows a circuit similar to Figure 2 but for the V signal. Equivalent parts of Figure 2 are increased by ten in Figure 3 and further description will be omitted except to say that in this case the R,G,B signals are combined with the sync, blank and burst signals to form Red * , Green * , Blue * , Burst * and Burst * input signals to transistors 43, 42, 41, 46 and 48 respectively.
  • Figure 4 shows the luminance digital to analogue converter circuit which in addition to the Red', Green', Blue' and Sync signals derived from the output of the data selector 16 has a further input HL which is derived from the highlight data bit in the attribute bytes.
  • Red', Green' and Blue' signals are used to gate transistors 53, 52, 51 respectively which are in the emitter circuit of a control transistor 55.
  • the HL signal is used to gate a transistor 56 which affects the base current to the control transistor 55.
  • the sync signal gates a further transistor 57 which is used to directly control the base bias of the output transistor 54.
  • Figure 5 which is made up of Figures 5A, 5B, 5C and 5D shows a detailed circuit diagram showing in detail the construction of the blocks shown in Figure 1 as well as the circuits for producing the correct phase R,G,B signals used in Figures 2, 3 and 4. Where appropriate the blocks are shown in Figure 5 in broken lines and given the same reference numeral as in Figure 1. The circuits shown in Figures 2, 3 and 4 are contained in the block 60 in Figure 5D.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Processing Of Color Television Signals (AREA)
  • Controls And Circuits For Display Device (AREA)

Claims (8)

1. Vorrichtung zum Erzeugen einer farbigen Computer-Anzeige mit einem Speicher zum Speichern einer Vielzahl von ersten digitalen Worten, die jeweils aus einer Vielzahl von binären Einheiten bestehen und eine anzuzeigende Struktur repräsentieren und einer geringeren Anzahl von zweiten digitalen Worten, die jeweils aus einer Vielzahl von binären Einheiten bestehen und die Farbe der anzuzeigenden Struktur repräsentieren, wobei jedes der genannten zweiten digitalen Worte einer Vielzahl von ersten digitalen Worten zugeordnet ist, mit Einrichtungen zum Lesen der ersten und zweiten Worte aus dem Speicher, und einer Einrichtung (16) zum Erzeugen digitaler Farbsignale, welche auf die genannten ersten und zweiten digitalen Worte anspricht, um digitale Farbsignale für einen Abschnitt einer Linie einer Video-Rasterabtastung zu erzeugen, dadurch gekennzeichnet, daß als Speicher ein dynamischer Speicher mit wahlfreiem Zugriff (DRAM) vorgesehen ist, der erste und zweite Plätze zum Speichern der genannten ersten bzw. zweiten Worte aufweist sowie eine Anzahl von Ausgängen (DO-D7), deren Anzahl der Anzahl der binären Einheiten eines digitalen Wortes entspricht, zwei Haltekreise (10, 15 und 11, 12), die jeweils mit den Ausgängen (DO-D7) des Speichers verbunden sind und die jeweils getaktet werden, um das Zugeordnete der ersten und zweiten digitalen Worte zu empfangen, und daß eine Einrichtung zum sukzessiven Adressieren der ersten und zweiten Speicherplätze vorgesehen ist, wodurch von der Einrichtung nacheinander erste und zweite digitale Worte an die Haltekreise abgegeben werden.
2. Vorrichtung gemäß Anspruch 1, wobei einer der zwei Haltekreise (10, 15) einen ersten Haltekreis (15) aufweist zum Empfangen eines ersten digitalen Wortes und zum seriellen Ausgeben von dessen binären Einheiten.
3. Vorrichtung nach Anspruch 2, wobei jedes der zweiten digitalen Worte Daten enthält, die sowohl die Vordergrund- als auch die Hintergrund-Farbinformation repräsentieren, wobei die Farbsignal-Erzeugungseinrichtung (16) einen Daten-Selektor (16) aufweist, der zwei Kanäle in einen umsetzt und auf den logischen Pegel jedes der vom ersten Haltekreis (15) abgegebenen binären Einheiten anspricht, wodurch die dem Vordergrund oder dem Hintergrund entsprechende Farb-Information erzeugt wird.
4. Vorrichtung nach einem der Ansprüche 2 oder 3, wobei der genannte eine der :beiden Haltekreise (10, 15) einen weiteren Haltekreis (10) zwischen den Ausgängen (D0­D7) des Speichers und dem ersten Haltekreis (55) aufweist.
5. Vorrichtung nach Anspruch 4, wobei der andere der beiden Haltekreise (11, 20) eine Reihenschaltung von Haltekreisen aufweist, die zwischen den Ausgängen des Speichers und der Einrichtung (16) zum Erzeugen eines digitalen Signales angeordnet sind.
6. Vorrichtung nach einem der vorhergehenden Ansprüche mit einem Digital/Analog-Wandler zum Erzeugen analoger Farbsignale aus den digitalen Signalen, die vom digitalen Farbsignal-Generator (16) abgegeben werden.
7. Vorrichtung nach Anspruch 6, wobei der Wandler drei Digital/Analog-Konverter aufweist, wovon einer (Fig. 2) dazu dient, ein Analogsignal zu erzeugen, welches ein U-Signal repräsentiert, während ein anderer (Fig. 3) dazu dient, ein Analogsignal zu erzeugen, welches ein V-Signal repräsentiert und während ein anderer (Fig. 4) dazu dient, ein Analogsignal zu erzeugen, welches einem Y-Signal entspricht.
8. Vorrichtung nach Anspruch 6, wobei jeder der Digital/Analog-Konverter einen Ausgangstransistor (34, 44, 54) aufweist, dessen Basis-Vorspannung mittels eines Steuertransistors (35, 45, 55) steuerbar ist, in dessen Emitter-Schaltkreis weitere Schalteinrichtungen (31 bis 36, 36; 41 bis 43; 46, 48; 51 bis 53, 56, 57) geschaltet sind, welche auf die Signale ansprechen, die vom digitalen Farbsignal-Erzeuger (16) abgeleitet werden.
EP19830901331 1982-04-22 1983-04-22 Anzeige für einen rechner Expired EP0107687B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT83901331T ATE35586T1 (de) 1982-04-22 1983-04-22 Anzeige fuer einen rechner.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8211723 1982-04-22
GB8211723 1982-04-22

Publications (2)

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EP0107687A1 EP0107687A1 (de) 1984-05-09
EP0107687B1 true EP0107687B1 (de) 1988-07-06

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EP19830901331 Expired EP0107687B1 (de) 1982-04-22 1983-04-22 Anzeige für einen rechner

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EP (1) EP0107687B1 (de)
JP (1) JPS59500929A (de)
DE (1) DE3377306D1 (de)
WO (1) WO1983003916A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8908980B2 (en) 1997-10-02 2014-12-09 S3 Graphics Co., Ltd. Image codec engine

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591842A (en) * 1983-05-26 1986-05-27 Honeywell Inc. Apparatus for controlling the background and foreground colors displayed by raster graphic system
JPS61130985A (ja) * 1984-11-21 1986-06-18 テクトロニツクス・インコーポレイテツド 多ビツト・ピクセル・データ蓄積装置
JP2501187B2 (ja) * 1985-07-08 1996-05-29 日本電気株式会社 ス−パ−インポ−ズ装置
JPS6358395A (ja) * 1986-08-11 1988-03-14 テクトロニックス・インコ−ポレイテッド カラ−表示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7101932A (de) * 1970-03-28 1971-09-30
GB2044052B (en) * 1978-10-04 1983-08-03 Sharp Kk Instruction controlled audio visual system
JPS5577787A (en) * 1978-12-08 1980-06-11 Matsushita Electric Ind Co Ltd Display unit
US4303912A (en) * 1980-05-19 1981-12-01 Burroughs Corporation Digitally controlled composite color video display system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8908980B2 (en) 1997-10-02 2014-12-09 S3 Graphics Co., Ltd. Image codec engine

Also Published As

Publication number Publication date
EP0107687A1 (de) 1984-05-09
JPS59500929A (ja) 1984-05-24
DE3377306D1 (en) 1988-08-11
WO1983003916A1 (en) 1983-11-10

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