Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Definitions

• the invention relates to a non-linear logic module for generating complex bit sequences.
• an object of the invention to combine modulo-two the outputs of a plurality of register pairs so that one register of each pair is-of selectable variable length and the other register of the pair is of fixed length and so that no two of the plurality of fixed length registers are of the same length and so that no two of the plurality of -variable length registers are of the same length.
• FIGURE 1 is a block diagram of a preferred embodiment of the invention utilizing 14 bit length segmented registers ?
• FIGURE 2 is a table of one-half the permitted sequence combinations for the 14 bit generators of FIGURE 1;
• FIGURE 3 is a partial schematic diagram of the block diagram of FIGURE 1.
• the invention comprises segmented programmable registers 10, 16, 22, 28, 34, 40 and 46 (clock inputs not shown) .
• Each of the segmented registers comprises a fixed length portion and a programmable variable length portion.
• register 10 comprises variable length portion 12 and fixed length portion 14.
• Fixed portion 14 determines the span of delay (in clock periods) between the two sequences to be combined in, for example, multiplier 54.
• the length of the registers of FIGURE 1 are for example only; the length and number of registers being variable to suit a particular application. Note that fixed length portions 14, 20, 26, 32, 38, 44 and 50 of registers 10, 16, 22, 28, 34, 40 and
• O 46 have lengths of 2, 3, 4, 5, 6, 7 and 8 bits, respectively.
• a bit introduced at node 52 of register 10 produces an immediate input to AND gate 54 and an input delayed by two clock times via register portion 14.
• programmable portion 12 of register 10 is arranged to delay an input bit at node 56 by two clock times at node 52.
• other delay times may have been programmed into register portion 12 by using a different output point for wire 58.
• eighth stage 60 of register 12 had been utilized for the output into wire 58, the delay in transit of a bit from input node 56 to node 52 through register segment 12 would have been 8 clock times.
• the other programmable register portions 18, 24, 30, 36, 42 and 48 may be programmed by selection of given register stages from which outputs to wires 62, 64, 66, 68, 70 and 72, respectively would be derived.
• a different tap point is selected for each of the register portions 12, 18, 24, 30, 36, 42 and 48. Now, looking at register portion 12, part of register 10 of FIGURE 1, it may be seen that there are 12 numbered stages there. Since no two full registers may have a tap point at the twelfth stage there is no need to have any other programmable register portion as long as register 12.
• each register portion 12, 18, 24, 30, 36, 42 and 48 is of a unique length but all lengths from 6 through 12 stages are represented.
• the shorter length programmable registers are associated with the lengthier fixed length registers and vice versa. This allows all possible combinations of bit timing since the programmable register length sets the position of the first bit of each bit pair in the output word and the fixed register associated with any given programmable register sets the spacing between that bit pair.
• a bit pair is defined as a given bit and its delayed counterpart. It ma be noted that any given combination of programmable and fixed delay must not exceed the total word length.
• bit 1 appears in positions one and three.
• Bit 1 refers to the first input bit in the bit stream 74 applied to the inputs of the programmable registers. (See FIGURE 1.)
• Bit 2 is the second bit in that stream, and so forth.) This means that there is no delay for the first bit of this pair and the second bit of the pair is delayed two clock times.
• every programmable register has at least a one bit delay, the delay generated if the first output bit is tapped from the first delay stage of the programmable register, this one stage delay is a reference delay and may be considered as zero delay.
• the input bit could be programmed as the first output bit with no delay and some register stages would be eliminated in such a configuration.
• bit 2 appears in positions four and seven of sequence number 1, reference numeral 100.
• the programmable register for the bit 2 pair is arranged for a four clock time delay; that is, the output of the programmable register is taken from the fifth stage.
• the associated fixed length register must then be the three stage fixed length register (20, if the scheme of FIGURE 1 is used) to provide the second bit of the pair in the seventh position.
• This logic may be extended for determination of all programmable register-fixed register combinations for any given sequence number of the table of FIGURE 2.
• the table of FIGURE 2 shows 26 sequences. There are also 26 more reverse sequences, which are not shown, for a total of 52 sequences.
• the partial block diagram of FIGURE 1 also includes multipliers such as 54 and "exclusive OR" adders such as 76 for combining the programmable and fixed register portion outputs and for combining, modulo-two, the outputs of the plurality of segmented registers 10, 16, 22, 28, 34, 40 and 46, for example.
• multipliers such as 54
• "exclusive OR" adders such as 76 for combining the programmable and fixed register portion outputs and for combining, modulo-two, the outputs of the plurality of segmented registers 10, 16, 22, 28, 34, 40 and 46, for example.
• a spare input 80 to one of the modulo-two adders, such as 78 may be provided for the purpose of combining the output bit stream of the system of FIGURE 1 with another bit stream. This may sometimes be desirable where combination with an equally balanced 0-1 bit stream is required, for example.
• FIGURE 3 A preferred embodiment of the partial block diagram of FIGURE 1 is shown in schematic diagram form in FIGURE 3.
• a typical segmented register is shown, 200, 202.
• Switches 204, 206 are connected to the output of each stage 203, 205 of programmable segment 200.
• Switch control register 208 is a static shift register in which a key word may be stored. This key word comprises all "zero" bits except for- a single “one". The single "one" bit in register 208 enables only one of the switches (such as 204 and 206) and thus determines which stage of programmable register 200 will supply the output to multiplier 210 and to input 212 of fixed length register 202.
• Clock lines CLK 01 and CLK 02 supply clock signals for operation of registers 200, 202 and all other such registers.
• registers 200, 202 shift input bit stream 214 one stage to the right.
• the other segmented registers of FIGURE 3 may also be programmed and operate in a similar fashion.
• Exclusive OR gates, such as 216, 218 and 220 serve to add the outputs of the segmented registers, modulo-two and provide the required output sequences at terminal 222 in response to the setting of a given key word into the various static shift registers such as 208.
• Static shift registers, such as 208 may be loaded either serially or in parallel fashion, but they are shown loaded serially in FIGURE 3. If loaded in parallel, the key words may be changed between clock pulse inputs to the segmented registers and new complex sequences may be generated "on-the-fly".
• variable register segment lengths might also be employed.
• simple mechanical switches might be utilized (not shown).
• the art of developing efficient complex sequences which indicate the key words which lead to these sequences, is taught in the prior art. Generation of Binary Sequences With Controllable Complexity, supra.

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• Compression, Expansion, Code Conversion, And Decoders (AREA)

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• 1982
  • 1982-04-05 WO PCT/US1982/000429 patent/WO1983003723A1/en not_active Application Discontinuation
  • 1982-04-05 EP EP19820901569 patent/EP0105258A1/de not_active Withdrawn
  • 1982-04-05 JP JP50156282A patent/JPS59500543A/ja active Pending

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