EP0077332A1 - Decodeur de modulation de largeur d'impulsion - Google Patents

Decodeur de modulation de largeur d'impulsion

Info

Publication number
EP0077332A1
EP0077332A1 EP19820900524 EP82900524A EP0077332A1 EP 0077332 A1 EP0077332 A1 EP 0077332A1 EP 19820900524 EP19820900524 EP 19820900524 EP 82900524 A EP82900524 A EP 82900524A EP 0077332 A1 EP0077332 A1 EP 0077332A1
Authority
EP
European Patent Office
Prior art keywords
capacitor
value
pwm signal
pwm
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19820900524
Other languages
German (de)
English (en)
Inventor
Roy P. Moeller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beckman Coulter Inc
Original Assignee
Beckman Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beckman Instruments Inc filed Critical Beckman Instruments Inc
Publication of EP0077332A1 publication Critical patent/EP0077332A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
    • H03K9/08—Demodulating pulses which have been modulated with a continuously-variable signal of duration- or width-mudulated pulses or of duty-cycle modulated pulses

Definitions

  • the present invention relates to circuits for decoding or demodulating pulse width modulated (PWM) signals.
  • PWM pulse width modulated
  • Pulse width modulation is a method of encoding a sequence of numerical values by modulating the duty cycle of a fixed-frequency square-wave carrier signal. More specifically, the duty cycle of each successive period of the carrier signal is modulated so as to be proportional to the corresponding numerical value in the sequence.
  • the information represented by the sequence of numerical values is typically either a succession of distinct measurement results or else periodic samples of a continuous waveform.
  • a PWM decoder The purpose of a PWM decoder is to recover from the modulated signal the originally encoded sequence of numerical values, typically by generating an analog signal successively proportional thereto.
  • One known PWM decoder comprises a resistor-capacitor integrator circuit. Before each successive period of the PWM signal, the integrator is initialized by discharg ing the integrator capacitor. During the period, a fixed current is supplied to the integrator capacitor during the time the PWM square-wave has one of its two alternating values. At the end of the period, the capacitor voltage is proportional to the duty cycle of the PWM signal during that period, and hence to the value of the encoded information. This capacitor voltage is typically stored by a sample-and-hold circuit so that the integrator can immediately thereafter be initialized to decode the next period of the PWM signal.
  • the present invention is a decoder for pulse width modulated (PWM) signals comprising an integrator and a sample-and-hold circuit wherein the sample-andhold output signal is fed back to the input of the integrator.
  • PWM pulse width modulated
  • One advantage of the present invention is that the integrator need not be initialized periodically. If the integrator is implemented with an integrator capacitor, the capacitor need not be discharged periodically, thereby avoiding offset errors due to the dielectric absorption of the capacitor.
  • FIG. 1 is a waveform diagram of a PWM signal having a fixed repetition period T, each period beginning with a "low" to "high” transition.
  • Figure 2 is a waveform diagram of a PWM signal having a fixed repetition period T, each period beginning with a "high” to “low” transition.
  • Figure 3 is a block diagram of a PWM decoder according to the present invention.
  • Figure 4 is an electrical schematic of the preferred embodiment of a PWM decoder according to the present invention.
  • Figure 1 depicts the waveform of a typical PWM signal.
  • the signal alternates between “high” and “low” values V H and V L at a fixed frequency or repetition rate 1/T, or equivalently, a fixed repetition period T.
  • the duty cycle of each period of the PWM signal is the ratio of the time “t” that the PWM signal is “high” during the period to the total duration "T” of the period.
  • Figure 1 illustrates two periods of a PWM signal having duty cycles of t 1 /T and t 2 /T during the first and second periods, respectively.
  • Each period of the PWM signal shown in Figure 1 consists of a first time interval when the PWM signal is "high”, followed by a second time interval when the PWM signal is "low”.
  • FIG 2 depicts a PWM signal identical to that shown in Figure 1 except that the first and second time intervals are reversed.
  • each period of the PWM signal shown in Figure 2 consists of a first time interval when the PWM signal is "low", followed by a second time interval when the PWM signal is "high".
  • the sum of the durations of the first and second time intervals within each period is the repetition period T of the PWM signal.
  • a PWM signal may be encoded according to either one of the two formats illustrated in Figures 1 and 2.
  • FIG. 3 is a block diagram of a PWM decoder according to the present invention.
  • the PWM decoder receives a PWM signal at input terminal 10 and produces a decoder output signal V o at output terminal 12 whose value during each period of the PWM signal is proportional to the duty cycle of the PWM signal during the preceding period.
  • the PWM decoder includes an integrator 14 that produces an output signal 16 proportional to the time integral of its input signal 18.
  • Sample-and-hold circuit 20 produces the decoder output signal V o by sampling the integrator output signal 16 at the begin ning of each period of the PWM signal 10. More specifically, the decoder output signal 12 equals a proportionality factor G 3 times the value of the integrator output signal 16 at the time of the most recent transition of the PWM signal 10 from its second value to its first value.
  • the integrator input signal 18 is obtained by summing a first value equal to a proportionality factor G, times the input signal 10 and a second value equal to a proportionality factor G 2 times the decoder output signal 12.
  • blocks 22, 24 and 26 are used to represent the proportionality factors G 1 , G 2 and G 3 . While such proportionality factors may be implemented as separate amplifiers, blocks 22, 24 and 26 are more preferably incorporated in the circuits which implement integrator 14 and sample-and-hold 20.
  • example-and-hold 20 may include an amplifier whose gain determines the proportionality factor G 3 . Thus, such an amplifier would be an element of both sample-and-hold 20 and block 26.
  • integrator 14 shown in Figure 4, which includes capacitor 28, amplifier 34, and resistors 38 and 36.
  • the circuit operation will be described more fully below, it may be recognized at this point that the proportionality factors G 1 and G 2 are inversely proportional to the resistances of resistors 38 and 36, respectively.
  • blocks 22 and 24 respectively comprise resistors 38 and 36, such resistors also being elements of integrator 14.
  • V o (-G 1 /G 2 ) [V L + (V H -V L ) (t/T)] (1)
  • V o -V H (G 1 /G 2 ) (t/T) (2)
  • the settling time required for the value V o of the output signal to converge to the values given in Equations (1) and (2) above is determined by the product of the proportionality constants G 2 and G 3 .
  • the PWM decoder is said to be critically damped when the product of G 2 and G 3 equals minus one times the repetition frequency 1/T of the PWM signal.
  • the settling time of the PWM decoder is zero; that is, the value V o of the decoder output signal assumes the values given in Equations (1) and (2) above immediately after each period of the PWM signal, without any initial settling time.
  • Equations (1) and (2) If the product G 2 G 3 differs somewhat from the critical damping value -1/T, a settling time will be required for the output signal V of the PWM decoder to converge to the values given in Equations (1) and (2). The greater the difference between the product G 2 G 3 and the critical damping value, the longer the required settling time. If the product G 2 G 3 is less than or equal to -2/T or is greater than or equal to zero, the PWM decoder will be unstable and the decoder output V o will never converge to a stable value.
  • FIG. 4 shows the preferred embodiment of a PWM decoder according to the present invention.
  • integrator 14 comprises a capacitor 28 connected between inverting input 30 and output 32 of an operational amplifier 34. Because of the high gain of operational amplifier 34, the voltage at the amplifier inverting input 30 essentially equals zero Volts, and the voltage at the amplifier output 32 equals the voltage across the capacitor 28.
  • Sampleand-hold circuit 20 samples the capacitor voltage at the beginning of each period of the PWM signal and produces decoder output voltage V o at output terminal 12 equal to the most recently sampled value of the capacitor voltage.
  • the sample-and-hold circuit 20 should be triggered by each "low” to "high” transition of the PWM signal 10.
  • the sample-and-hold circuit should trigger on “high” to "low” transitions of the PWM signal.
  • Resistor 36 connects between amplifier inverting input 30 and decoder output 12, thereby supplying to capacitor 28 a current proportional to the decoder output voltage V o .
  • resistor 38 connects to amplifier inverting input 30 to supply capacitor 28 a current proportional to the duty cycle of the PWM signal received at input terminal 10.
  • resistor 38 is not connected directly to input terminal 10; instead, resistor 38 is switchably connected to a reference voltage source V R through analog switch 40.
  • Switch 40 is controlled by the PWM signal received at input terminal 10 so as to be closed and opened, respectively, when the PWM signal has its "high” and "low” values . Switch 40 makes the decoder operation indepen dent of the amplitude of the incoming PWM signal by effectively replacing it with one having a fixed high value V R and a fixed low value of zero.
  • the decoder output voltage V converges after an initial settling period to the value given by the following equation wherein R 1 and R 2 denote the resistances of resistors 38 and 36, respectively:
  • V o -V R (R 2 /R 1 ) (t/T) (3)
  • Equation (3) shows that the decoder output voltage V o is directly proportional to the duty cycle t/T of the PWM signal and is independent of the capacitance of capacitor 28.
  • the values of resistor 36 and capacitor 28 determine the stability and settling time of the PWM decoder shown in Figure 4.
  • the decoder will be critically damped and the settling time will be zero if the product of the resistance of resistor 36 and the capacitance of capacitor 28 equals the repetition period T of the PWM signal.
  • the settling time of the decoder will increase as this resistance-capacitance product deviates from the critically damped value.
  • the decoder will be stable so long as the resistance-capacitance product is less than two times the critically damped value, that is, less than twice the repetition period T.
  • the present invention thereby avoids offset errors inherent in prior art designs because of dielectric absorption which prevents the integrator capacitor from being completely discharged.
  • Another advantage of the described PWM decoder is that the value to which the decoder output voltage settles is independent of the capacitance of the integrator capacitor. As a result, the accuracy of the decoder will not be degraded by the use of an integrator capacitor subject to thermal drift and having only ordinary capacitance tolerances.
  • Another advantage of the present invention is that the decoder output is proportional to the true duty cycle t/T.
  • many prior art designs produce an output proportional only to the duration "t" of the "high” interval within each period of the PWM signal, independent of the repetition period T.

Landscapes

  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Un decodeur pour des signaux modules par largeur d'impulsion (PWM) comprend un integrateur (14) et un circuit d'echantillonnage-blocage (20) ou le signal de sortie d'echantillonnage-blocage est renvoye a l'entree de l'integrateur (14). Aucune initialisation periodique de l'integrateur (14) n'est requise. Les gains de l'integrateur (14) et le circuit d'echantillonnage-blocage (20) ainsi que la capacitance du condensateur (28) de l'integrateur n'affectent que le temps de stabilisation du decodeur, non la valeur a laquelle la sortie du decodeur (Vo) se stabilise finalement
EP19820900524 1980-12-29 1981-12-28 Decodeur de modulation de largeur d'impulsion Withdrawn EP0077332A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22086980A 1980-12-29 1980-12-29
US220689 1980-12-29

Publications (1)

Publication Number Publication Date
EP0077332A1 true EP0077332A1 (fr) 1983-04-27

Family

ID=22825347

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19820900524 Withdrawn EP0077332A1 (fr) 1980-12-29 1981-12-28 Decodeur de modulation de largeur d'impulsion

Country Status (2)

Country Link
EP (1) EP0077332A1 (fr)
WO (1) WO1982002300A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643502B4 (de) * 1996-10-21 2007-05-16 Bosch Gmbh Robert Verfahren zur Decodierung eines digitalen Signals, Bussystem und Peripheriegerät hierfür
CN103091561B (zh) * 2012-12-26 2015-02-11 常州同惠电子股份有限公司 从交直流叠加信号中提取直流信号的装置及方法
ES2911285T3 (es) 2014-08-08 2022-05-18 Pr Electronics As Sistema y método para la modulación y demodulación

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1159073A (en) * 1967-03-28 1969-07-23 Standard Telephones Cables Ltd P.C.M. Decoders.
US3571736A (en) * 1969-01-14 1971-03-23 Ibm Demodulator for pulse width modulated signals
US3624529A (en) * 1969-11-25 1971-11-30 Chandler Evans Inc Pulse width signal demodulator
US3886463A (en) * 1974-05-09 1975-05-27 Us Air Force Pulse width detector circuit
SU589689A1 (ru) * 1976-03-17 1978-01-25 Ленинградский Ордена Ленина Электротехнический Институт Имени В.И.Ульянова (Ленина) Демодул тор импульсов, модулированных подлительности
JPS6017167B2 (ja) * 1978-05-23 1985-05-01 ソニー株式会社 パルス巾変調信号増幅回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8202300A1 *

Also Published As

Publication number Publication date
WO1982002300A1 (fr) 1982-07-08

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