EP0073916A2 - Steuereinrichtung zur individuellen Kontrolle der Farben der Zeichenkontur und des Hintergrundes eines auf einem Farbfernsehempfänger oder einem Monitor angezeigten Zeichens - Google Patents

Steuereinrichtung zur individuellen Kontrolle der Farben der Zeichenkontur und des Hintergrundes eines auf einem Farbfernsehempfänger oder einem Monitor angezeigten Zeichens Download PDF

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Publication number
EP0073916A2
EP0073916A2 EP82106645A EP82106645A EP0073916A2 EP 0073916 A2 EP0073916 A2 EP 0073916A2 EP 82106645 A EP82106645 A EP 82106645A EP 82106645 A EP82106645 A EP 82106645A EP 0073916 A2 EP0073916 A2 EP 0073916A2
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EP
European Patent Office
Prior art keywords
character
color
font
background
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP82106645A
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English (en)
French (fr)
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EP0073916A3 (en
EP0073916B2 (de
EP0073916B1 (de
Inventor
Jesus Andres Saenz
Mark Edward Dean
David Allen Kummer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Publication date
Priority claimed from US06/292,074 external-priority patent/US4442428A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0073916A2 publication Critical patent/EP0073916A2/de
Publication of EP0073916A3 publication Critical patent/EP0073916A3/en
Application granted granted Critical
Publication of EP0073916B1 publication Critical patent/EP0073916B1/de
Publication of EP0073916B2 publication Critical patent/EP0073916B2/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/024—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour registers, e.g. to control background, foreground, surface filling

Definitions

  • This invention relates generally to color television, and, more particularly, to a circuit for independently controlling the colors of the font and background of a character displayed on the cathode ray tube (CRT) screen employed in a conventional television receiver or monitor as used in a data processing system, such as a small personal computer, for displaying computer-generated alpha-numeric and graphic data.
  • CTR cathode ray tube
  • a data processing system such as a small personal computer, employing a conventional television receiver or a monitor for displaying characters in a color determined by computer-generated digital color signals
  • a conventional television receiver or a monitor for displaying characters in a color determined by computer-generated digital color signals
  • an 8-bit character attribute code which is applied to the existing multiplexer or color video control unit in the data processing system.
  • One part of this attribute code is dedicated to the color of the font ("foreground") of each character, and the other part of the code is dedicated to the color of the background of the character, whereby the colors of both the font and background of each character within a word are independently controlled.
  • the two portions of the code are independently selectable so that all possible combinations of font and background color are possible. In particular, if both the font and background colors are selected to be the same, the character which otherwise would be displayed on the CRT screen is invisible to a viewer.
  • Figure 1 is a block diagram of a portion of a data processing system, such as a personal computer, in which alpha-numeric and graphic data, generated by a keyboard or other components of the system, are displayed on a cathode ray tube, such as a conventional television receiver or monitor.
  • a data processing system such as a personal computer
  • alpha-numeric and graphic data generated by a keyboard or other components of the system, are displayed on a cathode ray tube, such as a conventional television receiver or monitor.
  • a central processing unit (CPU) 10 is connected to a three- state system bus 12 including a 8-bit data bus.
  • a character such as one entered by a keyboard coupled to the bus, is to be displayed on the cathode ray tube (CRT) of a conventional TV receiver 14 designed in accordance with the National Television Standards Committee (NTSC) standards.
  • a conventional CRT controller 16 such as a Motorola 6845 chip, controlled by CPU 10 via the bus 12, generates the CHARACTER ADDRESS on output line 18, CHARACTER SCAN on line 24, and the television frequency components on lines 20 and 22.
  • a -BLANK signal is produced on line 20, and the scanning pulses are produced on line 24 and applied to a character generator (ROM) 28.
  • ROM character generator
  • An 8-bit character code is fetched from a random access memory (RAM) 30 at the specified character address.
  • An 8-bit attribute code is also fetched, and four of these bits designate the color of the character to be displayed, i.e., the foreground color of the character, as opposed to the background color of the character.
  • the four character color bits are applied to a multiplexer (MUX) 32, such as a 74LS157 chip, which outputs the red (R), green (G), blue (B) and intensity (I) signals from which there is derived the composite video color signal to be applied to the TV receiver.
  • MUX multiplexer
  • Multiplexer 32 is under the control of the serial character dots from the 8-to-1 parallel-to-serial converter 34 connected to the output of the character generator 28.
  • the digital R, G, B and I signals on the output of multiplexer 32 are applied as inputs to a composite video generator 38 which produces the composite video color signal which can be used directly by a conventional composite monitor or, after being modulated by an R.F. modulator 13, by TV receiver 14 to display the colored character, or as inputs to the drivers 40 of a conventional direct drive TV monitor which operates directly from the R, G, B and I signals without the RF modulation required by the TV receiver 14, but which requires externally supplied synchronizing and blanking signals.
  • Figure 2 is a logic and schematic circuit diagram of the composite video generator 38 of Figure 1, and functions directly to convert the R, G, B and I digital color signals on the output of MUX 32 to a composite video color signal which can be utilized by the TV receiver 14 to display the character image having the color designated by a particular set of digital color signals.
  • a line is UP, i.e. has a logical value of 1 (+5 volts), when the indicated signal is present, and is DOWN, i.e. has the logical value of 0 (0 volt), when that signal does not exist.
  • the circuit of Figure 2 consists of three digital delay devices in the form of three 74LS74 edge-triggered D-type latches or flipflops 50, 52 and 54, each of which has a D input, a clock (CLK) input, a Q set output, and a Q reset output.
  • the outputs of the three latches are connected as six inputs to an 8-to-1 74LS151 multiplexer 56 to whose output Y are switched, under the control of digital color signals B, G, R applied to its SELECT terminals A, B and C, respectively, individual ones of the eight phase-shifted color subcarriers appearing on the eight inputs of the multiplexer.
  • the 0 input terminal of multiplexer 56 is grounded and represents the color black, and the white input is connected to +5 volts.
  • the S (strobe) terminal of the multiplexer chip 56 is not used and is grounded.
  • a 14.318 MHz clock signal from the system bus is applied to the CLK terminal of latches 50 and 52, and inverted and applied to the CLK terminal of latch 54.
  • the system clock signal is also divided by four in a frequency divider 58 to produce the 3.58 MHz (actually 3.5795) NTSC color subcarrier signal.
  • a delay of one clock period of the 14.318 MHz signal corresponds to a 90° phase shift of the 3.58 MHz subcarrier.
  • One-half of the 14.318 MHz clock period thus correspond to a 45° phase shift of the subcarrier.
  • the Q or 0° phase output of latch 50 is applied to the D input of latch 52, and the Q or 90° delay output of latch 52 is applied to the D input of latch 54.
  • the subcarrier signal is synchronized by the rising edges of the clock signal. Because of the inherent delay between the inputs and the outputs of such D-type latches, the zero phase output of latch 50, for example, will be slightly delayed from its D input. Thus, when the Q output of latch 50 is applied to the D input of latch 52, it will no be up for the first rising edge of the clock signal which is also applied to latch 52. Thus, the outputs of latch 52 will be delayed by ninety degrees relative to those of latch 50. Similarly, a 45° phase shift occurs between the outputs of latches 52 and 54; that is, when the Q output of latch 52 goes high, the Q output of latch 54 will go high one-half of the 14.318 MHz period later to produce the 45° phase shift. The same operation occurs for the Q outputs of latches 52 and 54.
  • the two outputs of latch or flip-flop 50 provide a 3.58 MHz color subcarrier signal at both, 0° phase shift (yellow, brown, burst) and also 180° phase shift (blue, brigth blue).
  • Latch 52 delays the 0° phase shift signal from latch 50 and provides a 3.58 MHz signal at 90° phase shift (red, pink) and at 270° phase shift (cyan, bright cyan).
  • Latch 54 delays the 90° phase shift signal from latch 52 by 45°, and its outputs provide a 3.58 MHz signal at 135° phase shift (magenta, bright magenta) and at 315° phase shift (green, bright green).
  • phase-shifted subcarriers at the output Y of multiplexer 56 are passed through a buffer 60 and a 2.2 K resistor to the summing node 62 connected to the base of an NPN emitter- follower transistor 64 whose emitter-resistor output contains the composite video color signal which is applied through R.F. modulator 13 to the input terminals of the TV receiver 14.
  • Also connected to summing node 62 via corresponding buffer 66, 68 and 69 and corresponding summing resistors having ohmic values of 3.3K, 13K and 4.7K are the -SYNC and -BLANK signals from the CRT controller 16 and the +INTENSITY (I) signal from the color video control circuit or multiplexer 32 of Figure 1.
  • the OR gates 70 and 72 are used to select the 3.58 MHz 0° phase shift signal during BURST time to provide the color burst signal.
  • the -SYNC signal is a composite of the horizontal and vertical synchronizing pulses. In the steady state condition, i.e. when the T.V. screen is black, the Y output is 0, -SYNC is 1, -BLANK is 1, and I is 0.
  • Figure 3 shows the eight color attribute bits applied to the inputs of the 74LS151 multiplexer 32 to produce the red (R), green (G), blue (B) and intensity (I) digital color signals which are applied to the composite video generator 38 to produce the video composite color signal as described in detail with reference to Figure 2.
  • the intensity signal (I) produces a D.C. level which produces "brighter” versions of the eight colors which are derived from the three basic colors of blue, green and red.
  • the eight character color attribute bits (four font or foreground color bits and four background color bits) are applied to the inputs of the multiplexer 32 and are selectively switched to the output lines of the multiplexer under the control of the serial character dots from the parallel to serial converter 34.
  • Figure 3 illustrates the format of the eight bit attribute code which is fetched from the RAM 30 and applied to the multiplexer 32.
  • Figure 4 illustrates the relative timing of the foreground (font) and the background color signals in the horizontal and vertical scannings of a CRT for a typical 7x7 character block for the character "A".
  • the shaded areas represent font or foregound times, and the unshaded areas represent background times.
  • the attribute byte also can be used to render a character invisible on the display screen by choosing the foreground (font) and background colors to be the same.
  • a separate DON'T DISPLAY code and hardware were required to prevent display of a character.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Processing Of Color Television Signals (AREA)
EP19820106645 1981-08-12 1982-07-23 Steuereinrichtung zur individuellen Kontrolle der Farben der Zeichenkontur und des Hintergrundes eines auf einem Farbfernsehempfänger oder einem Monitor angezeigten Zeichens Expired EP0073916B2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US29206781A 1981-08-12 1981-08-12
US292067 1981-08-12
US06/292,074 US4442428A (en) 1981-08-12 1981-08-12 Composite video color signal generation from digital color signals
US292074 1981-08-12

Publications (4)

Publication Number Publication Date
EP0073916A2 true EP0073916A2 (de) 1983-03-16
EP0073916A3 EP0073916A3 (en) 1984-06-06
EP0073916B1 EP0073916B1 (de) 1988-05-25
EP0073916B2 EP0073916B2 (de) 1992-01-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP19820106645 Expired EP0073916B2 (de) 1981-08-12 1982-07-23 Steuereinrichtung zur individuellen Kontrolle der Farben der Zeichenkontur und des Hintergrundes eines auf einem Farbfernsehempfänger oder einem Monitor angezeigten Zeichens

Country Status (4)

Country Link
EP (1) EP0073916B2 (de)
DE (1) DE3278546D1 (de)
HK (1) HK4290A (de)
SG (1) SG62089G (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0129712A2 (de) * 1983-05-26 1985-01-02 Honeywell Inc. Farbsteuerungssystem für ein grafisches Rasteranzeigesystem
WO1995000218A2 (en) * 1993-06-18 1995-01-05 Mendes Inc. Automated bowling scoring system
EP0989536A1 (de) * 1983-12-26 2000-03-29 Hitachi, Ltd. Graphisches Musterverarbeitungsgerät

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668686A (en) * 1969-06-06 1972-06-06 Honeywell Inc Control apparatus
US4149152A (en) * 1977-12-27 1979-04-10 Rca Corporation Color display having selectable off-on and background color control
DE2940322A1 (de) * 1978-10-04 1980-08-21 Sharp Kk Ton-bild-system
FR2477745A1 (fr) * 1980-03-04 1981-09-11 Thomson Brandt Dispositif d'affichage graphique en couleurs

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668686A (en) * 1969-06-06 1972-06-06 Honeywell Inc Control apparatus
US4149152A (en) * 1977-12-27 1979-04-10 Rca Corporation Color display having selectable off-on and background color control
DE2940322A1 (de) * 1978-10-04 1980-08-21 Sharp Kk Ton-bild-system
FR2477745A1 (fr) * 1980-03-04 1981-09-11 Thomson Brandt Dispositif d'affichage graphique en couleurs

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0129712A2 (de) * 1983-05-26 1985-01-02 Honeywell Inc. Farbsteuerungssystem für ein grafisches Rasteranzeigesystem
EP0129712A3 (de) * 1983-05-26 1989-03-01 Honeywell Inc. Farbsteuerungssystem für ein grafisches Rasteranzeigesystem
EP0989536A1 (de) * 1983-12-26 2000-03-29 Hitachi, Ltd. Graphisches Musterverarbeitungsgerät
US6492992B2 (en) 1983-12-26 2002-12-10 Hitachi, Ltd. Graphic pattern processing apparatus
WO1995000218A2 (en) * 1993-06-18 1995-01-05 Mendes Inc. Automated bowling scoring system
WO1995000218A3 (en) * 1993-06-18 1995-05-04 Mendes Inc Automated bowling scoring system

Also Published As

Publication number Publication date
EP0073916A3 (en) 1984-06-06
EP0073916B2 (de) 1992-01-29
DE3278546D1 (en) 1988-06-30
SG62089G (en) 1990-01-26
HK4290A (en) 1990-01-25
EP0073916B1 (de) 1988-05-25

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