EP0067982A2 - Configuration pour microprocesseur, particulièrement pour l'application dans des systèmes de multimicroprocesseurs - Google Patents

Configuration pour microprocesseur, particulièrement pour l'application dans des systèmes de multimicroprocesseurs Download PDF

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Publication number
EP0067982A2
EP0067982A2 EP82104786A EP82104786A EP0067982A2 EP 0067982 A2 EP0067982 A2 EP 0067982A2 EP 82104786 A EP82104786 A EP 82104786A EP 82104786 A EP82104786 A EP 82104786A EP 0067982 A2 EP0067982 A2 EP 0067982A2
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EP
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Prior art keywords
circuit
control
signal
bus
register
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EP82104786A
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German (de)
English (en)
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EP0067982A3 (fr
Inventor
Wolfgang Dipl.-Ing. Matthes
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Robotron VEB
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Robotron VEB
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Definitions

  • the invention relates to a microcomputer arrangement, preferably for use in multi-microcomputer systems, in which such arrangements are connected to one another and to other devices via a common time-division multiplex bus and which consist of a processing unit (CPU), I / O circuits and read-only memories (ROM) and read / write memories (RAM).
  • CPU processing unit
  • I / O circuits I / O circuits
  • ROM read-only memories
  • RAM read / write memories
  • Arrangements of this type can be used in conjunction with other devices to build up relatively complex digital systems, for example peripheral devices for EDP systems, small computer systems, machine controls and the like.
  • a characteristic example is an operating and service processor for EDP systems, which is set up for a variety of functions, e.g. B. for the communication "operator / operating system", for the communication "maintenance technician / hardware ', for the automated hardware diagnosis, for remote diagnosis etc.
  • microcomputer systems are commercially available that allow the coupling of several microcomputers.
  • a widely used system allows coupling via a time-division multiplex bus, which permits "multi master” operation.
  • This bus system is shown in the Rolander font “Intel Multibus Interfacing", application font AP 28, INTEL 1977.
  • Other systems only allow coupling via I / O circuits, as e.g. B. in the article “MStekro computer coupling via input and output ports” (radio television electronics, 29 (1980), Issue 8, pp 489 ff) is described. You can use it to build multi-microcomputer systems, but you have a choice the software organization is subject to many restrictions, so that certain advantageous organizational principles cannot be realized.
  • the object of the invention is to specify the structure of a microcomputer arrangement, which is designed for connection to other arrangements via a common time-division multiplex bus, and the specific internal switching means which allow the implementation of effective forms of software organization with the greatest possible freedom of movement for the hardware configuration and software organization within the framework of a multi-microcomputer arrangement .
  • bus lines are arranged between the internal data bus and the coupling stages for the data lines of the external bus system, to which control registers, a bus address register and an error register are connected in addition to the RAM and which are connected to an external connection in that these bus lines are connected to inputs of the I / O circuits, that the switching stages for the address lines of 1 external bus system in their lower positions with portions of the internal address bus and in their higher positions with portions of the Busdressnregisters are connected, that the address inputs of the RAM a selection circuit is arranged upstream, which is connected to output signals of the coupling stages and to parts of the internal address bus, that this selection circuit is further followed by a decoding circuit to which the selection signals of the RAM and the registers mentioned are connected, that the CPU has a Waiting signal circuit is arranged upstream, with output signals of a decoding circuit connected to the internal address bus, which is connected both to the master request circuit and to the switching circuit, with output signals of the switching circuit and the sequence control circuit, with parts
  • the decoding circuit downstream of the selection circuit is preferably designed in such a way that disjunctive connections of selection signals of a part of the control registers and of the bus address register and of selection signals are provided for defined memory locations of the RAM.
  • the switching circuit is designed as a priority switch, and the outputs of which are arranged downstream of one of the error detection circuits, and this is designed as a coincidence detector for the output signals of the switching circuit.
  • the wait signal circuit is designed in such a way that the wait signal for the CPU is formed by the disjunctive linking of the output signals from four flip-flops and the wait signal of part of the I / O circuits, two of the flip-flops mentioned being connected to parts of the control lines of the external bus system, that in the connections of these two flip-flops to the wait signal of the CPU a conjunctive link with a bit position of one of the control registers is arranged, that the other two flip-flops are connected to output signals of the decoding circuit, that the first of these flip-flops with the response and confirmation signals of the control lines of the external Bus system is connected and that the second of these flip-flops is connected to output signals of the switching circuit and the sequence control circuit.
  • the connections between the control registers and the sequence control circuit are designed such that a link between a bit position of one of the control registers and an input signal of a flip-flop is provided, which is followed by the enable signal of the control lines of the external bus system.
  • the coupling stages for the connection between the data bus of the CPU, the bus lines and the data lines of the external bus system are designed such that the control inputs of the first coupling stage are preceded by the write control signal of the CPU and control signals of the master request circuit and the switching circuit and that the control inputs of the second coupling stage are included the write control signal of the CPU in conjunctive linkage with the control signal of the master request circuit as well as with the read control signal disjunctively associated with slave accesses of the external bus system and with the disjunctive linkage of control signals of the master request circuit and the switching circuit.
  • the reset signals for the hardware of the arrangement are designed such that all switching means, including the first control register, are connected to a reset line which is connected to the external bus system and the diagnostic connection, and that all switching means, with the exception of the first control register, are connected to a further reset signal , which is formed from the conjunctive linkage of the slave request signal from the address comparator with a further reset line of the external bus system.
  • a processing unit 1 (hereinafter referred to as CPU) is provided, which is connected to an internal data bus 2 and to an internal address bus 3.
  • a waiting signal circuit 4 is arranged upstream of the WAIT input of the CPU 1.
  • the CPU 1 is also followed by control lines which are connected to the various complexes of the arrangement. These connections are not shown in Fig. 1.
  • the internal data bus 2 is with the I / O circuits
  • ROM read-only memory
  • bus lines 12 are routed to an externally accessible diagnostic connection 19 and connected to the data lines 21 of the external bus system via a coupling stage 20.
  • a master control circuit 28, a switching circuit 29 and a sequence control circuit 30 are provided for controlling and coordinating the internal processes and the control sequences of the external bus system. Both the master control circuit 28 and the switching circuit 29 are connected to the decoding circuit 24 and, via parts of coupling stages 31, to some of the control lines 32 of the external bus system. Some of the output signals of the sequence control circuit 30 are also connected to control lines 32 of the external bus system via further parts of the coupling stages 31. In detail, the connections of the external bus system to the switching circuit 29 are carried out in such a way that an address comparator 33 is interposed, which is also connected to parts of the coupling stage 26.
  • the sequence control circuit 30 is also connected to a bit position of the DIAG MODE register 14.
  • a refresh address counter 34 is provided and connected upstream of the selection circuit 25.
  • An output signal of the refresh address counter 34 is connected to the switching circuit 29. Besides, this is out Downstream signal an error detection circuit 35.
  • the error detection circuit 35, a further error detection circuit 36 and a memory protection device 37 are connected to the HDW ERROR register 18.
  • the HDW ERROR register is preceded by a signal from the diagnostic connection 19.
  • the registers 14, 15, 16, 18 and the diagnostic connection 19 are each connected to an output signal of a decoding circuit 38 which is arranged downstream of the selection circuit 25.
  • the arrangement is based on a commercially available microprocessor system, the
  • a device can access memory locations and registers of a selected other device. If a device is selected as a slave, it must enable the external bus system to access it without affecting the internal processes in principle (with the exception of a possible time delay). In the arrangement, RAM 13 and registers 14, 15, 16, 18 are accessible for slave access. Furthermore, it is possible to write information into the part of the I / O circuit (PIO) 9 which is connected to the bus lines 12.
  • PIO I / O circuit
  • the detailed structure of the external bus system can be selected within relatively wide limits. It is possible to use a bus system known per se, u. Some additional control lines may need to be inserted. Such a bus system is e.g. B. in the font by Rolander, "Intel Multibus Interfacing", application font AP 28, INTEL 1977, is shown.
  • bus system for connecting logical function modules
  • WP G06f / 227 967/4 bus system for connecting logical function modules
  • a complex one The system can be constructed by connecting several microcomputer arrangements to the bus system together with other devices.
  • Fig. 3 shows the structure of the CPU address for ROM access.
  • the ROM 10 has a total capacity of 4 kBytes, implemented by 4 MOS circuits of 1 kByte each.
  • the CPU address allows the addressing of 2 kBytes, i. H. of 2 MOS circuits.
  • the selection of which of the two physically installed 2k areas is addressed is determined by a bit position of the CONTROL register 15.
  • the address bits 12, 11 are reserved and can be used to increase the capacity of a ROM memory to 8 kbytes if circuits with a correspondingly higher capacity are used.
  • the ROM 10 can comprise a total of 16 kbytes.
  • Fig. 4 shows the structure of the CPU address for RAM access.
  • the RAM 13 has a capacity of 32 kBytes, which is realized with dynamic 16 kBit-MOS circuits. These circuits require the time-multiplexed supply of the address in the form of 27-bit sections (ROW ADRS, COLUMN ADRS). 18 circuits are installed, with one parity bit per byte. For this purpose, the corresponding parity generator and parity control circuits (PG, PC) are associated with the RAM 13. This bit position per byte can be used in a special mode under the control of the DIAG MODE register 14 and the CONTROL register 15 for diagnostic purposes in order to trigger a "comparison stop".
  • PG parity generator and parity control circuits
  • Fig. 5 shows the structure of the CPU address for register access.
  • the individual registers are addressed as follows:
  • the DIAGNOSTIC INPUT and DIAGNOSTIC OUTPUT registers are not included in the arrangement itself. Rather, it is provided that these registers are located on an external device ("diagnostic adapter") which can be plugged into the diagnostic connection 19.
  • the arrangement is designed in such a way that the corresponding register selection signals for diagnostic; see connection 19 are performed.
  • the external bus system itself requires a 20-bit address. Since the CPU 1 can only deliver the lower 14 bits, the remaining 6 bits are supplied by the assignment of the BUS ADRS register 16. The 4 most significant bits are used to select the slave on the bus,
  • the two least significant bits indicate the address of one of 4 segments in the address space of the slave device to be selected. Each of these segments can have a maximum of 16 kbytes. The following 4 bits indicate the address of the slave device to be selected on the external bus system.
  • Bit 6 indicates that an interrupt is to be triggered in the slave device to be selected in the following cycle.
  • the effect of such an interrupt in the respective slave device depends on the type of this device. It is an arrangement according to the invention voltage, an interrupt causes an information transfer to the part of the I / O circuit (PIO) 9 which is connected to the bus lines 12.
  • the I / O circuit 9 is usually programmed so that this information transmission triggers an interrupt in the CPU 1.
  • the design of the decoding circuit 22 for the I / O circuits 5 ... 9 is not described in detail, since it largely depends on the microprocessor circuit system used.
  • the request signals MASTER REQUEST, LOCAL ACCESS of the decoding circuit 24 act directly on flip-flops 39, 40.
  • the CPU 1 thus goes into the waiting state immediately after submitting the respective request.
  • the wait state is only exited when the relevant request has been met.
  • flip-flop 39 is reset when the external bus system signals the end of the bus cycle via the REPLY response line and the ACKNOWLEDGE confirmation line.
  • Flip-flop 40 is reset when the sequence control circuit 30 issues the end signal (END) in a local access (LOCAL CYCLE).
  • the output signal of the AND gate 43 is also used in inverted form to allow local access to the registers 14 ... 16, 18 or to the RAM 13 (LOCAL REQUEST ENABLE). This is necessary because the sequence controller 30 may only start a cycle if it can be ended again in a short time, since otherwise the access to the arrangement could be completely blocked.
  • a signal SIO WAIT is provided, which is directly linked to the WAIT signal of the CPU 1.
  • the "wait" outputs of those of the I / O circuits 5 ... 9, which have the possibility of operating in the "wait” mode are combined according to the "wired or” principle.
  • This mode can be used to control peripheral devices. This is particularly advantageous for the fast transmission of connected data streams, since the data rate in this mode corresponds practically directly to the command execution speed and no additional commands are necessary for organizational purposes (in contrast to the interrupt or query principle).
  • the corresponding programs for this are processed from the ROM 10, so that other devices can access the RAM 13 simultaneously with this data transport.
  • the request signal MASTER REQUEST of the decoding circuit 24 acts on a request flip-flop 44 which excites a request signal (REQUEST) of the external bus system.
  • the master selection itself takes place by means of a “looped through” request line (SELECT, SELECT PROPAGATE), a selection flip-flop 45 being activated when the selection is successful, which in turn activates the “busy” line (BUSY) of the external bus system.
  • this mode of operation is typical of many bus systems which can be used in connection with the arrangement according to the invention.
  • the preferred bus system also has the following features related to
  • Each master cycle is ended in that the arrangement receives either the response signal REPLY or the release signal RELEASE from the respective slave and that the confirmation signal ACKNOWLEDGE is active for this purpose.
  • the request signal SLAVE REQUEST is connected in a conjunctive link to the output of the part of the coupling stages 31 which connects the BUSY signal to the external bus system and the output of the address comparator 33.
  • the address comparator 33 is connected to the parts of the coupling stages 26 which connect the highest 4 bits of the address lines (ADRS 19-16) to the external bus system. Both parts of the coupling stages 26, 31 are in the "Receive from external bus system" mode, so that if the address signals supplied by the bus are the same as a set fixed address, the BUSY signal causes SLAVE REQUEST to be switched on.
  • Fig. 17 shows the formation of the reset signals for the hardware.
  • the reset pulses are supplied by the external bus system.
  • RESET becomes active in general initial situations, e.g. B. when turning on the power.
  • This signal can also be supplied by the pluggable diagnostic adapter will.
  • SELECTIVE RESET only works in conjunctive linkage with the SLAVE REQUEST signal, i.e. only selectively if the arrangement via the bus has been selected as a slave. This signal is emitted if certain sequences are to be forced in the arrangement, for example in the context of error handling in the overall system.
  • the HDW RESET signal becomes effective with each reset. It causes the entire arrangement, with the exception of the CONTROL register 15, to be reset.
  • the CONTROL REG RESET signal causes the CONTROL register 15 to be reset. With each reset, the CPU 1 starts the program work from address 0 with programs from the ROM 10.
  • the general reset is the first area of the ROM 10 that generally contains the initial test routines. In the case of a selective reset, which is only given when the system is in its normal operating state, the CONTROL register 15 is not cleared. In the normal operating state, the INITIALIZED bit is always set, so that the program processing starts from address 0 of the second area of the ROM 10. This generally contains error handling and restart routines.
  • the cycle register 51 is only cleared when the cycle in question has ended.
  • the control signals supplied by the shift register 52 are used to control the RAM 13, to generate write pulses for the registers 14 ... 16, 18 etc.
  • the RAM 13 is an arrangement of dynamic 16 kbit MOS memory elements which is time-multiplexed Address feed and various strobe pulses require.
  • the shift register supplies both the strobe pulses (RAS, CAS) and the address switching signal (SWITCH ADRS) for the selection circuit 25.
  • clock pulses for the RAM output register 17 RAM write pulses and load pulses for the various other registers are derived from combinatorial combinations which are not shown.
  • the decoding circuit 38 shows a part of the decoding circuit 38 with an upstream part of the selection circuit 25. It is the part in which the most significant address bits are evaluated in order to select whether the hardware registers or the blocks of the RAM 13 are to be accessed. Access to the undefined address area leads to excitation of the ACCESS ERROR error signal, which is connected to the HDW ERROR register 18.
  • the RAM 13 consists of two blocks of 16 kbytes each, the selection being made by selectively acting strobe signals RASO, RAS1.
  • RASO is also issued for register access. It is characteristic that a general permission signal for RAM accesses (RAM ACCESS) is formed by disjunctively linking the two selectively acting strobe signals RASO, RAS1 with the conjunctive linking of the register access signal (REGISTER ACCESS) with the low-order address signal RAM ADRS 2 of the selection circuit 25.
  • RAM ACCESS a general permission signal for RAM accesses
  • the nissignal RAM ACCESS controls the output of write pulses for the RAM 13 during write operations and the loading of the RAM output register 17 and its control to the bus lines 12 during read operations.
  • the coupling stage 11 is switched on when the CPU 1 wants to carry out an access and either; the master control circuit 28 or the switching circuit 29 emits the corresponding control signal MASTER BUSY or LOCAL CYCLE.
  • the bus lines 12 are thus connected to the data bus 2 of the CPU 1.
  • the direction of the information transport is determined by the assignment of the write signal WRITE of the CPU 1.
  • the coupling stage 20 is switched on when the connection to the external bus system is required. This is the case for both master and slave access (MASTER BUSY or SLAVE CYCLE).
  • the direction of the information transport is determined by the write signal WRITE of the CPU 1 for master accesses and by the received read signal of the external bus system READ (RECEIVED) for slave accesses.
  • FIG. 22 illustrates the connection of the coupling stages 26 for the lower 16 bits of the address lines 27 of the external bus system (this is for the higher 4 bits already shown in Fig. 17).
  • the external bus system is only used for master access.
  • the addresses supplied by the external bus system are only received with slave accesses and routed to the selection circuit 25 (BUS ADRS 15-0).
  • the formation of the enable signal MASTER OR SLAVE can be seen in FIG. 21.
  • READ, WRITE, INTERRUPT are reversed in the same way as the address signals in FIG. 22.
  • READ and WRITE are supplied directly by the CPU 1, and the interrupt signal is formed by bit position 6 of the BUS ADRS register 16.
  • the termination signals REPLY and RELEASE are placed on the bus for slave access and received by the bus for master access.
  • the SLAVE ERROR bus line is connected in the same way. In the case of slave accesses, it is excited by the overall error signal ERROR of the arrangement (the explanation of this signal will be given with reference to FIG. 27).
  • the received signal SLAVE ERROR (RECEIVED) can be used, for example, to switch off the BURST MODE signal (see also Fig. 16).
  • the inverted output carry forms the error signal PROTECT VIOLATION in conjunctive association with the inverted output signal NON EXECUTIVE STATE of the flip-flop 41 of the wait signal circuit 4, the write control signal WRITE OPERATION and the disjunctive association the RAM access signals RAM ACCESS 1, 2 from the decoding circuit 38 shown in FIG. 20.
  • the memory protection takes place in that the RAM 13 is divided into 16 segments of 2 kbytes each.
  • Segment 0 is always protected. It is therefore suitable ; preferably to accommodate important constant tax information for the organizational and operating software.
  • a switching error (ARBITRATION CHECK) is detected when the cycle register 51 of the switching circuit 29 carries more than one output signal.
  • the error detection circuit 36 is designed as a coincidence detector. This is brought about by the paired conjunctive linking of all output signals of the cycle register 51, all of these conjunctive links being disjunctively arranged upstream of an error flip-flop 55.
  • the error flip-flop 55 is connected to bit position 2 of the HDW ERROR register 18.
  • 26 shows the configuration of the refresh address counter 34 in connection with the error detection circuit 35.
  • the refresh address counter 34 consists of two binary counters 56, 57 connected in series, which are counted on cyclically.
  • the first binary counter 56 supplies the time intervals of the refresh requests (about 12 psec).
  • the binary counter 57 is incremented by 1 in each of these intervals.
  • the current refresh address REFRESH ADRS 6-0 is thus supplied to the selection circuit 25.
  • the request signal REFRESH REQUEST for the switching circuit 29 is activated. This is deleted again when the switching circuit 29 starts a REFRESH CYCLE.
  • the error detection circuit 35 consists of a flip-flop in which the previous state of this signal is adopted when REFRESH REQUEST is excited. This results in a REFRESH TIMEOUT CHECK error signal if, after an interval between two refresh times has elapsed, the previous refresh request has not yet been satisfied.
  • the HDW ERROR register 18 is a circuit with outputs that can be controlled independently of the charging clock (RAM LATCH PULSE), so that the information on the bus lines 12 can be read by the CPU 1 as well as by other devices via the external bus system.
  • the HDW ERROR register 18 is wired with error and status signals, as has already been explained with reference to FIG. 12.
  • an error flip-flop 58 is connected in conjunctive association with bit position 2 of CONTROL register 15 (ENABLE ERROR SIGNALIZATION).
  • An elementary microcomputer arrangement is implemented as a "hard core" (CPU 1, I / O circuits 5 ... 9, ROM 10).
  • CPU 1, I / O circuits 5 ... 9, ROM 10 This is functional within the framework of the conventions and the scope of the microprocessor circuit system.
  • the interrupt handling takes place entirely in this framework, regardless of whether interrupts are signaled by connected peripheral devices or via the external bus system.
  • the performance of the I / O circuits 5 ... 9 can be fully exploited, so that cost-effective control of complex and fast peripheral devices (e.g. floppy disc drives) is possible.
  • other devices can access the RAM 13 practically without conflict.
  • this "hard core” allows an advanced test of the remaining switching means with ROM-resident test routines.
  • a "non executive state" waiting state can be forced via the external bus system for purposes of initialization, error handling, etc.
  • it is possible to suppress external waiting conditions in the program for time-critical processes (DIAG MODE register 14, bit 5 SUPPRESS EXTERNAL WAIT CONDS).
  • the address space given by the CPU 1 can be expanded independently for the ROM 10 and other memory means (RAM 13 as well as external memory means accessible via the bus) (bit 0 of the CONTROL register 15 and BUS ADRS register 16). By controlling the reset signals for the CONTROL register 15, depending on the situation, initial test routines or error handling or restart routines are triggered directly in the ROM 10.
  • Error detection circuits are built in, which recognize critical hardware errors (incorrect parity in RAM 13, switching errors, time-out errors during RAM refresh) as well as errors that can be caused by hardware failures as well as incorrect software (memory protection errors, illegal access).
  • critical hardware errors incorrect parity in RAM 13, switching errors, time-out errors during RAM refresh
  • errors that can be caused by hardware failures as well as incorrect software (memory protection errors, illegal access).
  • memory protection errors illegal access
  • test phase for complex systems will be considerably simplified, since errors which can spread unnoticed in conventional microcomputer systems are immediately localized by the switching means provided. This enables errors to be handled by other facilities. This means greater reliability than internal error handling with the self-suspected hardware.
  • the additionally introduced registers through whose connections with other switching means a large part of the specific properties of the arrangement are realized, can be realized with simple means.
  • all commands of the CPU 1 can still be applied to these registers (increase, decrease, set bits, delete bits, query bits), so that effective software can be used for the Operational control can specify.
  • microcomputer arrangements can be implemented inexpensively, which otherwise require much more complex switching means (special control units, minicomputers and the like), or the total effort can be drastically reduced by reducing the number of microcomputer arrangements.
  • the microcomputer arrangements known hitherto require independent input / output computers, processing computers etc. to be provided for more complex systems, for which purpose a higher-level management computer which contains the operating system is usually required.
  • the arrangement according to the invention can, depending on the current situation, work as an input / output or as a processing computer, each of these arrangements in a system can contain its own operating system, and all storage means of the system can be reached among one another.

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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EP82104786A 1981-06-22 1982-06-01 Configuration pour microprocesseur, particulièrement pour l'application dans des systèmes de multimicroprocesseurs Withdrawn EP0067982A3 (fr)

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DD230961 1981-06-22
DD23096181A DD159916A1 (de) 1981-06-22 1981-06-22 Mikrorechneranordnung,vorzugsweise fuer den einsatz in multimikrorechnersystemen

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EP0067982A2 true EP0067982A2 (fr) 1982-12-29
EP0067982A3 EP0067982A3 (fr) 1985-01-09

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0166272A2 (fr) * 1984-06-05 1986-01-02 Nec Corporation Accès de bus pour processeur
EP0348663A2 (fr) * 1988-06-27 1990-01-03 International Business Machines Corporation Diffusion simultanée trans-processeur, de conditions de machine dans un système multiprocesseur à configuration dispersée
CN106652665A (zh) * 2016-12-09 2017-05-10 西安电子科技大学 一种计算机组成原理的实验装置

Citations (4)

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US3711835A (en) * 1969-09-02 1973-01-16 Siemens Ag Program-controlled data telecommunication exchange system and method for priority assignment of operating cycles
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EP0166272A2 (fr) * 1984-06-05 1986-01-02 Nec Corporation Accès de bus pour processeur
EP0166272A3 (en) * 1984-06-05 1988-01-07 Nec Corporation Processor bus access
EP0348663A2 (fr) * 1988-06-27 1990-01-03 International Business Machines Corporation Diffusion simultanée trans-processeur, de conditions de machine dans un système multiprocesseur à configuration dispersée
EP0348663A3 (fr) * 1988-06-27 1991-10-09 International Business Machines Corporation Diffusion simultanée trans-processeur, de conditions de machine dans un système multiprocesseur à configuration dispersée
CN106652665A (zh) * 2016-12-09 2017-05-10 西安电子科技大学 一种计算机组成原理的实验装置

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