EP0064774B1 - Security ignition circuit for an under water igniter - Google Patents

Description

The invention relates to a safety ignition circuit for an underwater detonator with the features of the preamble of patent claim 1.

Underwater detonators equipped with such safety ignition circuits are used, for example, for mine destruction charges. Such a safety ignition circuit is known from US-A-3,572,244. A blind position is achieved in this known ignition circuit by the combination of a relay with a logic circuit which only allows the relay to respond when a predeterminable sequence of acoustic signals is received. This blind position measure no longer meets the high safety requirements recently established, since in the event of failure or malfunction of the relay and / or the logic circuit connected to it, an unintentional ignition, for example by a sound signal not provided for this, because of the permanent connection of the igniter to the Energy source is not excluded.

Another safety ignition device, preferably suitable for active bodies in land use, is known from DE-A-2752823. This has a receiving part, a logic part consisting of directional signal generator, a digital time base and a time window, and actuating elements connected to it. Here the receiving part is used to emit and again pick up sound frequencies and, via control elements, delivers signals for comparison with stored signals to the logic part, which triggers an ignition or a passivation, e.g. B. causes a friend. There is no analogue receiving part for time-correlated frequencies and there is no provision for triggering the actuating elements in successive time intervals. There is therefore no indication of the object on which the invention is based from this published specification.

From DE-A-2 617 775, safety detonators for such explosive charges are already known, which have an exclusively mechanical safety device in which, after removal of a mechanical fuse, the entire charge is thrown into the water, whereupon the increasing water pressure via a membrane and a piston actuates an intermediate fuse, which then explodes the main charge. Such an arrangement thus inevitably detonates after removal of the mechanical fuse when a predetermined hydrostatic pressure is reached, which acts on it after a certain time, which depends on the sinking speed and thus on any flow conditions. A defined effect on the ignition timing and averting the ignition is practically no longer possible after being thrown off.

The object of the invention is therefore to provide a safety ignition circuit with which it is possible to construct a safe ignition device which can be ignited optionally at defined times and in which unintentional ignition is practically impossible.

The solution according to the invention consists in designing a safety ignition circuit in such a way that it has an analog receiving part, a digital logic part and two parallel discharge circuits connected via driver stages, in order to either ignite a detonator or to disconnect the circuit from its voltage supply and short-circuit the latter, and that the digital logic part controls the actuation of the two discharge circuits in successive time intervals as a function of two frequency signals which are correlated in terms of frequency and time.

Further features of the circuit according to the invention are explained in more detail in the subclaims and in the detailed description of the circuit below.

With the circuit according to the invention it is advantageously achieved that no ignition is possible within a first time interval to rule out accidents, ignition is possible at any time within a second time interval, but is not necessary to take account of the respective conditions, and in a third time interval, the power supply is switched off permanently in order to avoid accidents and to safely rule out accidental ignitions.

In this case, the selective bandpass behavior of the analog receiving part, which is designed only for a narrow frequency range of the possible input signal, is advantageously used, the digital circuit being clearly locked against signals of a different type. In addition, the circuit according to the invention offers the advantage of a high level of operational reliability using C-MOS components that require little electricity during operation and an energy source in the form of a lithium battery that can be stored for a number of years.

It is clear that the ignition circuit according to the invention can be used both for a wide variety of mine destruction charges and for other underwater devices. In addition, there are of course other uses, if you z. B. the switch used in the embodiment of a water pressure safety device by another switch, the ignition circuit of which is put into operation when it is closed. While the use of the ignition circuit according to the invention with a mechanical arrangement of pre-plugs and water pressure switches is a suitable type of application, the circuit according to the invention is by no means restricted to this.

• Figur 1 ein Impulsdiagramm von Ausgangssignalen an zwei Ausgängen eines Tellers zur Erläuterung der Abfolge von Totzeit, Scharfzeit und Batterieentladungszeit bei der erfindungsgemäßen Zündschaltung ;
• Figur 2 Blockschaltbild zur Erläuterung des Signalflusses bei der erfindungsgemäßen Zündschaltung ;
• Figur 3 eine Bandfiltercharakteristik der bei der Zündschaltung verwendeten Filter im Bandpaßfilter ;
• Figur4 ein Schaltbild des verwendeten selektiven Bandpaßfilters ;
• Figur 5 eine grafische Darstellung zur Erläuterung des Dämpfungsverlaufes des selektiven Bandpaßfilters nach Fig. 4 ;
• Figuren 6A und 6B ein Schaltbild zur Erläuterung von Einzelheiten der gesamten erfindungsgemäßen Schaltungsanordnung, wobei Fig.6A Einzelheiten der Baugruppen nach Fig. 2A und Fig. 6B Einzelheiten der Baugruppen nach Fig. 2B zeigt.

The invention is explained below with reference to the description of exemplary embodiments and with reference to the accompanying drawings. The drawing shows in

• 1 shows a pulse diagram of output signals at two outputs of a plate to explain the sequence of dead time, arming time and battery discharge time in the ignition circuit according to the invention;
• FIG. 2 block diagram to explain the signal flow in the ignition circuit according to the invention;
• FIG. 3 shows a band filter characteristic of the filters used in the ignition circuit in the band pass filter;
• Figure 4 is a circuit diagram of the selective bandpass filter used;
• FIG. 5 shows a graphic representation to explain the attenuation curve of the selective bandpass filter according to FIG. 4;
• FIGS. 6A and 6B show a circuit diagram for explaining details of the entire circuit arrangement according to the invention, FIG. 6A showing details of the modules according to FIG. 2A and FIG. 6B showing details of the modules according to FIG. 2B.

General function

The entire ignition circuit of the igniter electronics is activated in that when a predetermined water depth of a few meters is reached, the ignition circuit is connected via the switch 42 of the water pressure safety device to the internal battery 40, which is expediently a lithium battery. With a battery voltage of USatt, a normal load current flows in normal operation, while an increased, approximately twice as large load current flows for about 1 second at switch-on. This behavior is at the same time the control for the function of the directional signal generator 26, which ensures that the digital time base 22 and the other digital assemblies 24-32 are brought into a defined starting position at the start of the mission. In addition to other safety measures, the gate electrode of the firing thyristor Thy1 is also short-circuited during the first operating second, thus reliably preventing the firing of this firing thyristor Thy1.

With the end of the directional signal, the digital time base 22 begins with the generation of a time clock. The pulse diagram is shown in FIG. 1, in which the logic output levels of the two outputs Q1 and Q12 of the divider IC7 used are plotted against time. The total mission duration thus consists of three main intervals, namely a dead time t _i , an adjoining arming time t ₂ and finally a battery discharge time t ₃ . The generation and use of the logic signals shown in FIG. 1 is explained in more detail below.

During the dead time in the time interval t ₁ , a sound signal received by the hydrophone 10 can be amplified and switched through by the Schmitt triggers, which are essentially composed of the transistors T3 and T5 or T4 and T6, but prevents digital linking and Decision logic the delivery of an output signal from the power inverter 13 of the integrated circuit IC9 to the firing thyristor Thy1, so that an ignition in this time interval t ₁ is not yet possible.

During the arming time in the subsequent time interval t ₂ , the input decoder IC4A in conjunction with the time base decoder IC4B enables the preparation of the NAND gate G1 in the IC8, so that when a correct ignition signal arrives, the power inverter 13 of the IC9 is switched through and the ignition process is initiated. However, if such an ignition signal fails during the time interval t ₂ , the battery 40 is discharged during the subsequent time interval t ₃ and the entire evaluation electronics is disconnected from the power supply via a fuse Si. Ignition is impossible in this way, while recovery of the associated mine destruction charge or the underwater detonator is possible after the mission duration, but is not necessary.

Analog section with preamplifier, bandpass filter and isolation amplifier (see Fig. 2 and Fig. 6A)

The analog part of the ignition circuit according to the invention, which essentially has a preamplifier 12, a bandpass filter 14, an isolating amplifier 16 and first and second selective filters 18 and 20, is shown schematically in FIG. 2 and in detail in FIG. 6A.

Preamplifier

A ceramic pressure transducer or a hydrophone 10 is used to record the coded audio frequency signals emitted by a transmitter. The hydrophone 10 is already connected to a resistor R1 directly at the input of the circuit (see FIG. 6A) in order to linearize the transmission dimension and to avoid the formation of a static DC voltage due to the intrinsic capacity of the hydrophone 10.

The sound signal received by the pressure transducer or hydrophone 10 is then fed via the coupling capacitor C2 to the inverting input of the analog operational amplifier IC1, which represents the essential component of the preamplifier 12. The inverting input of the operational amplifier IC1, with two high-resistance resistors R3 and R2, lies symmetrically between the ground and the supply voltage U _Batt . while the supply line itself via two capacitors C1 and C15 is blocked from the crowd. Two measuring points MP5 and MP6 for the received sound signal are located at the two ends of the resistor R1. The non-inverting input of the operational amplifier IC1 is connected to ground via a resistor R4 and a capacitor C3.

The gain of this first amplifier stage is V ₁ = 1 000 ⁼ 60 dB, corresponding to the selected frequency-dependent negative feedback of the operational amplifier IC1 via the resistor R5 and the series connection of the resistor R4 and the capacitor C3. For a received sound signal, the output voltage of the pressure transducer or hydrophone 10 has a value U1, so that a correspondingly amplified signal with a value of U2 is available for further processing at the output of the preamplifier 12.

The RC element consisting of the resistor R4 and the capacitor C3 provides a frequency-dependent amplification of the output signal, the attenuation measure being approximately 6 dB per octave. In connection with the RC element or the resistor R1 consisting of the capacitor C2 and the resistor R3, which together form a high-pass filter, a slight band-pass behavior already results at this point. The capacitor C4 is used for frequency compensation of the operational amplifier IC1. The output of the iC1 is connected to the supply voltage via a resistor R6 and to the inverting input of a first operational amplifier IC2A of the subsequent bandpass filter 14 via a capacitor C5, a resistor R7 and a capacitor C7.

Bandpass filter

The bandpass filter 14 essentially consists of two operational amplifiers IC2A and IC2B with appropriate circuitry in order to implement the bandpass behavior already desired in the preamplifier 12 with an even more pronounced attenuation curve.

The output of the operational amplifier IC2A is connected via a resistor R9 to the inverting input and via a capacitor C6 to the input of the capacitor C7 and to one side of a resistor R8 which is connected to ground on the other side. The non-inverting input of the operational amplifier IC2A is on one side of a resistor R10, on the other side via a capacitor C8 to ground, via a resistor R12 also to ground, via a resistor R14 to the non-inverting input of the next operational amplifier IC2B and is connected to the supply voltage via a resistor R11. The output of the operational amplifier IC2A is connected via a resistor R13 and a capacitor C10 to the inverting input of the second operational amplifier 1C2B of the bandpass filter 14. The output of the operational amplifier IC2B is via a resistor R16 with its inverting input and via a capacitor C9 with the input of the capacitor C10 and connected to one side of a resistor R15, which is connected to ground on the other side.

The desired bandpass behavior with a pronounced damping curve can be achieved, for example, by connecting two selective filters of the 1st order in series, the resonance frequencies of which are slightly out of tune with one another, which is also referred to as staggered tuning. The qualitative attenuation curve is shown in Fig., In which the amount of the normalized gain is plotted against the normalized frequency. Curves 1 and 2 show the frequency response of the individual filters, while curve 3, which is drawn out more strongly, shows the resulting frequency response.

It can be seen that the resulting frequency response shown in curve 3 is substantially flatter in the vicinity of the resonance frequency than that of the individual low-pass filters, but drops more steeply at higher and lower frequencies. A bandpass filter optimized for the transmission range, as used in the entire circuit arrangement, is shown in detail in FIG. 4.

This results in the attenuation curve shown in FIG. 5 of the selective bandpass filter according to FIGS. 4 and 6A.

Using components with a maximum tolerance of 1% for the resistors R7 to R13 or 2.5% for the capacitors C6 to C10 results in a sufficiently small frequency change over the temperature range from - 20 ° C to + 50 ° C.

The saddling of the transmission dimension at the band ends shown in FIG. 5 is a maximum of 6 dB and is insignificant in practice since the gain is constant to ± 1 dB in the area actually used.

Isolation amplifier

The signal amplified in the preamplifier 12 and processed and amplified in the bandpass filter 14 is applied via a coupling capacitor C11 to the inverting input of an operational amplifier IC3.

The input side of the capacitor C11 is connected to the supply voltage via a resistor R17, while the inverting input of the IC3 with two high-resistance resistors R18 and R19 is symmetrical between the ground and the supply voltage. The non-inverting input of the operational amplifier IC3 is connected to ground via a resistor R20 and a capacitor C12, so that the operational amplifier IC3 is negatively coupled via the RC element R20 / C12 depending on the frequency. The output of the IC3 is via a potentiometer P1 with its non-inverting input connected, so that the output voltage required to control the Schmitt trigger in the two selective filters 18 and 20 can be set. The criterion for maintaining the selected sensitivity is the unambiguous switching of the Schmitt triggers, which is detectable for the two frequencies F1 and F2 at the two measuring points MP3 and MP4 at the output of the two selective filters. The capacitor C13 is used for frequency compensation of the operational amplifier IC3. Furthermore, the output of the operational amplifier IC3 is connected to the supply voltage via a resistor R21.

All four operational amplifiers IC1, IC2A, IC2B and IC3 are connected in the usual way to the supply voltage USatt and to ground (see FIG. 6A).

The now low-impedance and low-frequency output signal present at the output of the isolation amplifier 16, that is to say at the output of the operational amplifier IC3, is coupled out via a coupling-out capacitor C14 and passes through an RC low-pass element, which consists of a resistor R22 and a capacitor C16, to which are connected as limiters Zener diode D1, which limits the low-frequency output signal when the Zener voltage is reached.

This measure ensures that with constant amplification with a stronger input signal, for example with a short ignition and blasting distance, the downstream tuning fork filters StG1 and StG2 are not overridden before the Schmitt triggers. The result would be that the permissible switching bandwidth of the tuning fork filter would deviate too much from the nominal frequency. In this way, part of the high selectivity achieved would be lost again.

Selective filter and Schmitt trigger

The low-frequency voltage available at the output of the isolating amplifier 16 is fed to the two selective filter channels for the code frequencies F1 and F2 via the two decoupling resistors R23 and R24 for further signal processing, where they can be processed separately. The required high selectivity and quality of transmission can only be achieved with relatively little circuitry using piezo-electric tuning fork filters, which adhere exactly to the printed resonance target frequency to ± 1 Hz.

The two tuning fork filters StG1 and StG2 are each followed by a transistor T1 or T2 in channel F1 or F2 connected as an emitter follower, which each trigger a Schmitt trigger via coupling capacitors C19 and C20, which trigger consists of the two transistors T3 and T5 and T4 and T6 is built. In the channel for the signal F1, the base of the transistor T1 is connected to the supply voltage via a resistor R25, while the emitter of T1 is connected to ground via a resistor R27 and a parallel capacitor C17 and the collector is connected directly to the supply voltage. The capacitor C19 is connected on the input side to the emitter of T1, is connected to ground on the output side via the reverse-connected diode D2 and supplies the output signal from T1 via the forward-connected diode D4 to the base of the transistor T3 of the first Schmitt trigger. The base of T3 is connected to the supply voltage via a resistor R29 and to ground via a capacitor C21.

The collector of transistor T3 is connected to the supply voltage via a resistor R31 and is directly connected to its own emitter via a capacitor C23 and to the base of the transistor T5 connected downstream. The emitter of T3 is connected to ground via a resistor R32 and is connected to the emitter of the transistor T5 connected downstream. The emitter of T5 is connected to its base via capacitor C23, while its collector is connected to the supply voltage via a resistor R35. The measuring point MP3 is also located at the collector of T5.

In the second selective filter, the base of the transistor T2 connected as an emitter follower is connected to the second tuning fork filter StG2 and via a resistor R26 to the supply voltage, while the collector of T2 is connected directly to the supply voltage. The emitter of T2 is connected to ground via a parallel connection of resistor R28 and capacitor C18, while the output signal from T2 is connected to the base of transistor T4 of the second Schmitt trigger via the emitter, coupling capacitor C20 and a forward-connected diode D5. The output side of the capacitor C20 is connected to ground via a diode D3 switched in the reverse direction. The base of T4 is connected to the supply voltage Usatt via a resistor R30 and to ground via a capacitor C22. The collector of T4 is connected to the supply voltage via a resistor R33 and directly to the base of the transistor T6 of the second Schmitt trigger. A capacitor C24 is connected between the collector and the emitter of T4, while the emitter of T4 is connected to ground via a resistor R34 and is connected directly to the emitter of transistor T6. The collector of the transistor T6 is connected to the supply voltage via a resistor R36, and the collector of T6 also forms the measuring point MP4 for the signal F2 with the second code frequency.

Both Schmitt triggers work with switching delays in the millisecond range, so that interference pulses and noise signals cannot lead to false tripping. The measure thus serves to introduce a switching delay for operational safety. After switching through the two Schmitt triggers with transistors T3 and T5 or T4 and T6, a DC voltage signal with a level of approximately OV = is present at both measuring points MP3 and MP4, which are used as input signals for the digital logic and logic part of the ignition circuit serve.

The setting of the isolating amplifier 16 for the downstream selective filter is done in such a way that an input signal is fed in at the measuring point MP5, both frequencies F1 and F2 being selected in accordance with the marked fuse coding.

Thereupon, the switching of the Schmitt trigger with the transistors T3 and T5 for the frequency F1 is monitored at the measuring point MP3, while the gain is set at the potentiometer P1. An initially pending DC voltage signal with a level of U _Batt goes to a level of approximately OV ₌ when the Schmitt trigger is switched. In the same way, the switching of the second Schmitt trigger with transistors T4 and T6 is checked at measuring point MP4 when the input signal is fed in at frequency F2. This completes the setting of the gain, the total gain of the amplifier filter chain being equal to the sum of the gains of the individual amplifiers.

Digital part of the ignition circuit

All integrated circuits IC4A, IC4B, ICS, IC6, IC7, IC8 and IC9 in the digital part of the ignition circuit are constructed using C-MOS technology and are connected in a conventional manner to the supply voltage U _Batt or to ground, these connections being provided for the sake of clarity the drawing are omitted. The signals F1 and F2, which are amplified and filtered in the analog part, are fed into the input decoder IC4A at the two inputs A and B, as shown in FIG. 6B, while the signal F1 is also at the fourth input of the NAND gate G1. The supply voltage of the input decoder IC4A is blocked against ground via a capacitor C26. The outputs QO and Q3 of the IC4A are brought out freely, while the output Q1 of IC4A is connected to the P / S control input of the shift register IC5 and the output Q2 of IC4A is connected to the second input of the NAND gate G1.

At the output RI of the inverter 11 are the input of the inverter 12, via a resistor R48 the base of the transistor T7, the clock input E of the time base decoder IC4B, the reset input R of the plate IC7, the reset input R of the divider IC6 and the clock input E of the input decoder IC4A connected. The output Q12 of the plate IC6 is brought out, the output Q13 of the plate IC6 is connected to the clock input CL of the shift register IC5 and the output Q14 of the plate IC6 is connected to the clock input CL of the plate IC7. The outputs Q11 and Q12 of the plate IC7 are connected to the inputs A and B of the time base decoder IC4B.

In the time base decoder IC4B, the output QO is brought out, the two outputs Q1 and Q2 are connected to the two inputs of the NOR gate G3 and the output Q3 is connected to the fourth input of the NAND gate G2. The output of the NOR gate G3 is connected to the third input of the NAND gate G2 and to the input of the inverter 15. The output of the inverter 15 is at the third input of the NAND gate G1 and, on the other hand, via a resistor R39 at the measuring point MP8, which is blocked from ground via a capacitor C27. The output RI of the inverter 12 is connected to the first two inputs of the NAND gate G2 and to the eight parallel data inputs PI1 to PI8 of the shift register IC5. The input DS of the shift register IC5 is grounded, its two outputs Q7 and Q8 are brought out and the output Q6 is connected to the first input of the NAND gate G1. The outputs of the two NAND gates G1 and G2 are connected to inverters 13 and 14, which deliver the signals for the detonator ignition circuit and the battery discharge circuit via resistors R40 and R41. The output of the inverter 12 is fed back to the input of the inverter 11 via a resistor R42.

The divider IC6 is connected in the manner indicated, so that the input Ø is connected to the input 0 via a capacitor C25 and a resistor R37 and to the input 0 via a series circuit comprising a potentiometer P2 and a resistor R38. Input 0 itself is at measuring point MP7, which can be used as a time-lapse input.

The input decoder IC4A and the time base decoder IC4B are designed in the form of an integrated circuit and operate according to the truth table given below.

Truth table for the two decoders IC4A and IC4B

Eingangs- und Ausgangsfunktionen des Digitalteiles

Input and output functions of the digital part

Two input functions are formed by the two signals F1 and F2, which are trapezoidal pulses that run from «L to« Ø »and have a rise time of around 50 ms, a rise delay of around 50 ms and a fall time of around 50 ms. The pulse duration is about 1 second if the transmission is correct and the reception is undisturbed, but the transmission pulse can fluctuate or be chopped due to interference on the transmission path. Despite the above-mentioned, deliberately flat edge steepness, the pulses are suitable for further processing in the subsequent C-MOS circuits. There is a certain pulse pause between the two signals F1 and F2.

Another input function is the supply voltage or battery voltage U _Batt , because the directional signal RI is derived from its rise when the battery 40 is switched on by the switch 42 of the water pressure safety device, which brings all flip-flops within the C-MOS circuits into their starting position and also locks the ignition release during the settling time with a safety circuit.

The two output functions of the digital part are the ignition current for the detonator 38 and the battery discharge current of the battery 40.

• a) Scharfzeit : Freigabe der Zündung des Detonators 38 nach t₁ nach dem Schließen des Schalters 42 der Wasserdrucksicherung in einer vorgegebenen Wassertiefe von einigen Metern ;
• b) Ende der Scharfzeit : Sperren der Freigabe der Zündung des Detonators 38 nach t₁ + t₂ nach dem Schließen des Schalters 42 der Wasserdrucksicherung und Abtrennen der gesamten Zündschaltung von der Batterie 40 ;
• c) Entladen der Batterie 40 ebenfalls nach t₁ + t₂ nach dem Schließen des Schalters 42 der Wasserdrucksicherung ;
• d) Zeitfenster mit 3 Sekunden : Freigabe des Signals zur Zündung des Detonators 38 für etwa 3 Sekunden, wenn das Signal F1 wieder verschwunden ist, so daß der Pegel wieder auf eine Spannung von U_Batt ansteigt. In dieses Zeitfenster muß das Signal F2 fallen, damit die Zündbedingung für den Detonator 38 erfüllt ist.

As already mentioned at the beginning, the digital part of the ignition circuit has several tasks. Once the digital part checks whether the signals F1 and F2 appear approximately with the correct pulse length and the specified time sequence. Furthermore, the detonator ignition circuit is blocked if this condition is not met. In addition, the input functions are logically linked to one another and the two signals for firing the ignition thyristor Thy1 for the detonator and the discharge thyristor Thy2 for the battery are formed, or these signals are locked as a function of the time functions. In addition, all memories are aligned when the battery is switched on and the output functions are blocked. The following time functions are formed to carry out these various tasks:

• a) arming time: release of the ignition of the detonator 38 after t ₁ after the switch 42 of the water pressure safety device has been closed at a predetermined water depth of a few meters;
• b) end of the arming time: blocking the release of the ignition of the detonator 38 after t ₁ + t ₂ after closing the switch 42 of the water pressure safety device and disconnecting the entire ignition circuit from the battery 40;
• c) discharging the battery 40 also after t ₁ + t ₂ after closing the switch 42 of the water pressure safety device;
• d) Time window with 3 seconds: release of the signal to ignite the detonator 38 for about 3 seconds when the signal F1 has disappeared again, so that the level rises again to a voltage of U _Batt . The signal F2 must fall within this time window so that the ignition condition for the detonator 38 is fulfilled.

The individual components of the ignition circuit are explained in detail below.

Input decoder

• F1, F2 : logisch « L » (DC-Signal mit 11,2V=)
• F1, F2 : logisch « Ø » (Nullsignal).

The input decoder IC4A is used to sample the two signals F1 and F2, which are generated by the two Schmitt triggers in the two selective filters 18 and 20, respectively. In the description below, the following notation is used for the signals:

• F1, F2: logical «L» (DC signal with 11.2V =)
• F1, F2 : logical «Ø» (zero signal).

The two signals F1 and F2 are supplied at the measuring points MP3 and MP4 from the outputs of the two Schmitt triggers at which the interface between the analog parts and the digital part of the ignition circuit is located. The two signals are fed to an input decoder IC4A constructed using C-MOS technology, the input code being a 2-bit binary code, ie the logic signals F1 and F2 are considered to be binary variables and can occur in any distribution. The output code of the IC4A input decoder is a 1-out-of-4 code, whereby one of the four outputs can carry an L signal. The additional clock input E is driven only by the directional signal RI from the inverter 11 and blocks all four outputs of the input decoder IC4A during the switching on process of the battery 40.

As shown in Fig. 6B, only the two outputs Q1 and Q2 of the IC4A are used, with Q1 then becoming active and carrying an L signal when Fi is at the 0 level, i. H. when the frequency F1 has been emitted by the transmitter and the analog part as the receiving part has properly picked up, selected and amplified the oscillation train.

Due to the truth table of the input decoder IC4A given above, there is the further condition that F2 must not be present at the same time as F1. Conversely, for the next phase of signal transmission, signal F1 must have disappeared again before signal F2 arrives. In this case, output Q2 of the input decoder IC4A becomes active, while all other outputs carry a 0 signal. If signals F1 and F2 are received correctly with the corresponding frequencies, an L signal appears at output Q1 with the statement «F1 and F2 _' , then the _L signal changes to exit Q2 and then means « F1 and F2 ». If both signals F1 and F2 are missing with the corresponding frequencies or if both signals occur simultaneously, the two outputs Q1 and Q2 are both at Ø5 level.

Directional signal generator

In the directional signal generator 26 (see FIG. 6B), the two inverters 11 and 12 connected in series form a C-MOS buffer inverter in IC9 with positive feedback via resistor R42 together with a series resistor R43, a Schmitt trigger. This Schmitt trigger controls the charging voltage of the capacitor C30, which is expediently designed as a tantalum electrolytic capacitor. When the ignition circuit is switched on via the switch 42 of the water pressure fuse, the capacitor C30 is charged to the supply voltage U _Batt via the charging resistor R46. The charging time constant is approximately 1/2 second.

• Das Signal RI bringt sämtliche Flip-Flops des Binär-Untersetzers in die Nullage und sperrt den Eingangsdecoder IC4A und den Zeitbasisdecoder IC4B über die Takteingänge E während der Richtzeit. Außerdem liefert das Signal RI das Ansteuersignal für die Basis des Transistors T7 für die Funktion einer Kurzschlußschaltung, die dafür sorgt, daß für die Zeit der Richtsignalerzeugung der Zünd-Thyristor Thy1 gesperrt bleibt.

The downstream Schmitt trigger tips about 1 second after switching on. The exit RI remains at Ø level during this time and then jumps to L level (RI signal). The complementary output RI goes immediately after turning on L _- level and tilts about 1 second later, to the O-back level. Both signals are used in the digital part of the ignition circuit, as follows:

• The signal RI brings all flip-flops of the binary reducer into the zero position and blocks the input decoder IC4A and the time base decoder IC4B via the clock inputs E during the target time. In addition, the signal RI provides the drive signal for the base of the transistor T7 for the function of a short-circuit which ensures that the firing thyristor Thy1 remains blocked for the time of the directional signal generation.

The signal RI keeps the parallel data inputs PI1 to PI8 of the shift register IC5, which is used to generate the 3-second time window, at the Ø level for about 1 second. At the same time, the signal is blocked RI the NAND gate G2 for 1 second, so that the discharge thyristor Thy2 cannot be fired.

With the decay of the signal RI and the complementary signal RI the input decoder IC4A and the time base decoder IC4B as well as the NAND gate G2 at the output for the ignition of the discharge thyristor Thy2 are unlocked. At the same time, the short circuit of the gate electrode as the ignition electrode of the ignition thyristor Thy1 for the detonator 38 is removed and all binary converters in the dividers IC6 and IC7 are released. The parallel data inputs PI1-PI8 of the shift register IC5, which works as a time window 28, are set to L level. The entire ignition circuit is thus in operation and is no longer affected by the signals RI or RI dependent.

Time window

The function of the time window 28 is realized with an 8-stage, static C-MOS shift register IC5, in which the eight parallel data inputs PI1 to PI8 are constantly at the L level after the switch-on process. The only serial data input, namely the DS input of the IC5, is fixed at the Ø level. The three outputs Q6, Q7 and Q8 of the last three flip-flops of the shift register IC5 are brought out, but only the output Q6 is used to pass on the time window pulse.

The clock input CL of the shift register IC5 is constantly supplied with symmetrical rectangular pulses, which are supplied by the clock system of the digital time base 22, which is described in more detail below. The pulse repetition frequency is 2.2755 Hz, which corresponds to a period of 0.44 seconds. The parallel-serial control input P / S determines the function of the shift register ICS.

If there is a signal at the L level at the control input P / S of the IC5, the shift register IC5 operates in parallel, i. H. it works asynchronously and parallel operation has priority.

If there is a signal with a 0 level at the control input P / S of the shift register IC5, the shift register IC5 operates in serial mode, i. H. synchronized with the clock pulses at the clock input CL.

The control input P / S of the shift register IC5 is driven by the output Q1 of the input decoder IC4A (cf. FIG. 6B). The shift register IC5 switches to parallel operation when the output Q1 of the IC4A goes to L level, i. H. then when the circuit receives the signals «F1» and «F2. In this case, the output Q6 of the shift register IC5 goes to the L level and remains at the L level as long as the signals «F1» and «F2 are present.

When the signal F1 disappears after about a second, the output Q1 of the input decoder IC4A switches back to 0 level, so that the shift register IC5 switches back to serial operation via the control input P / S. With the next clock pulse at clock input CL, a logical “Ø” is “pushed” into the first flip-flop of shift register IC5, since the serial data input or control input DS, as already mentioned, is constantly at the Ø level. With the positive edges of the following clock pulses, the front of the signals with Ø level moves from flip-flop to flip-flop. With the sixth clock pulse, the signal reaches the output Q6 of the shift register IC5. In this way, the pulse called the time window is generated, which has the following duration:

T _F1 is hidden in the output link for firing the detonator 38, so that the duration of the time window is between 2.2 and 2.64 seconds. The tolerance range is explained by the fact that the positive edges of the clock pulses are asynchronous to the signal F1, their phase position is purely random. The next edge at the transition from 0 level to L level after the disappearance of the signal F1 can come immediately after or only after 0.44 seconds.

The pulse width of the time window pulse, in addition to this tolerance which is customary for digital counting circuits, depends only on the accuracy of the oscillator frequency of 2.2755 5 Hz, which will be discussed in more detail below in connection with the digital time base 22. The output pulse at the output Q6 of the shift register IC5 is at the first input of the NAND gate G1 for the output combination of the ignition of the detonator 38.

Digital time base

The timing system of the ignition circuit consists of an RC oscillator with a 26-bit binary reducer (2 ²⁶ = 67 108 864) and a decoder that evaluates the last two bits of the divider chain.

The RC oscillator is part of a divider IC6 designed in C-MOS technology with 14 flip-flops connected in series, which form a binary coaster 1: 16 384, the operation is asynchronous (ripple-carry). The zeroing of the divider IC6 takes place via a common reset input R, with the directional signal RI from the inverter 11 already explained above. The RC oscillator integrated with the binary coaster is tuned by the trim potentiometer P2, the total load resistance being determined by the measuring arrangement at the measuring point MP7 is 1 MΩ. The clock input or clock input of the first flip-flop of the divider IC6 is brought out and labeled “Ø”. The oscillator can be overridden by applying an external rectangular pulse sequence to the measuring point MP7 and thus to the clock input, so that the own RC circuit is ineffective. The following binary coaster processes frequencies up to approx. 8 MHz.

To test the clock program contained in the ignition circuit, z. B. feed an external frequency in the MHz range via the measuring point MP7 into the clock input, which shortens the cycle time to a few seconds in order to avoid long waiting times during testing and setting, ie one works in time-lapse mode at the measuring point MP7. It is important here that the controlling square-wave signal must never run symmetrically around the zero point, but should be approximately 10 V _ss , starting from ground. Please note that negative voltages of <0.7 volts at measuring point MR7 can destroy the divider IC6.

The last output Q14 of the 14-stage binary reducer in the divider IC6 outputs a square-wave frequency of 1.13775 Hz at the downstream 12-stage binary reducer of the plate IC7 (18641: 16384). This divider IC7 divides the square frequency once again in a ratio of 1: 4 096, ie by the value 2 ¹² , so that a square frequency of 2.7777 · 10 ^-4 Hz can be tapped at its last output.

The following frequencies and times are tapped and evaluated from the entire divider chain, which consists of the two dividers IC6 and IC7:

The frequency of 2.275 5 Hz serves as the clock frequency at the clock input CL for the shift register IC ₅ . The other two frequencies at the two outputs Q11 and Q12 of the divider IC7 are fed to the time base decoder IC4B at its two inputs A and B for evaluation. The input code of the time base decoder IC4B is a 2-bit binary code, its output code is a 1-out-of-4 code. According to the pulse diagram shown in FIG. 1, the three time ranges t ₁ , t ₂ and t ₃ result at the output of the time base decoder, as can be seen from the table below.

During the time t ₁ after switching on the ignition circuit, the two NAND gates G1 and G2 at the output of the digital logic part 24 in the two ignition channels for the ignition of the detonator 38 on the one hand and the discharge of the battery 40 on the other hand are blocked. The only output of the time base decoder IC4B which carries an L-level signal, namely Q0, is not used. After t _{1 has} elapsed, the signal with L level changes to output 01 of the time base decoder IC4B. This signal with L level then goes to the output Q2 and finally after t ₁ + t ₂ after switching on to the output Q3 of the time base decoder IC4B, the outputs Q1, Q2 and Q3 leading to the output linkage of the digital logic part 24.

Output links to ignite the detonator or discharge the battery

• a) Ein Zeitintervall von t₁ ist nach dem Einschalten der Zündschaltung vergangen : Es liegt ein Signal mit L-Pegel am dritten Eingang des NAND-Gatters G1 im IC8.
• b) Ein Signal F1 ist empfangen worden : Damit liegt ein Signal mit L-Pegel am ersten Eingang des NAND-Gatters G1 des IC8 für die Dauer des Signales F1 und ein Intervall von ungefähr 2,4 Sekunden an.
• c) Das Signal F1 ist wieder verschwunden : Es liegt ein Signal mit L-Pegel am vierten Eingang des NAND-Gatters G1 des IC8 an.
• d) Unmittelbar nach dem Verschwinden des Signals F1 wird ein Signal F2 empfangen : Es liegt ein Signal mit L-Pegel am zweiten Eingang des NAND-Gatters G1 des IC8 an.

To control the firing thyristor Thyl, which triggers the detonator 38, a total of four conditions must be met:

• a) A time interval of t ₁ has passed after the ignition circuit has been switched on: there is a signal with an L level at the third input of the NAND gate G1 in the IC8.
• b) A signal F1 has been received: This means that a signal with an L level is present at the first input of the NAND gate G1 of the IC8 for the duration of the signal F1 and an interval of approximately 2.4 seconds.
• c) The signal F1 has disappeared again: there is a signal with an L level at the fourth input of the NAND gate G1 of the IC8.
• d) Immediately after the disappearance of the signal F1, a signal F2 is received: there is a signal with an L level at the second input of the NAND gate G1 of the IC8.

At the output of the quadruple NAND gate G1 of the IC8 in the digital logic part 24, a signal with a 0 level is produced if the four conditions mentioned are fulfilled. From this signal with 0 level), the downstream inverter 13 generates a signal with L level, i. H. a signal for firing the firing thyristor Thy1 of the detonator 38. This L-level signal is fed to the gate electrode as the firing electrode of the firing thyristor Thy1, where it is also subject to a link to the directional signal RI from the inverter 11. The transistor T7, whose base is driven by a base voltage divider with the two resistors R48 and R49, short-circuits the gate electrode during the target time.

• a) Die Erzeugung des Richtsignales RI ist abgeschlossen : Es liegt ein Signal mit L-Pegel an den ersten beiden Eingängen des NAND-Gatters G2 von IC8.
• b) Die Ausgänge Q1 und Q2 des Zeitbasisdecoders IC4B führen ein Signal mit Φ-Pegel. Das nachgeschaltete NAND-Gatter G3 im IC8 erzeugt daraus ein Signal mit L-Pegel am dritten Eingang des NAND-Gatters G2, aus dem ein nachgeschalteter Inverter 15 ein Signal mit Φ-Pegel für das vierfache NAND-Gatter G1 des IC8 an dessen drittem Eingang macht und damit im digitalen Logikteil 24 im IC8 die beiden NAND-Gatter G1 und G2 gegeneinander verriegelt.
• c) Der Ausgang Q3 des Zeitbasisdecoders IC4B führt ein Signal mit L-Pegel, d. h. es ist 3 · t₁, insgesamt die Zeit t₁ + t₂, seit dem Augenblick des Einschaltens vergangen.

The following three conditions must be met to control the discharge thyristor Thy2 for battery discharge:

• a) The generation of the directional signal RI is completed: there is an L-level signal at the first two inputs of the NAND gate G2 of IC8.
• b) The outputs Q1 and Q2 of the time base decoder IC4B carry a signal with a Φ level. The downstream NAND gate G3 in the IC8 generates a signal with an L level at the third input of the NAND gate G2, from which a downstream inverter 15 generates a signal with a Φ level for the fourfold NAND gate G1 of the IC8 at its third input makes and thus interlocks the two NAND gates G1 and G2 in the digital logic part 24 in IC8.
• c) The output Q3 of the time base decoder IC4B carries a signal with an L level, ie it is 3 · t ₁ , total time t ₁ + t ₂ , since the moment of switching on.

In this way, a signal with a 0 level is present at the output of the second NAND gate G2 in the IC8, which signal is converted into a signal with an L level by a downstream inverter 14 and is then used to ignite the discharge thyristor Thy2 for battery discharge.

Detonator ignition circuit

The output signal of the inverter 13 of the first driver stage 30 in the IC9 is fed to an RC filter, which consists of the resistor R40 and the capacitor C28, for deriving interference peaks. With the output signal from the inverter 13, the gate electrode as the ignition electrode of the ignition thyristor Thy1 in the ignition circuit of the detonator 38 is then driven directly via a series resistor R44 and a diode D8 operated in the forward direction. The power diode D8 brings an additional safety threshold value of approximately 0.65 V into the ignition circuit.

On the anode side, a capacitor C33, expediently a tantalum electrolytic capacitor, is connected to the thyristor Thy1 and is charged by the battery 40 via the resistor R58 to the supply voltage of UBatt. The anode of the ignition thyristor Thy1 takes the ignition current for the detonator 38 from this capacitor C33, the capacitor C33 ensuring the required current surge. The detonator 38 itself lies in the cathode circuit of the ignition thyristor Thy1 to ground. In parallel with the detonator 38, the resistor R56 is connected to ground to discharge thyristor reverse currents, while the cathode of the thyristor Thy1 itself lies at measuring point MP9. The gate electrode of the thyristor Thy1 is connected to ground via a resistor R54 and a capacitor C32 connected in parallel therewith in order to discharge any positive interference peaks at the gate electrode of the ignition thyristor Thy1.

As already mentioned, the transistor T7 connected in parallel with the resistor R54 and the capacitor C32, which has its emitter connected directly to ground, with its collector on the one hand directly at the gate electrode of the ignition thyristor Thy1 and on the other hand via the diode D8 Resistor R44 and the RC element from R40 and C22 is at the output of inverter 13, for the fact that transistor T7 during the switching-on process of the circuit, via the signal RI from the inverter 11, performs a short-circuit function and ensures the blocking of the ignition thyristor Thy1.

Battery discharge circuit

Similar to the detonator ignition circuit, the output signal of the inverter 14 of the second driver stage 32 in the IC9 passes through an RC filter, which consists of the resistor R41 and the capacitor C29. From there, the signal runs as an ignition pulse for the discharge thyristor Thy2 via a resistor R45 and a Zener diode D7 to the gate electrode as the ignition electrode of the discharge thyristor Thy2, the Zener diode D7 having a Zener voltage of 5.1 V to raise the thyristor Ignition threshold ensures.

The gate electrode of the discharge thyristor Thy2 is connected to ground via a bleeder resistor R47, while a capacitor C31, expediently a tantalum electrolytic capacitor, is connected in parallel with R47 in order to short-circuit any interference peaks. In contrast to the ignition thyristor Thy1, the cathode of the discharge thyristor Thy2 is connected directly to ground, while the thyristor is mounted on a heat sink for better dissipation of the power loss that occurs in the discharge thyristor Thy2.

The battery 40 is discharged via four resistors R50 to R53 connected in parallel, which have a total resistance of approximately 11 ohms. The discharge thyristor Thy2 remains fired and discharges the battery 40 with an initial discharge current in the amp range. The rest of the ignition circuit is de-energized when the discharge thyristor Thy2 is fired, since at the same time the fuse Si, designed as a carrier fuse, is melted through a series circuit consisting of a diode D9 and a resistor R55.

From the time the switch 42 of the water pressure safety device is closed, the load resistor R57 ensures a constant load, so that the battery discharge process is not interrupted prematurely even when the holding current of the discharge thyristor Thy2 is undershot during the discharge phase.

Mode of action

As indicated in Fig. 2, the signals are received by the hydrophone 10 and pass through the preamplifier 12, the bandpass filter 14, the isolation amplifier 16 and the two selective filters 18 and 20, which deliver the two signals F1 and F2, which act as logic signals in the digital logic part are further processed, which is connected to a directional signal generator 26, a time window 28 and a digital time base 22 and contains the logic and decision logic, which, depending on the input signals received by the hydrophone 10, the first driver stage 30 or the second driver stage 32 supplied with an output signal, which either ignites the detonator 38 via an ignition circuit 34 or in the discharge circuit 36 for disconnecting the supply voltage and discharging the battery 40. In practice, the ignition circuit described above is connected to the battery 40 with the switch 42 of the water pressure safety device and is thus put into operation if the pin and the water pressure safety devices have previously been unlocked according to the forced sequence unlocking principle. As soon as this connection of the ignition circuit to the battery 40 has taken place, the dead time t _{1 of} the igniter begins, so that an emergency vehicle which has brought an ignition charge provided with the ignition circuit to the place of use can easily move away, since an ignition of the detonator 38 is not possible in this time interval.

After this dead time t ₁ , the arming time t _{2 of} the ignition circuit begins, during which the detonator can be ignited by coded signals with corresponding frequencies. In this case, ship noises or detonation impacts in or above the water are recognized and suppressed by the evaluation electronics of the ignition circuit as non-coded signals. For this reason, it is possible to work with a plurality of detonators with ignition circuits in this way at the same time in an operation area, since the detonator code can be specified differently in the evaluation electronics of the ignition circuit and the transmitter providing the triggering pulse can be set to the individual detonator codes.

If no ignition signal occurs in the ignition circuit during the arming time t ₂ , that is to say t ₁ + t ₂ after the start of the ignition circuit, the battery 40 carried in the igniter is discharged with a discharge current in the ampere range via a discharge circuit 36 with the thyristor Thy2. At the same time, the evaluation part of the ignition circuit, that is to say the analog part for selecting the input signals, and the entire detonator ignition circuit are separated from the battery 40 via the fuse Si, while the discharge thyristor Thy2 used for discharging the battery 40 is also switched through after the discharge time t ₃ remains. If the holding current falls below approximately 10 milliamperes, the discharge resistor R57 discharges the battery 40 until it is completely exhausted.

In the ignition circuit described above, C-MOS components are expediently used, which have a relatively slow switching behavior in the microsecond range, but are completely sufficient for the present purpose and also offer the advantage that they do not unnecessarily load the battery because the individual components practically only draw significant current for a few µs at the moment of switching.

Claims (11)

1. Detonator safety circuit for an under-water detonator in which a signal comprising a number of time-correlated frequencies from a sonic frequency range is used to initiate the detonation, an analog receiving part (10-20) for the conversion of the sonic signals into electrical signals and a digital logic part (22-28) for their further processing being provided, in which the analog receiving part (10-20) has successively a hydrophone (10), a preamplifier (12), a band-pass filter (14), a differential amplifier (16) and a number of parallel-connected selective filters (18, 20) the outputs (MP3, MP4) of which provide signals with a logic level (F1, F2) for processing in the digital logic part (22-28), characterized by the fact that the digital logic part (22-28) is followed by two parallel trigger circuits (34, 38, Thy1, 36, Thy2), which are connected via drivers (30, 32) and which optionally either fire a detonator (38) or disconnect the circuit from a voltage source (40) and short-circuit the said source in which process the logic part (22-28) causes the two discharge circuits (34, 38, Thy1, 36, Thy2), to be actuated at successive time intervals (t₁, t₂, t₃), in accordance with the signal comprising the time-correlated frequencies.

2. A circuit in accordance with Claim 1, characterized by the fact that the analog receiving part (10-20) has two parallel selective filters (18-20) which in their respective filter channels have a tuning fork filter (StG1, StG2 respectively), an emitter follower (T1, T2 respectively), and a Schmitt trigger (T3, T5 and T2, T4 respectively) connected in series.

3. A circuit in accordance with Claim 2, characterized by the fact that the selective filters (18, 20) are decoupled by two resistors (R23, R24) and have piezo-electric tuning fork filters (StG1, StG2) through which the resonance frequency imposed is kept at exactly 1 Hz.

4. A circuit in accordance with any one of Claims 1 to 3, characterized by the fact that the digital logic part (22-28) has a directional signal generator (26) for zeroing the time circuit, a digital time base (22) for generating a time clock pulse and a time window (28) for scanning time- and frequency-correlated coded reception signals (F1, F2).

5. A circuit in accordance with any one of Claims 1 to 4, characterized by the fact that the digital logic part (22-28) has at its output two parallel driver stages (G1, 13, G2, 14) which control respective thyristors (Thy1, Thy2) for firing the detonator (38) or disconnecting the source voltage and discharging the battery (40).

6. A circuit in accordance with any one of Claims 1 to 5, characterized by the fact that the digital logic part (22-28) has a divider (IC6, IC7) and subsequent logic AND gates (G1, G2, G3, 15) which, in succession to one another, block both firing circuits in a first time interval (t₁) and enable the detonator firing circuit (34) and isolate the battery discharge circuit (36) in a second time interval (t₂) and disconnect the detonator ignition circuit (34) and the analog receiving part (10-20) and discharge the battery (40) in a third time interval (t₃).

7. A circuit in accordance with any one of Claims 1 to 6, characterized by the fact that the circuit can be connected to the supply voltage by closing a switch (42) of a water pressure safety device and that in the closing of the switch (42) the digital logic part (22-28) takes up a defined initial state and starts an idle period in the first time interval (t_l).

8. A circuit in accordance with any one of Claims 1 to 7, characterized by the fact that the outputs (13, 14) of the digital logic part (22-28), are connected with gate electrodes of respective thyristors (Thy1, Thy2), and that the latter conduct when a certain defined output signal is present.

9. A circuit in accordance with any one of Claims 1 to 8, characterized by the fact that a transistor (T7) is connected to the gate electrode of the ignition thyristor (Thy1) for the detonator (38) and at the instant when the circuit is switched on it forms a short-circuit section and thus prevents the ignition thyristor (Thy1) from conducting.

10. A circuit in accordance with any one of Claims 1 to 9, characterized by the fact that the entire logic part (22-32) comprises C-MOS components.

11. A circuit in accordance with any one of Claims 1 to 10, characterized by the fact that the source voltage is provided by a lithium battery (40).

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