EP0037556B1 - Verfahren und Einrichtung zur Rahmensynchronisierung eines zusätzlichen Informationssignals bei Pegelteilungsübertragung - Google Patents

Verfahren und Einrichtung zur Rahmensynchronisierung eines zusätzlichen Informationssignals bei Pegelteilungsübertragung Download PDF

Info

Publication number
EP0037556B1
EP0037556B1 EP81102452A EP81102452A EP0037556B1 EP 0037556 B1 EP0037556 B1 EP 0037556B1 EP 81102452 A EP81102452 A EP 81102452A EP 81102452 A EP81102452 A EP 81102452A EP 0037556 B1 EP0037556 B1 EP 0037556B1
Authority
EP
European Patent Office
Prior art keywords
output
logic
counter
intervals
supplementary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP81102452A
Other languages
English (en)
French (fr)
Other versions
EP0037556A1 (de
Inventor
Giusto Pietro Porzio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Original Assignee
CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSELT Centro Studi e Laboratori Telecomunicazioni SpA filed Critical CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Publication of EP0037556A1 publication Critical patent/EP0037556A1/de
Application granted granted Critical
Publication of EP0037556B1 publication Critical patent/EP0037556B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J7/00—Multiplex systems in which the amplitudes or durations of the signals in individual channels are characteristic of those channels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Definitions

  • the present invention relates to digital-transmission systems and, in particular, to a method of frame synchronization of a supplementary information signal added to a main multilevel signal by means of level division multiplexing (LDM), as defined in the prior art portion of claim 1, and to an apparatus as defined in the prior art portion of claim 9, said apparatus being preferred for carrying out the method of claim 1,
  • LDM level division multiplexing
  • LDM technique whose application to the present invention will be described in details hereinafter, can be applied in amplitude modulation systems (AM) as well as in frequency modulation systems (FM), including those AM and FM only partly.
  • Said modulation systems tolerate addition of supplementary modulation levels outside the extreme modulation levels provided for in the main signal. It is known, in fact, that the excursions, of the signal outside the extreme levels otherwise provided for, do not involve a variation of the usual decision thresholds adopted for the main signal, since the waveforms exceeding the extreme level outside the main modulation area remain, with respect to the usual decision threshold, on the same side as the exceeded level, and therefore they are decoded as corresponding to the extreme level exceeded.
  • supplementary information signals by LDM technique is obtained by variations appropriately introduced into the waveforms of the main signal corresponding to extreme levels (modulable waveforms).
  • the supplementary information is extracted at the receiving side by detecting at first the presence of modulable waveforms and then, by means of appropriate supplementary decision thresholds, their possible modifications.
  • TDM time division mutliplexing
  • FDM frequency division multiplexing
  • the basic problem associated with the application of the LDM technique is that of synchronizing the receiving apparatus that is to extract the supplementary information signal.
  • the symbols of the supplementary information signal are transmitted at time instants that are not predetermined but that are random, since they are to be associated with the modulable waveforms of the main stream, that are random-ordered in time.
  • the main information signal consists of a series of waveforms respectively corresponding to digital symbols having a symbol cycle T of a series of the digital symbols representing the information to be transmitted.
  • the system object of the invention can also be applied when: the number of levels of the main information is different from 4; frequency modulation or partial frequency modulation is effected; the supplementary information signal is not necessarily coded in binary symbols.
  • T the mean time interval between the transmission of two successive symbols of a supplementary information signal and bearing in mind that T is the period of the symbol of the main information signal, we will denote by r the ratio between the transmission rates of the two information signals:
  • r must be a rational number.
  • the upper bound of r is represented by the statistical frequency of occurrence of the modulable waveforms.
  • p the probability that such modulable waveforms will be present in a time interval T, we must have, in order to transmit the supplementary information signal, so as to be sure that within a reasonably large number of symbols of the main information signals, we might make use of as many modulable waveforms as are the symbols of the supplementary information signal to be transmitted during a given time that corresponds to said number of main information symbols under consideration.
  • the ..supplementary information signal is transmitted in the following way:
  • Interval NT will be hereinafter referred to as "frame interval" since the operations relating to transmission and reception of supplementary stream are periodically repeated with period NT.
  • GP denotes a standard pulse generator which receives at the input from a wire 10 the train of waveforms associated with the line symbols of the main information signal, and transmits at the output over a wire 9 a pulse in coincidence with any modulable waveform, i.e., a waveform which, according to the already cited principle, may be altered to add a symbol of the supplementary information signal.
  • RS1 denotes a conventional circuit for the recovery of synchronism from the main information signal present on wire 10; RS1 is capable of transmitting, over the output connected to wire 1, a pulse every T seconds.
  • CL3 indicates a conventional cylic counter capable of counting the pulses received at its input over wire 1, to indicate symbol frequency; CL3 is also able to transmit at its output over wire 60 a timing signal at the frame frequency of the supplementary information.
  • SS indicates in a general way the source of supplementary information whose symbol transmission rate is timed by a signal from a delay cell, that will be examined hereinafter, through wire 61. It will be clear from what has already been described that the number of binary symbols sent by SS over a connection 13, during each frame (duration NT) of the supplementary information signal, must be equal to the predetermined number k'.
  • M2 indicates a conventional buffer memory able to temporarily memorize the bits it receives in parallel from the connection 13 in accordance with the timing signal present on wire 60.
  • L3 indicates a conventional delay line able to delay the signal received from wire 60 by a time equal to the handling time required by M2.
  • CC1 denotes a conventional counter able to receive at its input, via wire 9, pulses to be counted starting from the instant in which the counter receives from L3 through wire 61, the delayed signal of frame timing, acting as a reset pulse; counter CC1 supplies, at its output via a connection 59, instant by instant, the total count attained.
  • the maximum count envisaged for CC1 is equal to k+ 1.
  • SE2 denotes a conventional multiplexer which can be switched, by the signal it receives via an input connected to counter CC1, via connection 59, between the wires forming a connection 14 which is connected to another input of the multiplexer.
  • the output of multiplexer SE2 linked to wire 17 provides a logic value "0".
  • GF represents a conventional waveform generator which can receive at a first input connected to wire 10 the main information signal, at a second input connected to wire 9 the pulses transmitted by pulse generator GP1 and at a third input connected to wire 17, the signal coming from multiplexer SE2. As each pulse is received at the second input from generator GP1, GF emits, over the output connected to wire 19, a well-defined waveform whose sign is determined in accordance with the signal received at the first input and whose amplitude is determined in accordance with the signal received at the third input.
  • the amplitude of the waveform generated by GF is equal to zero when a logic level corresponding to binary digital symbol "0" is present at the third input connected to wire 17.
  • L1 indicates a conventional delay line able to delay the signal received from wire 10 by a time equal to the handling time required by the remaining parts of the apparatus.
  • S1 denotes a conventional analog adder which can add the waveform it receives from GF via wire 19, to the waveform of the signal it receives from delay time L1 via a wire 20.
  • Supplied from adder S1 is a signal on a wire 21, which contains both the main information signal and the supplementary information signal.
  • RS2 indicates a conventional synchronism recovery circuit, similar to RS1 shown in Fig. 1, and able to ensure synchronism recovery with the information signal received on wire 22 (Fig. 2).
  • RS2 emits as an output, via a wire 23, a pulse every T seconds.
  • CD indicates a conventional threshold decision circuit which can receive the information signal present on wire 22 and recognize, at a rate determined by the timing signal it receives from RS2 via wire 23, the symbol waveforms of the information signal exceeding a given number of predetermined thresholds.
  • circuit CD is able to detect, within the information signal, the modulable waveforms by comparing the waveforms of said signal with a first pair of thresholds.
  • CD is also able to decide whether said modulable waveforms have been altered by comparing the waveforms of said signal with u second pair of thresholds.
  • Circuit Cd therefore emits a pulse over the output connected to a wire 24 if it has detected a modulable waveform, and emits a pulse over the output connected to a wire 25 if said modulable waveform has been modulated in accordance with a logic value "1".
  • CL4 denotes a conventional cylcic counter capable of receiving a timing signal at its first input connected to wire 23 and a configuration of logic symbols, that serves to determine the duration of its counting cycle, at its second input connected with connection 63; CL4 is capable of emitting over its first output, connected to wire 34, a pulse at each completion of its counting cycle and is also capable of emitting over its second outputs connected to connection 67, a configuration of digital symbols instantaneously corresponding to the attained counting value.
  • L4 represents a conventional delay line able to receive pulses at its input connected to wire 34 and able also to emit them at the output over wire 65 after introduction of a delay equal to about the memorizing time into memory M3, that will be examined later.
  • L5 represents a conventional delay line able to receive pulses at its input connected to wire 24 and able also to emit them at the output over wire 66 after introduction of a delay equal to about the memorizing time of pulses present on wire 25 into memory M3, that will be examined later.
  • CC2 indicates a conventional binary counter, able to receive at its first input connected to wire 66 the pulses to be counted, and to receive at its second input, connected to wire 34, a reset signal: CC2 is able to generate at its output, via a connection 35, a bit configuration indicating the attained counting value.
  • the maximum number of states envisaged for CC2 is k+ 1 (0 to k enclosed).
  • M3 indicates a memory made up of a number of cells equal to k.
  • the writing in the cells of memory M3 is in ordered succession in accordance with timing provided by the signal coming from counter CC2 over connection 35; when connection 35 carries the bit configuration corresponding to the highest count of CC2 none of the cells of M3 is connected for writing so that no further data is written into M3; memorized data is always available at the output of M3 on connection 36; the simultaneous reset of all the cells of M3 is accomplished by a signal from L4 through wire 65.
  • M6 denotes a conventional buffer memory able to receive at its input from connection 36 a binary configuration and to transfer said configuration at the output over connection 50, in correspondence with the pulses of the signal it receives at its second input connected to wire 34.
  • PP indicates a logic circuit of the sequential type, whose operation will be described hereinafter in connection with Fig. 3; depending on the signals it receives at its inputs via wires 35, 67 and via wires 24, 25, 34 PP emits at the output, over a wire 63 a binary configuration that determines the duration of the counting cycle of CL4.
  • P8 denotes a conventional logic AND gate able to receive pulses at its first input connected to wire 25 and also able to emit them at the output via wire 76 when both the signals present on its second and third inputs, connected to wires 71 and 73 respectively, are at logic value "1".
  • P9, P10, P11, P12, P13, P14 denote conventional logic AND gates having two inputs and one output whose operations will be examined hereinafter.
  • LE2 denotes a conventional combinatory logic circuit able to receive at its input from connection 35 a binary configuration corresponding to the counting value attained by CC2 (Fig. 2).
  • LE2 (Fig. 3) is able to emit at its first output connected to wire 71, a logic "0” if the counting value attained by CC2 is less than the number of k supplementary symbols to be transmitted during each frame and to emit a logic "1" if the counting value attained by CC2 is higher than or equal to k.
  • LE2 is also able to emit at a second output connected to wire 72, a logic "1" if the counting value attained by CC2 is equal to 0 or to k-1..
  • LE1 denotes a conventional combinatory logic circuit able to receive a binary configuration at its input from connection 67 and to emit: over its first output, connected to wire 73, a logic "1" only if the input binary configuration corresponds to a number included within a first pre-determined pair of numbers N1, N2, extremes included; to emit over a second output connected to wire 74, a logic "1 ", only if the binary configuration at the input corresponds to a number comprised within a second predetermined pair of numbers N3, N4, extremes included; to emit over a third output connected to wire 75, a logic "1" only if the binary configuration at the input corresponds to a number comprised within a third pre-determined pair of numbers N5, N6, extremes included.
  • F3 indicates a conventional bistable circuit able to emit at its output, over wire 84 a logic "1" acting as enabling signal for gate P 12, after each transition from logic “0" to “1” of the signal it receives at its first input connected to wire 71 and to emit a logic "0” after each pulse it receives at its second input connected to wire 83.
  • F4 denotes a conventional bistable circuit able to emit to its output over wire 81 a logic "1" acting as enabling signal for gate P13, after each pulse it receives at its input connected to wire 79 and able to emit a logic "0" after each pulse it receives at its second input connected to wire 24.
  • L6 and L7 denote two conventional delay lines arranged to introduce a well-defined delay on the signals coming from wires 25 and 24 respectively; the function of said delays will be examined hereinafter.
  • CC3 indicates a conventional counter able to receive at the input from wire 78 the pulses to be counted, starting from the instant when it receives a reset pulse from wire 89, and able also to constantly transfer to its outputs, via connection 91 the attained counting value at each instant.
  • CC4 denotes a conventional up/down counter able to receive at its input: via wire 90 reset pulses, from wire 76 counting up pulses and from wire 77 counting down pulses, able also to constantly transfer to its output, via connection 92, the attained counting value instant by instant.
  • CC5 denotes a conventional up/down counter able to receive at its input from wire 94 reset pulses, from wire 85 counting up pulses (that make it advance) and from wire 82 counting down pulses and able also to constantly transfer to its outputs, on connection 93, the attained counting value at each instant.
  • CL5 denotes a conventional cyclic counter of modulus H5, said value will be described hereinafter, able to receive at its input, via wire 80, pulses to be counted and from wire 95 reset pulses, and able also to transfer to the output on wire 94, a pulse whenever it recovers its initial condition or in dependance of a reset pulse it receives from wire 95 or when its counting cycle is over.
  • CL6 and CL7 denote two counters analogous to CL5, but with different moduli H6, H7 respectively and with their outputs connected to wires 90 and 89 respectively.
  • LC denotes a conventional combinatory logic circuit able to transfer to its output on connection 63 the attained counting value corresponding to the cycle of counter CL4 (Fig. 2) and a logic binary value via wire 96 dependant on the counting value attained by counters CC3, CC4 and CC5 (Fig. 3) it receives at its input from connections 91, 92 and 93 respectively.
  • the correspondence between inputs and outputs is indicated in the following Table:
  • FIG. 4 shows a particular example of the transmission, in a frame interval having duration NT, of a block of ten binary symbols (bit) of a supplementary information signal and consisting of the following succession
  • This succession may be interpreted both as the combination of the information of the 8 bits 00111010 to which two bits "1" have been added at the beginning and at the end in order to make the acquisition of synchronism easier, as it will be seen hereinafter, and as a particular case of a block of ten significant bits of the supplementary information in which the first and the last bits have logic value "1".
  • Signal 1 ( Figures 1 and 4) is a periodic timing signal with period equal to the symbol period T of the main information.
  • Signal 60 serves to time memory M2.
  • Signal 61 serves to reset the counter CC1 and to time source SS.
  • Signal 10 is the waveform assumed for the main information signal; signal 9 is formed by a series of pulses which appear in coincidence with the modulable waveforms of signal 10.
  • Signal 17 carries the block of ten supplementary bits (already examined) to be transmitted in the following way. After each pulse of signal 9, signal 17 takes on the logic value corresponding to the bit of the supplementary information signal to be transmitted in coincidence with the subsequent pulse of signal 9.
  • Signal 19 is the signal representing the supplementary information, to be added to signal 20 which corresponds to the main information signal 10 delayed by a time which in the drawing, is equal to a symbol period of the main information signal.
  • signal 21 represents the signal combining both the main information and the supplementary information, and is present on wire 21 at the output of the transmitting apparatus of Fig. 1.
  • Fig. 5 shows, in a similar manner to that adopted in Fig. 4 the shapes of the signals present on wires 22, 23, 24, 25,66,34,35, 71, 72, 73, 74, 75, 79, 81, 83, 84 of the receiving apparatus (Figs 2 and 3) as a consequence of the reception of the particular block of ten supplementary bits associated with a particular waveform of the main stream, already examined when investigating the transmitting apparatus.
  • waveforms of signals 66, 83 are identical.
  • connection 35 The binary configurations present on connection 35 are represented in Fig. 5, by simply indicating the numbers in decimal notation which are represented by said configurations and correspond to the counts reached by counter CC2 (Fig. 2) at the instants marked by the pulses of signal 24 (Fig. 5); it has been assumed, in accordance with the particular example here described, that said counter has 11 counting positions only and therefore, once number 10 is attained the counter stops.
  • Signal 22 is the received signal, and corresponds to signal 21 shown in Fig. 4;
  • signal 23 (Fig. 5) is the basic clock signal having a frequency equal to the symbol frequency of the main information signal and is derived from RS2 (Fig. 2).
  • Signal 24 (Fig. 5) is formed of a series of pulses which appear in coincidence with the modulable waveforms of signal 22;
  • signal 25 is formed of a series of pulses which appear in coincidence with those modulable waveforms which have been altered by the supplementary modulation of signal 22.
  • Signal 66 is signal 24 delayed by L5 (Fig. 2) and carries the pulses which are to be counted by CC2; signal 34 (Fig. 5) serves for frame synchronism and more particularly performs as a reset signal for CC2.
  • Signals 71, 72, 73, 74, 75, 81, 84 are enabling signals for logic AND gates as will be described later.
  • Signal 79 is signal 25 delayed by L6.
  • Signal 83 whose trend is equal to that of signal 66, acts as reset signal for F3 (Fig. 3).
  • NT counter CL3 In connection with Figs. 1 and 4 in correspondence with the instant of the beginning of the frame interval NT counter CL3 emits a pulse via wire 60. Said pulse controls memorization in M2 of the supplementary block present on connection 13.
  • Said supplementary block delayed by a time equal to processing time of M2, is made available at the output, on connection 14, and may be possibly completed by two bits "1" located at the beginning and at the end.
  • the pulse present on wire 60 is delayed in delay cell L3 by a value equal at least to processing time of M2, but much less than symbol period T, and is emitted via wire 61.
  • the pulse present on wire 61 controls the reset of CC1 and the emission effected by SS of a new bit configuration on connection 13.
  • Counter CC reset by the pulse present on wire 61 positions selector SE2 on the input connected to that particular wire of connection 14, which carries the first bit of the supplementary block; in the particular case examined here said bit has logic value "1" as illustrated at the row 17 of Fig. 4.
  • the first pulse on wire 9 causes in CC1 the count to be advanced by unity and, consequently, according to the bit configuration supplied by CC1 on connection 59, causes the positioning of SE2 on the input linked to a particular wire of connection 14 which carries the second bit of the supplementary block to be transmitted; in this particular case this second bit has logic value "0", as indicated on row 17 of Fig. 4.
  • the second bit of the supplementary block is transmitted, in a similar manner to the transmission of the first bit; the only difference lies on that the logic value "0" in question has been transferred from SE2 on wire 17 to GF which does not generate any waveform, and S1 adds a zero signal to the signal present on wire 20 so that the signal present on wire 20 passes completely unaltered on to the wire 21.
  • the fifth and sixth bits of said supplementary block have logic value "1" but are transmitted by means of the generation in GF of negative pulses; since said bits are transmitted by altering the waveforms corresponding to extreme negative levels of the signal relating to the main information signal according to modulation principles expressed above.
  • selector SE2 emits at its output on wire 17 a logic value "0", being positioned by counter CC1 to an input which supplies a constant logic value "0" provided in a pre-wired form in this example; as already said the logic value "0" transferred from SE2 to its output on wire 17 disables GF for the emission of waveforms so that the signal present on wire 20 passes on to wire 21 without any alteration.
  • the receiving apparatus has been assumed to be already in condition of normal frame alignment, i.e., in a steady state condition, it will be described later how the receiving apparatus has to act to detect the condition of out-of-alignment and to recover the steady state of normal alignment.
  • Circuit RS2 (Fig. 2) derives a timing signal from the signal present on wire 22.
  • This timing signal has a period T equal to the symbol period of the main information signal, and is sent over wire 23 towards circuit CD and counter CL4.
  • CL4 is timed by the signal present on wire 23 to send a pulse every time its counting cycle is over.
  • the duration of said cycle is determined by the bit configuration received by CL4 at its input, connected to connection 63. In a steady state condition the duration of the cycle of CL4 is equal to NT.
  • the pulses present on wire 34 identify the beginning of the frame at the receiving end.
  • the pulse at the beginning of each frame causes CC2 to reset and controls the storage in M6 of the supplementary block received during the preceding frame.
  • Such block in fact, as will be described hereinafter, is present at the input of M6, that is connected to connection 36, and is transferred onto the output over connection 50.
  • the pulse present on wire 34 is delayed in L4 by a time equal at least to the processing time of M6, but much less than symbol period T, and is emitted onto wire 66.
  • the pulse present on wire 65 causes memory M3 to reset.
  • Counter CC2 that has been reset, as described, by the pulse present on wire 34, enables through the binary configuration present on its output connected to connection 35, the first cell of memory M3 to receive a pulse, to be stored, coming from CD through wire 25.
  • Circuit CD depending on the timing signal it receives from RS2 via wire 23 and on the signal it receives via wire 22, recognizes the modulable waveforms, and sends on wire 24 a pulse in coincidence with each modulable wavefrom recognized; in addition, CD sends on wire 25 a pulse in coincidence with each altered modulable waveform modulated by means of a logic value "1 ", as indicated in Fig. 5 on rows 24, 25.
  • the pulses present on wire 24 are delayed in L5 by a time which is equal at least to the memorizing time of M3, but much less than symbol period T, and are emitted over wire 66.
  • Each pulse present on wire 66 causes CC2 to advance by a counting step till CC2 attains the envisaged maximum counting value.
  • the counting reached by CC2 is indicated, instant by instant in binary code by the signals present on connection 35 and addresses step by step the cells of memory M3.
  • the first cell of M3 is addressed first (reset of CC2); then the first pulse present over wire 66 causes the number of counts of CC2 to advance from 0 to 1 causing the second cell of M3 to be addressed; the second pulse of wire 66 will cause the third cell of M3 to be addressed, and so on till the kth cell of M3 is addressed, what happens after the (k-1 )th pulse present on wire 66.
  • the counting value reached by CC2 is equal to k and corresponds to no cell of M3; the content of M3 is no longer altered to the start of the successive frame since, as already stated, the following pulses, CC2 receives from wire 66, do not cause further modifications of its state to the successive reset of CC2.
  • logic circuit PP The operation of logic circuit PP will be now described with references to Figures 2, 3 and 5.
  • Logic circuit LE2 depending on the counting value reached by CC2 and received over connection 35, emits two enabling signals for gates P8 and P9.
  • time intervals i c ' and i c " are provided in which signal 72 has logic value "1".
  • i c ' and i c " there is a time interval in in which, in a steady state condition, the bits of the supplementary block appear with the exception of the extreme bits.
  • Time intervals i c ' and i c " correspond to the time intervals in which the extreme bits of the supplementary block occur.
  • the sum of the intervals i c ' and i c " will be later referred to as i c .
  • Analogously logic circuit LE1 depending on the attained counting value, which hereinafter will be marked by N67, obtained by CL4, which LE1 receives from connection 67, emits, as mentioned, three enabling signals over wires 73, 74, 75 for gates P8, P11, P10 respectively. Said three enabling signals identify three time intervals within the supplementary frame.
  • Said three time intervals can in a general case be contiguous, separate, or partially overlapping according to the characteristics that are specified for the apparatus while planning it. To make the description simpler said time intervals are assumed to be contiguous. Under this assumption the enabling signal for P8 takes on logic value "1" when condition N1 ⁇ N67 ⁇ N2 occurs on the assumption that N1 corresponds to the counting value attained by CL4 in correspondance with the start instant of the supplementary frame and indicating by N2 a number predetermined while- planning the system. The time interval during which gate 8 is enabled, as signals 71 and 73 have logic "1", will be indicated by is hereinafter.
  • the enabling signal for P11 takes on logic value "1" when condition N67 ⁇ N3 occurs, since N3 denotes a number predetermined while planning the system and assumed to be greater than N2, i.e. N3 > N2. Obviously in each frame said enabling signal 74, once it has attained logic “1 ", keeps it to the frame end. The time interval during which signal 74 has logic value "1" will be indicated by ip hereinafter.
  • the enabling signal for P10 takes on logic value "1" where N2 ⁇ N67 ⁇ N3.
  • Reference i c will denote the time interval during which enabling signal 67 has logic value "1".
  • the duration of i o is constant being equal to a predetermined number of count steps of CL4.
  • the duration of the other intervals may vary frame by frame, since the beginning and the end of said intervals are dependent on the occurrence of modulable waveforms.
  • the addition of time intervals i c , i m , i s , i o , i p is equal to the duration of the count cycle of CL4.
  • bistable circuits F3 and F4 that emit enabling signals for gates P12 and P13 respectively, has already been described.
  • Said interval if starts at the end of interval i c " and ends with the occurrence of the first modulable waveform after the beginning of if, but with the delay introduced by L7 (Fig. 3).
  • a time interval denoted by i i (Fig. 5) may be assumed in which the last modulable waveform, occurring before the end of interval ip, occurs.
  • interval i is fictitious, i.e. its beginning and its end are not placed in correspondence with any waveform.
  • a count pulse for counter CC5 is emitted at the output of P13 (Fig. 3) connected to wire 82.
  • Counters CL5, CL6, CL7 count the number of altered modulable waveforms occurring during interval i c .
  • the pulses present on wire 80 are nothing but the pulses emitted by CD on wire 25 that pass through gate P9 when it is enabled.
  • counter CC3 counts the number of altered modulable waveforms occurring during time interval i a .
  • Counter CC4 positively counts (i.e. increases its actual value) the number of altered modulable waveforms occurring during time interval i s and negatively counts (i.e. decreases its actual value) the number of altered modulable waveforms occurring during time interval i p . .
  • Counter CC5 working as already examined in conjunction with F3, F4, L6, L7, P12 and P13 positively counts the number of alternations found out on the last modulable waveform occurring in each frame after the start of time interval i s , and negatively counts the alterations found out on the last altered modulable waveform occurring during each frame before the end of ip.
  • gate P12 is enabled by F3 at the beginning of i s and is disabled by the pulses corresponding to the detection of modulable waveforms coming from wire 24 with a delay, determined by L7, that allows the passage along wire 85 of a pulse that may be present on wire 25.
  • the pulse present on wire 34 (occurring in coincidence with the end of interval i ) can pass onto wire 82 through gate P13, onfy if the preceding modulable waveform was altered too.
  • circuit PP The principles of operation of circuit PP, described in Fig. 3, are based on the comparison of statistical frequencies at which altered modulable waveforms occur in intervals i c , i s , i o , ip.
  • ihterval i c is that in which, in a steady state condition altered modulable waveforms systematically appear, while during intervals i S , i c , i p , in a steady state condition, altered modulable waveforms do not appear unless in presence of transmission errors.
  • counters CC3 and CL7 compare the statistical frequencies of the altered modulable waveforms that may occur in time intervals i c and i o respectively.
  • Modulus H7 of CL7 and threshold value H1, reported in the Table, will be chosen while planning the system so that, under these conditions, the probability that CC3 will reach the counting value H 1, before the attained counting value of CL7 has exceeded H7, is sufficiently low.
  • the counting period of CL4 is outphased with respect to the counting period of CL3 (Fig. 1) by a time period such that the transmitted supplementary block arrives at the receiving end during interval i a .
  • the attained counting value of CL7 (Fig. 3) is incremented only in case of possible transmission errors while the attained counting value of CC3 is incremented during each frame by a number equal to the number of bits having logic value "1", in the transmitted supplementary block.
  • H1 and H7 will be chosen so that, under these conditions, the probability that CC3 will reach the counting value H1, before the attained counting value of CL7 exceeds H7, is very large.
  • the counting cycle of CL4 is lengthened by lengthening ip by the amount S1, that will be chosen while planning the system equal to about the mean number of symbol periods T of the main signal which, in steady state conditions, are contained in the time interval that goes from the central point of i o to the end of i .
  • Counters CC4 and CL6 co-operate in a similar way to detect and correct a possible out-of-alignment state of counter CL4 (Fig. 2) such that the transmitted supplementary block may take place during interval i or during interval i
  • threshold value H2 relating to the number, emitted by CC4 (Fig. 3) on connection 92, and modulus H6 of counter CL6 will be chosen so that in steady state condition the probability that the count number of CL6 exceeds H6, before the count number of CC4 may reach values +H2 or -H2, is high.
  • H6 and H2 will be chosen so that when the supplementary block occurs in the interval i s , there is a high probability that counting value of CC4 may reach H2 before CL6 exceeds value H6.
  • the counting cycle of CL4 is lengthened, by lengthening of time interval i o or of time interval ip, by the amount corresponding to S2, that will be chosen while designing the system to optimize the acquisition time of synchronization conditions.
  • Counter CC5 and CL5 co-operate in a way perfectly analogous to what already examined for pair CC4 and CL6.
  • the threshold values for the attained counting value of CC5 are equal to +H3 and -H3
  • the modulus of counter CL5 is H5 and lengthening and shortening of the counting cycle of CL4 will be equal to value S3.
  • the apparatus, object of the invention is also able to operate even if transmitted supplementary blocks do not systematically have bits with logic value "1" at the beginning and at the end of the supplementary block, but only irregularly.
  • counters CL5, CL6, CL7 no longer systematically increment their attained counting value but they increment it at the statistical frequency of occurrence of bits of logic value "1" at the beginning or at the end of the supplementary block.
  • counter CC3, CC4 and CC5 will be no longer incremented systematically, but depending on the statistics of bits having logic value "1" occurring during the intervals relating to said counters.
  • threshold values for counters CC3, CC4, CC5 and moduli of counters CL5, CL6, CL7 must be sized depending on the statistical frequency at which bits of logic level "1" occur in different positions of the supplementary block.
  • the supplementary block consists of 10 bits, but it can obviously consist of any suitable number of bits. More particularly it can also consist of a single bit, that will have logic value "1" with statistical frequency depending on the characteristics of the information associated to the supplementary stream.
  • interval in will be reduced to zero and intervals i c ' and i c " will coincide.
  • the subdivision can be effected into a different number of intervals causing each of them or a pair of them to correspond to a pair of counters.
  • Each pair of counters together with associated circuits will be able to operate in the ways already examined for the pairs CC3-CL7, CC4-CL6, CC5-CL5.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Claims (15)

1. Verfahren zur Rahmensynchronisation eines zusätzlichen Informationssignals, das innerhalb gegebener Zeitintervalle (zusätzlicher Rahmenintervalle) in Blöcken organisiert wird, beim Senden einem mehrpegeligen Hauptsignal zuaddiert wird, indem die den Extrempegeln entsprechenden Signalbilder (modulierbare Signalbilder) des Hauptsignals mit Hilfe des Pegelteilungsmultiplexierens (LDM) geändert werden, und beim Empfang durch ein entgegengesetztes Vorgehen wieder hergestellt wird, dadurch gekennzeichnet, daß man die Synchronisation der empfängerseitigen Vorrichtung mit der exakten Rahmen-Zeitsteuerung durch Wechsel der Dauer des Zählzyklus bewirkt, der die Zeitsteuerung dieses Rahmens auf der Basis der Anzahl der geänderten modulierbaren Signalbilder tastet, die man innerhalb geeigneter Zeitintervalle (i) feststellt, in die das Rahmenintervall beim Empfang unterteilt wird; daß man die Dauer des Zählzyklus dann verläugert, wenn die Anzahl der geänderten modulierbaren Signalbilder, die nach dem Intervall des Empfangs des zusätzlichen Informationssignals auftreten, größer ist als die Zahl, die sich aufgrund von Übertragungsfehlerstatistiken ergibt; und daß man umgekehrt die Dauer des Zählzylkus dann verkürzt, wenn diese größere Zahl der geänderten modulierbaren Signalbilder vor dem Intervall des Empfangs des zusätzlichen Informationssignals auftritt.
2. Verfahren zur Rahmensynchronisation nach Anspruch 1, dadurch gekennzeichnet, daß man die Blöcke (zusätzliche Blöcke) aus einer gegebenen Zahl zusätzlicher Informationsbits und aus zwei Bits mit dem logischen Wert "1", von denen eines an der Stelle der höchsten Wertigkeit und das andere an der Stelle der niedrigsten Wertigkeit des zusätzlichen Blocks angeordnet wird, aufbaut.
3. Verfahren zur Rahmensynchronisation nach Anspruch 1, dadurch gekennzeichnet, daß man die zusätzlichen Blöcke ausschließlich aus einer gegebenen Zahl von Bits der zusätzlichen Information aufbaut.
4. Verfahren zur Rahmensynchronisation nach Anspruch 3, dadurch gekennzeichnet, daß die zusätzlichen Blöcke aus einem einzigen Bit der zusätzlichen Information bestehen.
5. Verfahren zur Rahmensynchronisation nach Anspruch 1, dadurch gekennzeichnet, daß man im stetigen Zustand bei den Intervallen (i), in die man das zusätzliche Rahmenintervall (NT) beim Empfang unterteilt, drei Serien vorsieht: eine erste Serie aus Intervallen (io, ir) von konstanter und gegebener Dauer; eine zweite Serie (is, ic+in) aus Intervallen veränderlicher Dauer, da deren Anfangzeitpunkt oder Endzeitpunkt in Abhängigkeit von der Feststellung modulierbarer Signalbilder veränderlich ist; und eine dritte Serie aus Intervallen (i' c, i" c, if' il) von derart veränderlicher Dauer, daß eine gegebene Anzahl der modulierbaren Signalbilder, die eine gegebene Zählstellung einnehmen, bei jedem dieser Intervalle dieser dritten Serie auftritt, wobei sich die Intervalle dieser dritten Serie gegebenenfalls mit denen der anderen Serien überlappen können.
6. Verfahren zur Rahmensynchronisation nach den Ansprüchen 1, 5, dadurch gekennzeichnet, daß sich in den Intervallen (i' c, i" c, if, il) der dritten Serie von variabler Dauer ein einziges modulierbares Signalbild je zusätzlichem Rahmen befindet.
7. Verfahren zur Rahmensynchronisation nach den Ansprüchen 1, 5, dadurch gekennzeichnet, daß man bei den Zeitintervallen (i), in die man das zusätzliche Rahmenintervall (NT) beim Empfang unterteilt, drei Gruppen vorsieht: eine erste Gruppe aus zwei Intervallen (i' c, i" c), die zur dritten Serie gehören und so vorbestimmt sind, daß im Zustand der erzielten Synchronisation (stetiger Zustand) die modulierbaren Signalbilder, die die extremen Symbole des zusätzlichen Blocks tragen, auftreten; eine zweite Gruppe aus Intervallen (in), die ebenfalls zur dritten Serie gehören und in denen im stetigen Zustand modulierbare Signalbilder, die die übrigen Symbole des zusätzlichen Blocks tragen, auftreten; und eine dritte Gruppe aus Intervallen (is, io, ip, if, il), von denen jedes irgendeiner der angegebenen Serien angehört und in denen im stetigen Zustand kein modulierbares Signalbild, das Symbole des zusätzlichen Blocks trägt, auftritt.
8. Verfahren zur Rahmensynchronisation nach den Ansprüchen 1, 4, 6, 7, dadurch gekennzeichnet, daß die beiden diese erste Gruppe bildenden Intervalle (i' c, i" c) zusammenfallen.
9. Einrichtung zur Rahmensynchronisation, mit einer Wiederherstellungsschaltung (RS2) für die Symbolfrequenz (1/T) des empfangenen Signals und einer Schwellenentscheidurigsschaltung (CD), die von dieser Symbolfrequenz (1/T) zeitgesteuert ist und einen ersten und einen zweiten Ausgang (24, 25) hat, wobei diese Schaltungen mit einem Schaltungskomplex aus einem ersten Ringzähler (CL4), einem zweiten Zähler (CC2), einem ersten und einem zweiten Speicher (M3, M6) und einer logischen Schaltung (PP) verbunden sind, dadurch gekennzeichnet, daß zur Durchführung des Verfahrens nach Anspruch 1:
- die Schwellen-Entscheidungsschaltung (CD) die den Extrempegeln entsprechenden Signalbilder (modulierbare Signalbilder) des Hauptsignals durch Vergleich dieser Signalbilder mit einem ersten Schwellenpaar und durch Abgeben eines Impulses von einem ersten Ausgang (24) bei jedem erfolgten Erkennen erkennt, und die beim Senden geänderten modulierbaren Signalbilder durch Vergleich dieser modulierbaren Signalbilder mit einem zweiten Schwellenpaar und durch Abgeben eines Impulses auf einen zweiten Ausgang (25) für jedes erkannte geänderte modulierbare Signalbild erkennt;
- der erste Ringzähler (CL4) die Rahmen-Zeitsteuerung in Abhängigkeit von der Symbolfrequenz (1/T), die er von der Wiederherstellungsschaltung (RS2) empfängt, erzeugt und von einem ersten Ausgang (34) einen Impuls bei jeder Vollendung seines Zählzyklus und von einem zweiten Ausgang (67) eine BinärKonfiguration abgibt, die von Zeitpunkt zu Zeitpunkt dem erreichten Zählwert entspricht, und weiterhin die Dauer seines Zählzyklus in Abhängigkeit von einer Konfiguration logischer Symbole ändert, die er von einer sequentiellen logischen Schaltung (PP) empfängt;
- der zweite Zähler (CC2), der ein (k+1 Zustände)-Binärzähler ist, gemäß seiner Schaltung durch einen Impuls, den er vom ersten Ausgang des Ringzähler (CL4) empfängt, zurückstellbar ist und die Impulse zählt, die er über eine erste Verzögerungsstrecke (L5) vom ersten Ausgang (24) der Entscheidungsschaltung (CD) empfängt, und am Ausgang (35) eine von Zeitpunkt zu Zeitpunkt dem erreichten Zählwert entsprechende Binärkonfiguration abgibt;
-der erste Speicher (M3), der aus k Zellen besteht, die vom zweiten Ausgang der Entscheidungsschaltung (CD) kommenden Impulse an den den vom Binärzähler (CC2) abgegebenen Binärkonfigurationen entsprechenden Adressen speichert und durch die Impulse, die or über eine zweite Verzögerungsstrecke (L4) vom ersten Ausgang des ersten Ringzählers (CL4) empfängt, zurückstellbar ist;
-der zweite Speicher (M6) die Binärkonfiguration, die er vom ersten Speicher (M3) in Abhängigkeit von vom ersten Ausgang des ersten Ringzählers (CL4) empfangenen Impulsen empfängt, speichert und sie an den Ausgang der Empfängervorrichtung abgibt;
-die logische Schaltung (PP) sequentiellen Typs ist, den Rahmen (NT) in eine gegebene Anzahl von Intervallen (i) unterteilt, einen Vergleich zwischen den statistischen Frequenzen, zu denen während jedes Intervalls vom zweiten Ausgang der Entscheidungsschaltung (CD) empfangene geänderte modulierbare Signalbilder auftreten, durchführt und als Folge hiervon ausgangsseitig eine Konfiguration logischer Symbole zum Ringzähler (CL4) abgibt.
10. Einrichtung zur Rahmensynchronisation nach Anspruch 9 zur Durchführung des Verfahrens nach einem der Verfahrensansprüche 5 und 7, dadurch gekennzeichnet, daß die logische Schaltung (PP) des sequentiellen Type folgende Hauptbestandteile umfaßt:
-eine erste logische Verknüpfungsschaltung (LE2), die vom Ausgang (35) des Binärzählers (CC2) den erreichten Zählwert empfängt und von ihrem ersten Ausgang (71) eine logische "0" abgibt, wenn der Zählwert niedriger als k ist, und eine logische "1" abgibt, wenn der Zählwert größer oder gleich k ist, und die an ihrem zweiten Ausgang (72) eine logische "1" abgibt, wenn der Zählwert gleich 0 oder k-1 ist;
- eine zweite logische Verknüpfungsschaltung (LE1), die gemäß ihrer Schaltungsanordnung von zweiten Ausgang (67) des ersten Ringzählers (CL4) den erreichten Zählwert empfängt und von ihrem ersten Ausgang (73), von ihrem zweiten Ausgang (74) oder von ihrem dritten Ausgang (75) eine logische "1" abgibt, wenn der Zählwert zwischen zwei ersten Zahlen (N1, N2), zwischen zwei zweiten Zahlen (N3, N4) bzw. zwischen zwei dritten Zahlen (N5, N6), die vorgegeben sind, liegt;
eine erste bistabile Schaltung (F3), die gemäß ihrer Schaltungsanordnung an ihrem Ausgang (84) eine logische "1" abgibt, wenn das Signal, das sie vom ersten Ausgang der ersten logischen Verknüpfungsschaltung (LE2) empfängt, vom logischen Wert "0" zum logischen Wert "1" wechselt, und die eine logische "0" nach jedem Impuls abgibt, den sie über eine dritte Verzögerungsstrecke (L7) vom ersten Ausgang (24) der Schwellen-Entscheidungsschaltung (CD) empfängt, wobei das Vorliegen des logischen Werts "1" am Ausgang (84) ein erstes Zeitintervall (if), das zur dritten Serie und zur dritten Gruppe gehört, identifiziert;
- eine zweite bistabile Schaltung (F4), die an ihrem Ausgang (81) eine logische "1" nach jedem Impuls abgibt, den sie über eine vierte Verzögerungsstrecke (L6) vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) empfängt, und die am Ausgang (81) eine logische "0" nach jedem Impuls abgibt, den sie vom ersten Ausgang (24) der Schwellen-Entscheidungsschaltung (CD) empfängt, wobei das Vorliegen des logischen Werts "1 am Ausgang (81) ein zweites Zeitintervall (i,), das zur dritten Series und zur dritten Gruppe gehört, identifiziert;
-einen ersten Zähler (CC3), der mit einem zweiten Ringzähler (CL7) mit einem Betrag H7 zum Zählen der Impulse zusammenwirkt, die er innerhalb eines dritten Intervalls (io) über ein erstes Tor (P 10), das durch den logischen Wert "l", der vom dritten Ausgang (75) der zweiten Verknüpfungsschaltung (LE1) kommt, durchgeschaltet wird, vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) empfängt, und der an einem Ausgang (91) den von Zeitpunkt zu Zeitpunkt erreichten Zählwert abgibt;
- einen ersten Auf- und Abzähler (CC4), der mit einem dritten Ringzähler (CL6) mit dem Betrag H6 zusammenwirkt und die Impulse abwärtszählt, die er innerhalb eines vierten Intervalls (ip) über ein zweites Tor (P11 ), das durch den vom zweiten Ausgang (74) der zweiten Verknüpfungsschaltung (LE1) kommenden logischen Wert "1" durchgeschaltet wird, vom zweiten Ausgang (25) der Schwellen-Entscheidungsschältung (CD) empfängt, und der die Impulse aufwärtszählt, die er innerhalb eines fünften Intervalls (is) von diesem selben zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) über ein drittes Tor (P8), das in Verbindung mit einer logischen "1", die vom ersten Ausgang (73) der zweiten logischen Verknüpfungsschaltung (LE1) kommt, und durch eine logische "1", die vom ersten Ausgang (71) der ersten logischen Verknüpfungsschaltung LE2) kommt, durchgeschaltet wird, empfängt, und der schließlich am Ausgang (92) den von Zeitpunkt zu Zeitpunkt erreichten Zählwert abgibt;
- einen zweiten Auf- und Abzähler (CC5), der mit einem vierten Ringzähler (CL5) mit dem Betrag H5 zusammenwirkt und der innerhalb eines ersten Intervalls (if) die Impulse aufwärtszählt, die er vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) über ein viertes Tor (P12), das durch eine vom Ausgang (84) der ersten bistabilen Schaltung (F3) kommende logische "1" durchgeschaltet wird, empfängt, und der innerhalb des zweiten Intervalls (il) die Impulse, die er vom ersten Ausgang (34) des ersten Ringzählers (CL4) über ein fünftes Tor (P13), das durch eine vom Ausgang (81) der zweiten bistabilen Schaltung (F4) kommenden logische "1" durchgeschaltet wird, empfängt, und der schließlich auf den Ausgang (93) den von Zeitpunkt zu Zeitpunkt erreichten Zählwert abgibt;
-eine logische Verknüpfungsschaltung (LC), die den Zählwert, den sie vom Zähler (CC3) und vom ersten und vom zweiten Auf- und Abzähler (CC4, CC5) empfängt, dazu verwendet, von einem ersten Ausgang (63) an den ersten Ringzähler (CL4) eine Konfiguration logischer Symbole abzugeben, die den Zyklus des ersten Ringzählers (CL4) bestimmt, und von einem zweiten Ausgang (96) ein Durchschaltsignal für das sechste Tor (P14) abzugeben.
11. Einrichtung zur Rahmensynchronisation nach Anspruch 10, dadurch gekennzeichnet, daß der zweite Ringzähler (CL7), der dritte Ringzähler (CL6) und der vierte Ringzähler (CL5) durch den Impuls zurückgestellt werden, den sie über das durchgeschaltete sechste Tor (P14) vom ersten Ausgang (34) des ersten Ringzählers (CL4) empfangen, und daß die Rückstellung des zweiten, des dritten und des vierten Ringzählers (CL7, CL6, CL5) die Rückstellung des Zählers (CC3) bzw. des ersten Auf- und Abzählers (CC4) bzw. des zweiten Auf- und Abzählers (CC5) bewirkt.
12. Einrichtung zur Rahmensynchronisation nach den Ansprüchen 9 und 10 zur Durchführung des Verfahrens nach Anspruch 2, dadurch gekennzeichnet, daß die logische Schaltung (PP) des sequentiellen Typs den Rahmen (NT) in sieben Intervalle, nämlich ein erstes (if), ein zweites (i,), ein drittes (i ), ein viertes (ip), ein fünftes (is), ein sechstes in) und ein siebtes (ic) Intervall, so unterteilt, daß im stetigen Zustand alle vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) abgegebenen Impulse im sechsten (in) und im siebten (ic) intervall auftreten und die Impulse, wenn keine Übertragungsfehler vorliegen, im ersten (if), im zweiten (il), im dritten (io), im vierten (ip) und im fünften (is) Intervall nicht auftreten, und so, daß im stetigen Zustand im siebten (ic) Intervall die modulierbaren Signalbilder vorliegen, die die Bits des zusätzlichen Blocks, die an den Stellen höchster Wertigkeit und niedrigster Wertigkeit angeordnet sind, tragen.
13. Einrichtung zur Rahmensynchronisation nach den Ansprüchen 9 bis 12, dadurch gekennzeichnet, daß der zweite Ringzähler (CL7) und der erste Zähler (CC3) zum Vergleichen der statistischen Frequenzen der Impulse, die vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) abgegeben werden und im siebten (i") und dritten (0) Intervall auftreten, zusammenwirken.
14. Einrichtung zur Rahmensynchronisation nach den Ansprüchen 9 bis 12, dadurch gekennzeichnet, daß der erste Auf- und Abzähler (CC4) und der dritte Ringzähler (CL6) zum Vergleichen der statistischen Frequenzen der Impulse, die vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) abgegeben werden und im vierten (ip), fünften (is) und siebten (ie) Intervall auftreten, zusammenwirken.
15. Einrichtung zur Rahmensynchronisation nach den Ansprüchen 9 bis 12, dadurch gekennzeichnet, daß der zweite Auf- und Abzähler (CC5) und der vierte Ringzähler (CL5) zum Vergleichen der statistischen Frequenzen der Impulse, die vom zweiten Ausgang (25) der Schwellen-Entscheidungsschaltung (CD) abgegeben werden und im ersten (if), im zweiten (i,) und im siebten (ic) Intervall auftreten, zusammenwirken.
EP81102452A 1980-04-04 1981-04-01 Verfahren und Einrichtung zur Rahmensynchronisierung eines zusätzlichen Informationssignals bei Pegelteilungsübertragung Expired EP0037556B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT6753080 1980-04-04
IT67530/80A IT1128766B (it) 1980-04-04 1980-04-04 Procedimento e dispositivo per la sincronizzazione di trama di un segnale di informazione supplementare trasmesso a divisione di livello

Publications (2)

Publication Number Publication Date
EP0037556A1 EP0037556A1 (de) 1981-10-14
EP0037556B1 true EP0037556B1 (de) 1984-03-21

Family

ID=11303181

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81102452A Expired EP0037556B1 (de) 1980-04-04 1981-04-01 Verfahren und Einrichtung zur Rahmensynchronisierung eines zusätzlichen Informationssignals bei Pegelteilungsübertragung

Country Status (5)

Country Link
US (1) US4376306A (de)
EP (1) EP0037556B1 (de)
CA (1) CA1157593A (de)
DE (1) DE3162736D1 (de)
IT (1) IT1128766B (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2153634B (en) * 1984-02-02 1987-03-25 Plessey Co Plc An arrangement for controlling switched speech or data communication in a communications exchange
DE69031004T2 (de) * 1989-04-02 1997-10-30 Sony Corp Funkübertragungsgerät
FR2652217B1 (fr) * 1989-09-20 1994-02-18 Merlin Gerin Dispositif de transmission synchrone, notamment pour declencheur electronique.
AT401838B (de) * 1990-06-01 1996-12-27 Schrack Telecom Verfahren zur aufbereitung von signalen für die signalübertragung im basisband
KR970003971B1 (ko) * 1994-11-30 1997-03-24 엘지전자 주식회사 위성 방송 수신 시스템에서 동기검출기의 위상 천이 보정 장치
DE19504728A1 (de) * 1995-01-31 1996-08-08 Seebeck Norbert Dipl Ing Verfahren zu komprimieren und dekomprimieren von amplitudenmodulierten Signalen
US5828696A (en) * 1995-03-30 1998-10-27 Lucent Technologies Inc. Timing recovery in a network-synchronized modem
WO1998021847A1 (en) * 1996-11-13 1998-05-22 Nokia Telecommunications Oy Method, transmitter and receiver for transmitting training signals in a tdma transmission system
US6480138B1 (en) 1997-02-11 2002-11-12 Continental Teves Ag & Co. Ohg Method of transmitting data within pulse intervals of a rotational speed signal, and circuit arrangement for implementing the method
DE19714152A1 (de) * 1997-02-11 1998-08-13 Itt Mfg Enterprises Inc Verfahren zur Übertragung von Daten in Pulspausen eines Drehzahlsignales und Schaltungsanordnung zur Durchführung des Verfahrens
IT1320459B1 (it) * 2000-06-27 2003-11-26 Cit Alcatel Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito.
US7206878B2 (en) * 2003-01-08 2007-04-17 International Business Machines Corporation Voltage level bus protocol for transferring data
US8082474B2 (en) * 2008-07-01 2011-12-20 International Business Machines Corporation Bit shadowing in a memory system
US8139430B2 (en) * 2008-07-01 2012-03-20 International Business Machines Corporation Power-on initialization and test for a cascade interconnect memory system
US8201069B2 (en) * 2008-07-01 2012-06-12 International Business Machines Corporation Cyclical redundancy code for use in a high-speed serial link
US8082475B2 (en) * 2008-07-01 2011-12-20 International Business Machines Corporation Enhanced microprocessor interconnect with bit shadowing
US20100005335A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Microprocessor interface with dynamic segment sparing and repair
US7895374B2 (en) * 2008-07-01 2011-02-22 International Business Machines Corporation Dynamic segment sparing and repair in a memory system
US8245105B2 (en) * 2008-07-01 2012-08-14 International Business Machines Corporation Cascade interconnect memory system with enhanced reliability
US8234540B2 (en) 2008-07-01 2012-07-31 International Business Machines Corporation Error correcting code protected quasi-static bit communication on a high-speed bus
US7979759B2 (en) * 2009-01-08 2011-07-12 International Business Machines Corporation Test and bring-up of an enhanced cascade interconnect memory system
US20100180154A1 (en) * 2009-01-13 2010-07-15 International Business Machines Corporation Built In Self-Test of Memory Stressor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3000941A1 (de) * 1979-01-09 1980-07-17 Telecommunications Sa Anordnung zur uebertragung zusaetzlicher informationen fuer eine einrichtung zur uebertragung digitaler daten

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1928986B2 (de) * 1968-06-29 1978-09-21 N.V. Philips' Gloeilampenfabrieken, Eindhoven (Niederlande) Übertragungssystem mit einer Sende- und einer Empfangsvorrichtung zur Übertragung von Informationen in einem vorgeschriebenen Frequenzband und dafür geeignete Sende- und Empfangsvorrichtungen
JPS5034366B1 (de) * 1971-04-30 1975-11-07
FR2217872B1 (de) * 1973-02-12 1976-05-14 Cit Alcatel
DE2330263A1 (de) * 1973-06-14 1975-01-09 Licentia Gmbh Uebertragungs- und vermittlungsverfahren mit hilfe der amplitudenselektion
IT1059489B (it) * 1976-04-22 1982-05-31 C S E L T Spa Sistema per l aggiunta di canali di informazione in una trasmissio ne numerica multilivello
US4243930A (en) * 1979-05-23 1981-01-06 Lynch Communication Systems, Inc. Method and means for transmitting low speed signals over a PCM framing code

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3000941A1 (de) * 1979-01-09 1980-07-17 Telecommunications Sa Anordnung zur uebertragung zusaetzlicher informationen fuer eine einrichtung zur uebertragung digitaler daten
FR2446570A1 (fr) * 1979-01-09 1980-08-08 Telecommunications Sa Procede et dispositif permettant la transmission simultanee d'un signal numerique et d'une onde basse frequence

Also Published As

Publication number Publication date
CA1157593A (en) 1983-11-22
IT8067530A0 (it) 1980-04-04
DE3162736D1 (en) 1984-04-26
US4376306A (en) 1983-03-08
EP0037556A1 (de) 1981-10-14
IT1128766B (it) 1986-06-04

Similar Documents

Publication Publication Date Title
EP0037556B1 (de) Verfahren und Einrichtung zur Rahmensynchronisierung eines zusätzlichen Informationssignals bei Pegelteilungsübertragung
US4131761A (en) Method of and means for conveying and recovering supplementary message signals superimposed upon a multilevel signal stream in a digital transmission system
US3767855A (en) Pulse position modulation communication system
US5557614A (en) Method and apparatus for framing data in a digital transmission line
USRE33900E (en) Error monitoring in digital transmission systems
AU583033B2 (en) Data and voice communications system
JPH0142172B2 (de)
EP0133726B1 (de) Video-Übersetzungssystem zur Übersetzung von numerisch codierten Informationssignalen in Video-Signale und umgekehrt
US4748643A (en) Start bit detecting circuit
CA1266128A (en) Data modulation interface
US2988596A (en) Telegraph system with automatic repetition of mutilated signals
US4398290A (en) Process and apparatus for digital data communication using packet switching
EP0039150A2 (de) Verfahren und Einrichtungen zur Verarbeitung von binären Daten
US5022029A (en) Data transmission method and device
EP0187342B1 (de) Dekodierungsschaltung
US4554669A (en) Frequency jump radiocommunications system with interburst redundancy
CA1203026A (en) Error detection circuitry for digital systems
GB1507093A (en) Arrangements for correcting slip errors in pulse-code transmission systems
US4675545A (en) Wave shaping apparatus for eliminating pulse width distortion
US5619532A (en) Digital communication system
US3646271A (en) Pcm retiming method
WO1984002432A1 (en) Ternary encoding and decoding of digital data
EP0530030A2 (de) Schaltungsanordnung zur Detektion vom Synchronisationssignal in Datenübertragung mit Rahmensynchronisation
US4514852A (en) Process for protected transmission of digital signals
US3159812A (en) Frame synchronization of pulse transmission systems

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB NL

17P Request for examination filed

Effective date: 19811021

TCNL Nl: translation of patent claims filed
DET De: translation of patent claims
TCNL Nl: translation of patent claims filed
GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB NL

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19840419

Year of fee payment: 4

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19840425

Year of fee payment: 4

REF Corresponds to:

Ref document number: 3162736

Country of ref document: DE

Date of ref document: 19840426

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19870430

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19881101

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19881118

GBPC Gb: european patent ceased through non-payment of renewal fee
NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19881229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19890103

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST