Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/005—Control means for lapping machines or devices
  • B24B37/013—Devices or means for detecting lapping completion
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N17/00—Investigating resistance of materials to the weather, to corrosion, or to light
  • G01N17/02—Electrochemical measuring systems for weathering, corrosion or corrosion-protection measurement
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/302—Contactless testing
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/26—Processing photosensitive materials; Apparatus therefor
  • G03F7/30—Imagewise removal using liquid means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31127—Etching organic layers
  • H01L21/31133—Etching organic layers by chemical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
  • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

Definitions

• Linewidth control is important also during device processing levels following resist development. Fabrication depends heavily on etching, and adherence to prescribed tolerances is critical here as well.
• etching when bared results in an increase in current or, alternatively, in a decrease in voltage drop which is sensed to indicate end point.
• the electrical indication yielded by the monitoring wafer is then used to control processing of a plurality of production wafers.
• etch procedure being monitored is development of a widely used positive acting photoresist.
• the material to be removed during etching is primarily a phenol formaldehyde—a novolac— while the fluid is a liquid—aqueous sodium hydroxide developer.
• a preferred embodiment involves use of a ' specifically designed monitoring wafer provided with a plurality of conducting stripes with circuit means for detecting baring of one or some greater number of stripes.
• Useful information which may be derived from this embodiment relates to uniformity of clearing—in turn, dependent on such factors as uniformity of exposure, of resist thickness, of development. Selection of positive resist monitoring as a preferred embodiment is based on exposing monitoring. Since material removed is exposed (rather than unexposed as in negative resist processing) , this variable is inherent in the control data.
• FIG. 1 is a plan view of a specifically designed monitoring wafer usefully employed for monitoring development or other etching of a batch of production wafers;
• FIG. 2 is a sectional view in cross-section of a portion of the structure of FIG. 1;
• FIG. 3 includes a circuit representation and cross-sectional view of a monitoring wafer similar to that of FIG. 2 to result in an also depicted electrical output, in this instance, in terms of voltage-time coordinates;
• FIG. 4 and 5 are plots, the first in coordinates of blanket exposure energy E ⁇ on the ordinate, and clearing time t c on the abscissa; and the second in coordinates of production wafer feature size on the ordinate and development time t D on the abscissa, which are useful for establishing the relationship between end point detection and the desired lithographic dimension as used manually or by computer in a preferred embodiment.
• Etching Removal of material to bare a substrate whether in lithographic- patterning or actual fabrication; contemplated removal is by fluid medium, usually by liquid medium.
• Delineation Material Generic to resist but includes other material to be patterned in the course of which underlying surface of relatively high conductivity is bared to result in intimate contact with etching fluid.
• Delineation material other than resist includes material which is native to underlying surface material such as thermally oxidized silicon oxide, as well as material independent of underlying surface such as CVD-produced silicon nitride. Monitoring of removal of native products generally proceeds by use of a production wafer as a test wafer, although specific monitoring wafers may be used.
• Resist Overlying material imbued with differential ease of removability as usually realized by uniform exposure to a developer by wetting. Resist, as so contemplated, is usually, but not necessarily, sensitive to patterning radiation. Resist material is generally organic or organo-metallic but may be inorganic, as well. Organics are represented by the common novolacs, while inorganics are represented by germanium selenium glasses with insoluble regions defined by silver introduced via photomigration. While resist layers may be retained, they are generally removed after having served to delineate regions to be processed both when used to fabricate separated masks and as used on devices undergoing processing.
• Test Wafer A generic term for a wafer provided with at least a surface region of requisite conductivity which is covered by delineation material of low conductivity relative to such region so that removal of such delineation material by etching results in baring of the region to the etchant, thereby increasing conductivity of a test circuit involving the region and an etching fluid.
• the test wafer may be either a production wafer or a specifically designed monitoring wafer. In either instance, it serves to indicate an etching end point for a batch of production wafers which are not part of the test circuit.
• a wafer provided with one or more conducting regions generally in the form of conducting stripes explicitly designed for test purposes with measurements serving to monitor etching of an accompanying batch of production wafers.
• G_ Production Wafer: A wafer undergoing processing in the concerned stage, by removal of delineation material, to ultimately result in one or more devices.
• device is used in its generic sense as encompassing individual devices, as well as integrated circuits.
• H. Test Circuit A circuit including at least one conducting region on a test wafer as well as etching fluid so that an electrical parameter of the circuit— generally conductivity—is altered upon baring of such region by etching to remove overlying delineation material.
• End Point This term signifies desired termination of processing. Such processing is directed to removal of material to reveal features which are generally continuous over regions to be bared and which are of very closely controlled dimension.
• the end point of a process may correspond with clearing time (i.e., initial clearing of the first or n t-n region on the monitor) but as contemplated does not generally correspond with initial clearing on the production wafer.
• FIG. 1 and 2 The test wafer is exemplified by an explicit monitoring wafer design useful for LSI fabrication.
• Silicon wafer 1 is a standard production wafer, in this instance, 7.62 cm. in diameter by 0.0508 millimeters thick.
• the substrate wafer surface is covered by insulating thermally produced silica (SiC ⁇ ) layer 2 which is, in turn, covered by Si3N 4 layer 3.
• the six conducting paths or stripes 4 are platinum, deposited by sputtering. Complete fabrication of stripes 4 in ⁇ volves first deposition of titanium which acts as a "glue" layer but for these underlying layers are omitted.
• an insulating layer 5 of silicon nitride (SiN) is deposited over the entirety of the now composite surface and is subsequently selectively removed so as to result in openings 6 in layer 5, one near the lower extremity of each stripe 4, and the other at enlarged contact regions of the stripes 4—the latter to permit a clip or wiping connection to complete a circuit external to the etching cell. Removal of nitride to produce openings 6 is by plasma etching. Layer thicknesses shown are exaggerated with layers 2, 3, 4, and 5 of approximate thicknesses 0.5 ⁇ m,.0.08 ⁇ m, 0.06 ⁇ m, and 1.0 ⁇ m, respectively.
• Resist layer 7 may be a novolac positive—acting resist and is identical in composition and in thickness to that on accompanying production wafers to be monitored.
• FIG. 3 is a simple circuit representation which, in effect, is repeated for each of stripes 4.
• a wafer 10 provided with coatings as shown in FIG. 2 immersed in developer 11 to the level shown and clamped in a probe fixture 12 designed to break through the resist in the enlarged region 13 (corresponding with regions 6 of FIG. 1).
• Counter electrode 14 is maintained at a predetermined potential by means of biasing means 15.
• Circuitry external to developer 11 is completed by means of dropping resistor 16 and test lead 17. Initially, there is no electrical connection between the immersed electrode 14 and the conducting path 18 (corresponding with stripes 4 on FIG. 1).
• FIG. 4 and 5 are representative of data developed for calibration purposes for a preferred embodiment in which positive resist development is monitored. This data may subsequently be used in a computerized monitoring circuit to give an automatic cessation of etching (as by removal of production wafers from etchant, e.g. acqueous developer) .
• the plot of FIG. 4 is in coordinates of blanket exposure energy in millijoules/cm 2 (mj/cm 2 ) and clearing time (t c ) . Abscissa units have a typical value of the order of tens of seconds for the mid-point of the curve form.
• Plot 5 is on coordinates of feature size (minimum line width of a cleared line) in micrometers, ⁇ m, and development time.
• FIG. 4 relates to development (or, more generally, etching) of the test wafer, while FIG. 5 is concerned with the production wafer. _3.
• A. Calibration determination of .E p /E ⁇ :
• the procedure contemplated may take a variety of forms. Common to all is a test wafer provided with a layer usually identical in nature to layers undergoing patterning. Under the layer to be patterned, there is at least one region of material, generally more electrically conductive than that of the overlying layer, which, upon being bared, results in an electrical signal. Alternatives include sensing of decreased conductivity upon removal of.relating conductive material as well as sensing of capacitance possibly in terms of a.c. measurement of diminishing thickness of dielectric being etched.
• the electrical signal which may be sensed, in terms of any of a variety of parameters, is directly or indirectly indicative of desired end point.
• the exemplary procedures depend upon a specifically designed monitoring wafer used as a processing control for a batch of production waters.
• the monitoring wafer design is that of FIG. 1, and consists of a silicon substrate of the same size and configuration as that of the production wafers. Isolation of the six platinum stripes is provided by insulation, first by native silica, and, finally, by a thin, deposited Si3N 4 . After fabrication of the stripes, the wafer is covered with a nonconductive SiN layer. The top insulating material is selectively removed in two regions of each stripe. The first is a small region to be exposed to etching fluid and the other is a large region near the edge of the wafer to facilitate electrode connection. In this procedure, the composite platinum-SiN surface is coated with positive novolac photoresist of the type in popular worldwide use in LSI -fabrication. Resist composition, thickness, etc., are identical to resist layers on production wafers to be monitored.
• monitor regions regions to be removed responsive to radiation in the instance of positive photoresist
• regions regions to be removed responsive to radiation in the instance of positive photoresist
• a least dimension of 25 ym which is sufficiently large relative to contemplated radiation wavelength to avoid this complication.
• Resist coated production wafers are exposed at a fixed pattern exposure energy E p , and feature size corresponding with least dimension -of cleared features is determined and plotted for various development times t D .
• the resulting plot is of the form of FIG. 5.
• the choice of desired feature size permits selection of a value of. required blanket exposure Eg for which monitoring wafer clearing time t c equals production wafer development time t D .
• This equivalency is set forth in FIG. 4 and 5 by the vertical broken line joining the two FIGS.
• This graphical determination identifies a unique E p /E B ratio for each step.
• the monitoring wafer is clamped ' to a probe fixture which breaks through the resist in the large insulator-free areas near the edge of the monitoring wafer, thereby making electrical contact to the conducting paths on the wafer.
• the clamped monitoring wafer is lowered into the resist developer with the batch of production wafers to a sufficient depth to expose the lower extremities of- the stripes.
• Probe fixtures which are not immersed are maintained at potential V relative to a counterelectrode, for example, in accordance with the arrangement of FIG. 3. There is no electrical connection between the counterelectrode and the stripes until resist is developed away from the small platinum regions which are not protected by SiN. Upon clearing of each stripe region, an electrical path through the etch fluid is established. This condition is sensed for each stripe, and end point of production wafers being monitored is defined upon clearing of the desired fraction of stripes presented.
• Sensing of the desired stripe may be signalled in any manner or may initiate an automated step, such as withdrawal of the production wafers from the fluid and rinsing.
• the prime example here is a masking layer between the conductive regions and the material to be etched. Minimal openings in such masking layer lessen the likelihood of false readings due to pinholes in the material to be etched.
• Monitoring wafer regions may be of noble metal or other conductive metal which is unaffected in contemplated ambients.
• Conductive regions may be designedly reactive to simulate a corresponding structure in a production wafer—e.g., such region may be silicon which is oxidized in situ to yield an overlying passivating layer which in the production wafer, itself, becomes the material to be etched.
• the measured interval of primary concern may be made to correspond with the initial baring of some conductive region after baring of the first region—e.g., reported work herein includes results obtained by use of the monitoring wafer of FIG. 1 in which "averaging" results from sensing of the third stripe to be bared.
• the etching fluid may be the aqueous alkaline ionic developer commonly used for commercial positive photoresist so that the ionic current generally contemplated is at a readily measurable level.
• Additions may include organic salts or acids, as well as inorganic ionic material.
• Monitoring measurement may proceed across a gaseous or plasma etching fluid.
• the test wafer may be a production wafer with portions of the circuitry themselves serving as sensed conducting regions.
• the production wafer serving as a test wafer may be provided with a specifically designed region serving as monitor.
• Such a "hybrid" production-monitoring wafer may be identical to or different from other production wafers which are in the batch being monitored.
• the monitor region may be unmasked (in terms of design rule dimensions) so that blanket exposure Eg is meaningful in terms, for example, of the discussion relating to FIG. 4 and 5.
• Sensing may be of any electrical parameter which shows a quantum change upon clearing. Examples include AC effects, as well as DC current, DC voltage, and DC capacitance. In the instance of plasma etching, ionic current flow resulting in charging may, itself, be sensed without separate external power supply.

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• 1980
  • 1980-07-28 WO PCT/US1980/000934 patent/WO1981000646A1/en not_active Application Discontinuation
  • 1980-07-28 JP JP50204080A patent/JPS56501226A/ja active Pending
• 1981
  • 1981-03-09 EP EP19800901737 patent/EP0035529A4/de not_active Withdrawn

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