EP0034931B1 - Integrierte Halbleiterschaltung - Google Patents

Integrierte Halbleiterschaltung Download PDF

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Publication number
EP0034931B1
EP0034931B1 EP81300720A EP81300720A EP0034931B1 EP 0034931 B1 EP0034931 B1 EP 0034931B1 EP 81300720 A EP81300720 A EP 81300720A EP 81300720 A EP81300720 A EP 81300720A EP 0034931 B1 EP0034931 B1 EP 0034931B1
Authority
EP
European Patent Office
Prior art keywords
minority carriers
resistors
resistive means
region
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP81300720A
Other languages
English (en)
French (fr)
Other versions
EP0034931A1 (de
Inventor
Shoji Ariizumi
Makoto Segawa
Hisaaki Maiwa
Seishi Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26358237&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0034931(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from JP2120380A external-priority patent/JPS56118363A/ja
Priority claimed from JP8733580A external-priority patent/JPS5712550A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0034931A1 publication Critical patent/EP0034931A1/de
Application granted granted Critical
Publication of EP0034931B1 publication Critical patent/EP0034931B1/de
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components

Definitions

  • This invention relates to semiconductor integrated circuits in which steps are taken to reduce the adverse influences of minority carriers.
  • FIG. 1 illustrates a known N-type channel MOS static random access memory (RAM):
  • This memory is composed of a flip-flop circuit constructed of a pair of inverter circuits 5 and 6 and a pair of transmitting transistors 9 and 10 connected to data lines 7 and 8 respectively.
  • Inverter circuits 5 and 6 have driving transistors 1 and 2 and load resistors 3 and 4.
  • Load resistors 3 and 4 are preferably made from high resistance polycrystalline silicon.
  • This type of RAM is called a four transistor and two resistor RAM.
  • the values of load resistors 3 and 4 are determined by ion implantation in which the impurity is injected into the undoped polycrystalline silicon layer.
  • the resistors 3 and 4 have a negative gradient characteristic with change of temperature so that the resistance becomes lower at high temperatures, increasing the leakage current of the PN junction and the current supply.
  • Load resistors 3 and 4 are ordinarily in the range several MS2 to several hundred MS2 at high temperatures. However the value of load resistors 3 and 4 increases considerably into the G (1000 MQ) range at low temperatures.
  • the leakage current of the PN junction decreases, and the leakage current decreases at a rate much greater than the rate of resistance increase. For example, when the temperature is lowered from 100°C to 25°C, the leakage current decreases by an order of magnitude of 3 to 4, but the value of the resistors increases no more than by a factor of two. Consequently, load resistors 3 and 4 have sufficiently performed to retain the data.
  • FIG. 2 illustrates the effect of the minority carriers on a RAM composed of N-type channel transistors.
  • Transistor T (shown by dotted line) forms part of a peripheral circuit, for example, an input circuit or a self-substrate biasing circuit.
  • Minority carriers (electrons) 11 generated at N+ region 12 diffuse into P-type substrate 13 and reach another N+-type region 14 which is a part of the memory stored "1" level.
  • An object of this invention is to provide an improved semiconductor integrated circuit with decreased electric power consumption and with established high density integration.
  • a semiconductor integrated circuit includes a plurality of memory cells and at least one peripheral circuit which, in use, generates minority carriers, each of said memory cells being in the form of a flip-flop circuit having first and second MOS transistors and resistive means connected to the transistors and serving to store data; at least one, but not all, of the memory cells being positioned relative to the peripheral circuit such that the resistive means of the cell are likely to be influenced by the minority carriers, characterised in that the resistive means of the or each cell which are likely to be influenced by the minority carriers are of a lower value than the resistive means of those cells which are not so influenced such that data stored in said resistive means is not lost.
  • FIG. 3 illustrates a schematic plan view of a memory having memory cells of the type shown in Figure 1.
  • Chip 50 is composed of part 51 containing the memory and part 52 containing peripheral circuits including circuit 53 which generates minority carriers, for example an input circuit, a self-substrate biasing circuit, etc. Since a region A of part 51 is close to part 53, the minority carriers from part 53 can reach region A. Now, the values of the resistors 3 and 4 of the part of the memory in region A are equal and set to R 1 . A region B is located further from part 53 than is region A and the minority carriers do not reach, or at least do not have any influence in, region B. The values of resistors 3 and 4 (shown in Figure 1) of the memories in region B are equal and set to R 2 , and a relation R 1 to R 2 is established between the resistors of the regions A and B.
  • the value of the resistors serving as the load elements in region A is arranged to be lower than in region B and so the destruction of data is prevented. Moreover, use of polycrystalline silicon as the load elements harms high integration. This improvement is accompanied by only a little increase of electric power consumption since region A is much smaller than region B.
  • the memory has a capacity of 1 K bits or 2 K bits, the area of region A is about one-tenth of the total area, for a 64 K or 28 K bit memory the ratio is one to several hundreds.
  • One method of reducing the value of resistors 3 and 4 in region A is additional ion implanting using a photo engraving process (PEP) only in region A when the value of the resistors is determined by the quantity of the impurity of ion implantation. If the value of the resistors is determined by the length of polycrystalline silicon layer not including the impurity, a better method is selective ion implantation only in region A. The values can also be varied by designing the pattern of the resistors.
  • PEP photo engraving process

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Claims (2)

1. Integrierte Halbleiterschaltung bestehend aus mehreren Speicherzellen (14) und mindestens einer peripheren Schaltung (12), die, wenn sie arbeitet und im Betriebszustand ist, Minoritätsträger erzeugt. Jede der vorerwähnten Speicherzellen ist als Flip-Flop-Schaltung ausgeführt, und besteht aus einem ersten und einem zweiten Metalloxid-Silizium-Transistor/ MOS-Transistor (1, 2) sowie aus den schaltungsmäßig mit den Transistoren verbundenen Widerstandsvorrichtungen (3, 4) zum Speichern der Daten. Mindestens eine der Speicherzellen - jedoch nicht alle Speicherzellen - ist im Hinblick auf die periphere Schaltung (12) derart angeordnet, daß die Widerstandsvorrichtungen (3, 4) der Speicherzelle wahrscheinlich von den Minoritätsträgern beeinflußt werden, dadurch gekennzeichnet, daß die Widerstandsvorrichtungen der Zelle oder einer jeden Zelle, die von den Minoritätsträgern beeinflußt wird/werden, einen geringeren Widerstandswert haben als die Widerstandsvorrichtungen der Speicherzellen, die von den Minoritätsträgern nicht beeinflußt werden, so daß die in diesen Widerstandsvorrichtungen gespeicherten Daten nicht verloren werden lönnen.
2. Integrierte Halbleiterschaltung nach Anspruch 1, dadurch gekennzeichnet, daß die Schaltungselemente, die den Widerstand hervorbringen aus gedopten oder dotierten polykristallinen Silizium hergestellt werden.
EP81300720A 1980-02-22 1981-02-20 Integrierte Halbleiterschaltung Expired EP0034931B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2120380A JPS56118363A (en) 1980-02-22 1980-02-22 Semiconductor integrated circuit
JP21203/80 1980-02-22
JP87335/80 1980-06-27
JP8733580A JPS5712550A (en) 1980-06-27 1980-06-27 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
EP0034931A1 EP0034931A1 (de) 1981-09-02
EP0034931B1 true EP0034931B1 (de) 1984-11-21

Family

ID=26358237

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81300720A Expired EP0034931B1 (de) 1980-02-22 1981-02-20 Integrierte Halbleiterschaltung

Country Status (3)

Country Link
US (1) US4399520A (de)
EP (1) EP0034931B1 (de)
DE (1) DE3167256D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740958B2 (en) 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
JPS62154287A (ja) * 1985-12-27 1987-07-09 Hitachi Ltd 半導体メモリ装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2751591A1 (de) * 1976-11-19 1978-05-24 Hitachi Ltd Dynamische speichereinrichtung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279787A (en) * 1975-12-26 1977-07-05 Toshiba Corp Integrated circuit device
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2751591A1 (de) * 1976-11-19 1978-05-24 Hitachi Ltd Dynamische speichereinrichtung

Also Published As

Publication number Publication date
US4399520A (en) 1983-08-16
DE3167256D1 (en) 1985-01-03
EP0034931A1 (de) 1981-09-02

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